University of South Florida Scholar Commons Graduate Theses and Dissertations Graduate School 2006 Low-power flip-flop sinu g internal clock gating and adaptive body bias Jorge Alberto Galvis University of South Florida Follow this and additional works at: http://scholarcommons.usf.edu/etd Part of the American Studies Commons Scholar Commons Citation Galvis, Jorge Alberto, "Low-power flip-flop using internal clock gating and adaptive body bias" (2006). Graduate Theses and Dissertations. http://scholarcommons.usf.edu/etd/2528 This Dissertation is brought to you for free and open access by the Graduate School at Scholar Commons. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Scholar Commons. For more information, please contact [email protected]. Low-Power Flip-Flop Using Internal Clock Gating And Adaptive Body Bias by Jorge Alberto Galvis A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Wilfrido Moreno, Ph.D. Fernando Falquez, Ph.D. James Leffew, Ph.D. Srinivas Katkoori, Ph.D. Hua Cao, Ph.D. Date of Approval: March 28, 2006 Keywords: Clocked Storage Elements, Logical Effort, Spice Simulations, Power Consumption, Clocked Logical Units. © Copyright 2006, Jorge Alberto Galvis ACKNOWLEDGEMENTS I wish to thank Dr. Wilfrido Moreno, my major professor, for his friendship, encouragement and support. Without Dr. Moreno’s support this Ph.D. process would truly not have been completed. I wish to thank Dr. James T. Leffew for his arduous work in the revision and correction of the dissertation document. I wish to thank Dr. Fernando Falquez for his guidance and counseling throughout the process of this dissertation. I wish to thank Dr. Srinivas Katkoori for his guidance and teachings during my years as a graduate student and throughout the process of this dissertation. I wish to thank Dr. Hua Cao for his gentle help in this dissertation. I wish to thank Dr. A. N. V. Rao for his friendly help in this dissertation. I wish to thank my family for their sincere and valuable support. TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ABSTRACT vii CHAPTER 1 BACKGROUND 1 1.1 Power Consumption 1 1.2 Leakage Current 2 1.2.1 pn Junction Reverse-Bias Current 3 1.2.2 Subthreshold Leakage 4 1.2.2.1 Drain-Induced Barrier Lowering, (DIBL) 6 1.2.2.2 Body Effect 7 1.2.2.3 Narrow-Width Effect 8 1.2.2.4 Effect of Channel Length and VTH Rolloff 8 1.2.3 Tunneling Into and Through Gate Oxide 9 1.2.3.1 Fowler-Nordheim (FN) Tunneling 9 1.2.3.2 Direct Tunneling 9 1.2.4 Injection of Hot Carriers from Substrate to Gate Oxide 10 1.2.5 Gate-Induced Drain Leakage 10 1.2.6 Punchthrough 10 1.2.7 Leakage Reduction Techniques 11 1.2.8 Process-Level Leakage Reduction Techniques 11 1.2.8.1 Retrograde Doping 12 1.2.8.2 Halo Doping 12 1.2.9 Circuit-Level Leakage Reduction Techniques 12 1.2.9.1 Transistor Stacking, (Self-Reverse Bias) 13 1.2.9.2 Multiple VTH Designs 13 1.2.9.3 Multiple Channel Doping 14 1.2.9.4 Multiple Oxide CMOS 14 1.2.9.5 Multiple Body-Biases 14 1.2.9.6 Supply Voltage Scaling 18 1.3 Logical Effort 19 1.4 Clocked Storage Elements 22 1.4.1 Latch-Based Clocked Storage Elements, (CSE) 22 1.4.2 Transmission-Gate Flip-Flop, (TGFF) 24 1.4.3 True-Single-Phase-Clock Latch 26 i 1.4.4 Transmission-Gate Flip-Flop with Input Gate Isolation 26 1.4.5 C2MOS Flip-Flop 27 1.4.6 Pulse-Triggered Latches 28 1.4.7 Pulse Register Single Latch 29 1.4.8 Purely Digital Flip-Flop 30 1.4.9 Time Window-Based Flip-Flops 31 1.4.9.1 Semi-Dynamic Flip-Flop, (SDFF) 31 1.4.9.2 Hybrid-Latch Flip-Flop, (HLFF) 32 1.4.10 Differential-Input Differential-Output Flip-Flops 33 1.4.10.1 Sense Amplifier Based Flip-Flop, (SAFF) 33 1.4.10.2 Modified Sense Amplifier Flip-Flop, (modSAFF) 34 1.4.11 Flip-Flops with Internal Clock Gating 36 1.4.11.1 Data-Transition Look-Ahead D Flip-Flop, (DL-DFF) 37 1.4.11.2 Clock-on-Demand Flip-Flop, (COD-FF) 38 1.4.11.3 Conditional-Capture Flip-Flop, (CCFF) 39 1.4.11.4 Gated TGFF, (TGCGFF) 39 1.5 Proposed Desig 41 1.6 Environment Setup 43 CHAPTER 2 METHODS 47 CHAPTER 3 RESULTS 55 CHAPTER 4 CONCLUSIONS 78 REFERENCES 80 APPENDICES 83 Appendix A Simulation Results 84 Appendix B Interface Programs 140 ABOUT THE AUTHOR End Page ii LIST OF TABLES Table 2.1: Fan-out for Each Cell Size 50 Table 2.2: Transistor Sizing for Each Cell 52 Table 3.1: Delay Measurements 56 Table 3.2: Power Consumption Measurements 58 Table 3.3: Total Transistor Area and Area Overhead 60 iii LIST OF FIGURES Figure 1.1: Using the Body Effect through Body-Bias Control 15 Figure 1.2: Global RBB Scheme 16 Figure 1.3: n-well Body-Bias Scheme 16 Figure 1.4: Adaptive Body-Bias Control Structure 17 Figure 1.5: Simple Latch 23 Figure 1.6: Clocked D Latch 23 Figure 1.7: Earl’s Latch 24 Figure 1.8: Conventional Transmission Gate Flip-Flop 25 Figure 1.9: Transmission-Gate Master Slave Latch, Used in the PowerPC 603 Microprocessor 25 Figure 1.10: True Single Phase Clock, (TSPC), Master Slave Latch 26 Figure 1.11: 6-stage Transmission Gate Flip-Flop 27 Figure 1.12: C2MOS Flip-Flop 28 Figure 1.13: Intel Pulsed Latch 29 Figure 1.14: Texas Instruments SN7474 D-type Flip-Flop 30 Figure 1.15: Semi-Dynamic Flip-Flop 32 Figure 1.16: Hybrid-Latch Flip-Flop 32 Figure 1.17: Sense Amplifier Flip-Flop 34 Figure 1.18: Modified Sense Amplifier Flip-flop, (modSAFF) 36 iv Figure 1.19: Data-Transition Look-Ahead D Flip-Flop 37 Figure 1.20: Clock-on-Demand Flip-Flop, (COD-FF) 38 Figure 1.21: Conditional-Capture Flip-Flop, (CCFF) 39 Figure 1.22: Gated TGFF 40 Figure 1.23: Proposed Design 41 Figure 1.24: Test Bench Used for the Simulations 46 Figure 2.1: Flip-Flop Time Measurements 48 Figure 2.2: Procedure Followed in the Comparison of the Flip-flops 49 Figure 2.3: Active Circuit Limiting Clock-Q Delay 50 Figure 3.1: Clock-to-Q delay with D Rising, (cqR) 62 Figure 3.2: Clock-to-Q Delay with D Falling, (cqF) 63 Figure 3.3: D-to-Q Delay with D Rising, (dqR) 64 Figure 3.4: D-to-Q Delay with D Falling, (dqF) 65 Figure 3.5: Power Consumption with 1111 as Input Pattern 66 Figure 3.6: Power Consumption with 0101 as Input Pattern 67 Figure 3.7: Power Consumption with 1001 as Input Pattern 68 Figure 3.8: Power Consumption with 0000 as Input Pattern 69 Figure 3.9: Power Consumption with the Input Pattern Comprised of 20 Ones 70 Figure 3.10: Power Consumption with the Input Pattern Comprised of 50 Ones 71 Figure 3.11: Power Consumption with the Input Pattern Comprised of 100 Ones 72 Figure 3.12: Power Consumption with the Input Pattern Comprised of 20 Zeros 73 Figure 3.13: Power Consumption with the Input Pattern Comprised of 50 Zeros 74 Figure 3.14: Power Consumption with the Input Pattern Comprised of 100 Zeros 75 v Figure 3.15: Power Consumed by the FF During the Total Simulation Period, (FFp) 76 Figure 3.16: Power Consumed by the Test Bench Circuit During the Total Simulation Period, (tbP) 77 vi LOW-POWER FLIP-FLOP USING INTERNAL CLOCK GATING AND ADAPTIVE BODY-BIAS Jorge Alberto Galvis ABSTRACT This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency. A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice. The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison. vii Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area.