A Dual-Mode Synchronous/Asynchronous CORDIC Processor

Total Page:16

File Type:pdf, Size:1020Kb

A Dual-Mode Synchronous/Asynchronous CORDIC Processor A Dual-Mode Synchronous/Asynchronous CORDIC Processor Eckhard Grass, Bodhisatya Sarker and Koushik Maharatna IHP Im Technologiepark 25 15236 Frankfurt (Oder), Germany [email protected] Abstract a frequency correction on the incoming signals. A Coordinate Rotation Digital Computer (CORDIC) offers For application in a software defined radio a CORDIC an elegant way of implementing an NCO. processor has been developed that can operate both in To open a broad market for consumer products, low synchronous and asynchronous mode. Each mode of cost of the required hardware is essential. One way to operation has advantages and drawbacks. Depending on realise low-cost systems is to reduce system complexity the actual application, an optimal trade-off can be and implement all functions of a wireless modem in a achieved by selecting the mode of operation that fits best single chip. Potentially, a single-chip solution is also with system demands. We believe that for a system advantageous in terms of performance and power developer this additional degree of freedom significantly dissipation when compared with multi-chip increases the application space. µ implementations. Fewer signals have to be routed via slow The design has been implemented on a 0.25 m SiGe:C and power-hungry pad drivers. In addition, short BiCMOS process. Simulation results using post-layout interconnections allow faster operation of the system. extracted parameters indicate that the design is µ competitive both with purely synchronous and purely Our in-house 0.25 m SiGe:C BiCMOS technology asynchronous implementations. enables the integration of complex digital baseband functionality together with the analog RF front-end (AFE). This process technology forms the basis for the single-chip 1. Introduction implementation of a complete wireless modem. This single-chip wireless modem will hence comprise analog Fourth generation (4G) wireless and mobile systems circuitry, processor cores as well as dedicated hardware. are currently the focus of research and development. They For the single-chip modem, a number of critical design will allow new types of services to be universally available problems have to be solved. One major issue is the to consumers and for industrial applications. Broadband reduction of crosstalk from the digital part to the analog wireless networks will enable packet based high datarate circuitry. The high energy which is delivered by clock communication suitable for video transmission and mobile drivers can influence the AFE and deteriorate its signal to Internet applications. noise (S/N) ratio. The most predominant crosstalk This paper is based on a project which aims to develop mechanisms are substrate noise, supply voltage variations a single-chip wireless broadband communication system in as well as electro-magnetic effects (EMR) [3]. Secondly, the 5 GHz band, compliant with the Hiperlan/2 [1] and system power dissipation is a critical issue. Since many IEEE 802.11a [2] standards. Both standards specify functional blocks are active for a limited period only, there broadband communication systems using Orthogonal is potential to reduce power dissipation drastically. A Frequency Division Multiplexing (OFDM) with data rates token-flow approach [4] is adopted by adding signals ranging from 6-54 Mbit/s. The duration of one OFDM which indicate the validity of data at inputs and outputs of symbol, which can carry 24 to 216 bits of information is functional blocks. Distributing the control of data flow, 4 µs. For such a system a large portion of the digital this token-flow approach allows easy implementation of baseband processor has to operate on complex signals clock gating and lends itself to asynchronous which are sampled at a rate of 20 MS/s. The most difficult implementations of blocks. to implement functional blocks of the baseband processor Currently a number of extensions to the standards for are FFT/IFFT processor, Viterbi Decoder, and Numeric 5 GHz broadband communication systems are being Controlled Oscillator (NCO). The NCO is used to perform discussed by the standardisation committee. Therefore, it w ou l d b e b e n e f i c i a l f o r c u s t o m e r s a n d s upp li e r s o f t ho s e a nd t h e v ec t o r i n g m od e w h e r e , v a r i a b l e s z a n d y a r e f o r c e d s y s t e m s i f h a r d w a r e w ou l d b e a b l e t o acc o m m od a t e f u t u r e t o ze r o r e s p ec ti v e l y . E ac h o f t h e s e m o d e s ca n b e u tili s e d i n c o mm un i ca ti o n s t a nd a r d s . A s o f t w a r e d e f i n e d r a d i o , i n c i r c u l a r , li n ea r a nd h yp e r bo li c c o o r d i n a t e s y s t e m s . T h i s p r i n c i p a l , o ff e r s t h i s n ee d e d f l e x i b ilit y . ill u s t r a t e s t h e v e r s a tilit y o f t h e C O R D I C a nd e xp l a i n s w hy H e r e w e e x t e nd t h e i d ea o f s o f t w a r e d e f i n e d r a d i o s u c h iti s r e g a r d e d a s on e o f t h e m a j o r t oo l s i n d i g it a l c o m p u t e r t h a t t h e s o f t w a r e d e v e l op e r ca n c ho s e ce r t a i n h a r d w a r e a r it h m e ti c . acce l e r a t o r s t o op e r a t e e it h e r s yn c h r o n ou s l y o r H o w e v e r , f o r o u r p u r p o s e it i s s u ff i c i e n t t o u s e t h e a s yn c h r o n ou s l y . T h i s a dd iti on a l d e g r ee o f fr e e do m r o t a ti on a n d v ec t o r i ng o p e r a ti on s i n t h e c i r c u l a r c oo r d i n a t e i n c r ea s e s t h e a pp li ca ti on s p ace o f t h e c o m p l e t e s y s t e m . s y s t e m on l y . H e n ce w e c o n ce n t r a t e on t h e r ea li za ti on o f a F u r t h e r m o r e , a l s o w it h a g i v e n s t a nd a r d , d i ff e r e n t c i r c u l a r C O R D I C p r o ce ss o r . I t ’ s op e r a ti on r e li e s on t h e a pp li ca ti on s ce n a r i o s r e q u i r e d i f f e r e n t p r o p e r ti e s o f t h e p r i n c i p l e o f v ec t o r r o t a ti on . T h e b a s i c op e r a ti on i s h a r d w a r e . W e a r e c onv i n c e d t h a t h a v i ng t h e fr ee d o m f o r d e s c r i b e d b e l o w : ce r t a i n k e y b l o c k s o f c h o o s i ng b e t w ee n s yn c h r o nou s a n d T h e r o t a ti on o f a v ec t o r [ x0 y 0 ] T i n t h e C a r t e s i a n c o - a s yn c h r o n ou s o p e r a ti on a ll o w s f i n d i ng a s u it a b l e t r a d e - o ff o r d i n a t e s y s t e m ca bn e d e s c r i b e d a s , b e t w ee n po w e r d i ss i p a ti on , c r o ss t a l k , d a t a t h r ou g hpu t , é x 1 ù é cos q sin q ù é x 0 ù l a t e n c y a nd ( s e l f-) t e s t a b ilit y .
Recommended publications
  • Instruction-Level Distributed Processing
    COVER FEATURE Instruction-Level Distributed Processing Shifts in hardware and software technology will soon force designers to look at microarchitectures that process instruction streams in a highly distributed fashion. James E. or nearly 20 years, microarchitecture research In short, the current focus on instruction-level Smith has emphasized instruction-level parallelism, parallelism will shift to instruction-level distributed University of which improves performance by increasing the processing (ILDP), emphasizing interinstruction com- Wisconsin- number of instructions per cycle. In striving munication with dynamic optimization and a tight Madison F for such parallelism, researchers have taken interaction between hardware and low-level software. microarchitectures from pipelining to superscalar pro- cessing, pushing toward increasingly parallel proces- TECHNOLOGY SHIFTS sors. They have concentrated on wider instruction fetch, During the next two or three technology generations, higher instruction issue rates, larger instruction win- processor architects will face several major challenges. dows, and increasing use of prediction and speculation. On-chip wire delays are becoming critical, and power In short, researchers have exploited advances in chip considerations will temper the availability of billions of technology to develop complex, hardware-intensive transistors. Many important applications will be object- processors. oriented and multithreaded and will consist of numer- Benefiting from ever-increasing transistor budgets ous separately
    [Show full text]
  • A Low Power Asynchronous GPS Baseband Processor
    A Low Power Asynchronous GPS Baseband Processor Benjamin Z. Tang, Stephen Longfield, Jr., Sunil A. Bhave, Rajit Manohar School of Electrical and Computer Engineering Cornell University. Ithaca, NY, 14853, U.S.A. Email: {bt48, slongfield}@csl.cornell.edu, [email protected], [email protected] Abstract—We present the design and implementation of an having power consumption of less than 10mW [4]. However, asynchronous Global Positioning System (GPS) baseband pro- more work needs to be done to lower the power consumption cessor architecture designed with a combination of Quasi-Delay- of the GPS baseband processor. Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their A powerful DSP can perform all baseband processing in natural frequency without clocking and all signal processing software [5]. This approach is highly reconfigurable and easy is done on-the-fly. Transistor-level simulations show that our to develop and debug but not suitable for low power applica- system consumes only 1.4mW with position 3-D rms error below tions. An alternative is to use a hardware correlation engine 4 meters, comparing favorably to other contemporary GPS to handle the fast correlation operations and a microprocessor baseband processors. Index Terms—GPS, QDI, Bundled-Data, Asynchronous Cir- to handle the rest of the signal processing tasks [6]. cuits, Low-Power Receiver In applications where the user only requires infrequent position updates, a possible solution is proposed in [7], where I. INTRODUCTION the receiver is only powered intermittently. This approach does A. Motivation not continually track satellites, but instead focuses on rapid re- acqusition.
    [Show full text]
  • Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice
    Clock Gating for Power Optimization in ASIC Design Cycle: Theory & Practice Jairam S, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, Udayakumar H, Jagdish Rao SoC Center of Excellence, Texas Instruments, India (sjairam, bgm-rao, jithendra, pari, uday, j-rao) @ti.com 1 AGENDA • Introduction • Combinational Clock Gating – State of the art – Open problems • Sequential Clock Gating – State of the art – Open problems • Clock Power Analysis and Estimation • Clock Gating In Design Flows JS/BGM – ISLPED08 2 AGENDA • Introduction • Combinational Clock Gating – State of the art – Open problems • Sequential Clock Gating – State of the art – Open problems • Clock Power Analysis and Estimation • Clock Gating In Design Flows JS/BGM – ISLPED08 3 Clock Gating Overview JS/BGM – ISLPED08 4 Clock Gating Overview • System level gating: Turn off entire block disabling all functionality. • Conditions for disabling identified by the designer JS/BGM – ISLPED08 4 Clock Gating Overview • System level gating: Turn off entire block disabling all functionality. • Conditions for disabling identified by the designer • Suspend clocks selectively • No change to functionality • Specific to circuit structure • Possible to automate gating at RTL or gate-level JS/BGM – ISLPED08 4 Clock Network Power JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of – Clock Tree Buffer Power JS/BGM – ISLPED08 5 Clock Network Power • Clock network power consists of – Clock Tree Buffer
    [Show full text]
  • Saber Eletrônica, Designers Pois Precisamos Comprovar Ao Meio Anunciante Estes Números E, Assim, Carlos C
    editorial Editora Saber Ltda. Digital Freemium Edition Diretor Hélio Fittipaldi Nesta edição comemoramos o fantástico número de 258.395 downloads da edição 460 digital em PDF que tivemos nos primeiros 50 dias de circu- www.sabereletronica.com.br lação. Assim, esperamos atingir meio milhão em twitter.com/editora_saber seis meses. Na fase de teste, no ano passado, com Editor e Diretor Responsável a Edição Digital Gratuita que chamamos de “Digital Hélio Fittipaldi Conselho Editorial Freemium (Free + Premium) Edition”, já atingimos João Antonio Zuffo este marco e até ultrapassamos. Redação Fica aqui nosso agradecimento a todos os que Hélio Fittipaldi Augusto Heiss seguiram nosso apelo, para somente fazerem Revisão Técnica Eutíquio Lopez download das nossas edições através do link do Portal Saber Eletrônica, Designers pois precisamos comprovar ao meio anunciante estes números e, assim, Carlos C. Tartaglioni, Diego M. Gomes obtermos patrocínio para manter a edição digital gratuita. Publicidade Aproveitamos também para avisar aos nossos leitores de Portugal, Caroline Ferreira, cerca de 6.000 pessoas, que infelizmente os custos para enviarmos as Nikole Barros revistas impressas em papel têm sido altos e, por solicitação do nosso Colaboradores Alexandre Capelli, distribuidor, não enviaremos mais os exemplares impressos em papel Bruno Venâncio, para distribuição no mercado português e ex-colônias na África. César Cassiolato, Dante J. S. Conti, Em junho teremos a edição especial deste semestre e o assunto prin- Edriano C. de Araújo, cipal é a eletrônica embutida (embedded electronic), ou como dizem os Eutíquio Lopez, Tsunehiro Yamabe espanhóis e portugueses: electrónica embebida. Como marco teremos também no Centro de Exposições Transamérica em São Paulo, a 2ª edição da ESC Brazil 2012 e a 1ª MD&M, o maior evento de tecnologia para o mercado de design eletrônico que, neste ano, estará sendo promovido PARA ANUNCIAR: (11) 2095-5339 pela UBM junto com o primeiro evento para o setor médico/odontoló- [email protected] gico (a MD&M Brazil).
    [Show full text]
  • Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: a Practical Approach∗
    IEICE TRANS. INF. & SYST., VOL.E101–D, NO.4 APRIL 2018 1116 PAPER Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach∗ Carlos Cesar CORTES TORRES†a), Nonmember, Hayate OKUHARA†, Student Member, Nobuyuki YAMASAKI†, Member, and Hideharu AMANO†, Fellow SUMMARY In the past decade, real-time systems (RTSs), which must in RTSs. These techniques can improve energy efficiency; maintain time constraints to avoid catastrophic consequences, have been however, they often require a large amount of power since widely introduced into various embedded systems and Internet of Things they must control the supply voltages of the systems. (IoTs). The RTSs are required to be energy efficient as they are used in embedded devices in which battery life is important. In this study, we in- Body bias (BB) control is another solution that can im- vestigated the RTS energy efficiency by analyzing the ability of body bias prove RTS energy efficiency as it can manage the tradeoff (BB) in providing a satisfying tradeoff between performance and energy. between power leakage and performance without affecting We propose a practical and realistic model that includes the BB energy and the power supply [4], [5].Itseffect is further endorsed when timing overhead in addition to idle region analysis. This study was con- ducted using accurate parameters extracted from a real chip using silicon systems are enabled with silicon on thin box (SOTB) tech- on thin box (SOTB) technology. By using the BB control based on the nology [6], which is a novel and advanced fully depleted sili- proposed model, about 34% energy reduction was achieved.
    [Show full text]
  • Coverstory by Robert Cravotta, Technical Editor
    coverstory By Robert Cravotta, Technical Editor u WELCOME to the 31st annual EDN Microprocessor/Microcontroller Di- rectory. The number of companies and devices the directory lists continues to grow and change. The size of this year’s table of devices has grown more than NEW PROCESSOR OFFERINGS 25% from last year’s. Also, despite the fact that a number of companies have disappeared from the list, the number of companies participating in this year’s CONTINUE TO INCLUDE directory has still grown by 10%. So what? Should this growth and change in the companies and devices the directory lists mean anything to you? TARGETED, INTEGRATED One thing to note is that this year’s directory has experienced more compa- ny and product-line changes than the previous few years. One significant type PERIPHERAL SETS THAT SPAN of change is that more companies are publicly offering software-programma- ble processors. To clarify this fact, not every company that sells processor prod- ALL ARCHITECTURE SIZES. ucts decides to participate in the directory. One reason for not participating is that the companies are selling their processors only to specific customers and are not yet publicly offering those products. Some of the new companies par- ticipating in this year’s directory have recently begun making their processors available to the engineering public. Another type of change occurs when a company acquires another company or another company’s product line. Some of the acquired product lines are no longer available in their current form, such as the MediaQ processors that Nvidia acquired or the Triscend products that Arm acquired.
    [Show full text]
  • Synthesizing FPGA Cores for Software Defined Radio
    SYNTHESIZING FPGA CORES FOR SOFTWARE DEFINE RADIO John Huie (General Dynamics Decision Systems, Scottsdale, Arizona, [email protected]); Price D’Antonio (General Dynamics Decision Systems, Scottsdale, Arizona, price.d’[email protected]); Robert Pelt (Altera Corporation, San Jose, California, [email protected]); Brian Jentz (Altera Corporation, San Jose, California, [email protected]) ABSTRACT modulation and demodulation is performed in the analog domain. The processing power of digital components can The paper describes the integration of two separate now easily perform these operations. The first step in a waveforms (FM and Spread Spectrum) in a new prototype digital radio architecture is to perform the exact analog development of a software define radio. functions in the digital domain. This can be done in three The FM modulator and demodulator were integrated ways: 1) perform the signal processing as software on a soft into one signal processing core capable of performing the core general purpose processor (GPP) or on a soft core modulation and demodulation of a 5Khz audio signal. digital signal processor (DSP), 2) perform the signal Waveform processing for the Spread Spectrum processing as hardware implemented as firmware in the Waveform (SSW) proved to be a challenge due to the wide FPGA, or 3) perform the signal processing as a micro- bandwidth of the waveform, and due to the high signal sequenced co-processor supporting specialized instructions processing requirements for high data rates greater than for the DSP. 10Mbps. Since the waveform is going through Antenna Low Noise Demodulator evolutionary change during its development cycle, the Amplifier Filter prototype design meets both current waveform requirements User and maintains sufficient flexibility to accommodate VCO VCO Interface, additional processing and evolution of the waveform.
    [Show full text]
  • Interfacing the MC13783 Power Management IC with I.MX31 Applications Processors By: Power Management and I.MX31 Application Teams
    Freescale Semiconductor Document Number: AN3276 Application Note Rev. 0.3, 01/2010 Interfacing the MC13783 Power Management IC with i.MX31 Applications Processors by: Power Management and i.MX31 Application Teams 1 Introduction Contents 1 Introduction . 1 The purpose of this application note is to provide 2 Power Management Basics . 2 information for the development of the power 3 MC13783 Overview . 3 management section of a product that incorporates an 4 i.MX31 Overview . 6 i.MX31 processor or similar processor and a power 5 Interconnection . 11 management IC (PMIC) such as the MC13783. 6 Control and Other Considerations . 17 7 Revision History . 21 The i.MX31 applications processors incorporate numerous features to enhance use time and battery life by reducing power consumption. These features include: • Power gating • Variety of low power modes • Smart techniques for short wake-up time from low power modes • Dynamic Process Temperature Compensation (DPTC) • Automatic Dynamic Voltage and Frequency Scaling (DVFS, sometimes shortened to DVS for Dynamic Voltage Scaling) • Low-power clocking scheme • Active Well Bias (AWB) © Freescale Semiconductor, Inc., 2006–2010. All rights reserved. Power Management Basics Some of these features are implemented entirely within the i.MX31; others such as dynamic voltage scaling, dynamic process temperature compensation of voltage and power gating require the use of a power management device designed with i.MX31 in mind. Freescale’s MC13783 power management IC is designed with all of the power management, logic and audio features needed for an advanced 3G cell phone or other portable devices using the i.MX31 as an applications processor.
    [Show full text]
  • Register Allocation and VDD-Gating Algorithms for Out-Of-Order
    Register Allocation and VDD-Gating Algorithms for Out-of-Order Architectures Steven J. Battle and Mark Hempstead Drexel University Philadelphia, PA USA Email: [email protected], [email protected] Abstract—Register Files (RF) in modern out-of-order micro- 100 avg Int avg FP processors can account for up to 30% of total power consumed INT → → by the core. The complexity and size of the RF has increased due 80 FP to the transition from ROB-based to MIPSR10K-style physical register renaming. Because physical registers are dynamically 60 allocated, the RF is not fully occupied during every phase of the application. In this paper, we propose a comprehensive power 40 management strategy of the RF through algorithms for register allocation and register-bank power-gating that are informed by % of runtime 20 both microarchitecture details and circuit costs. We investigate algorithms to control where to place registers in the RF, when to 0 disable banks in the RF, and when to re-enable these banks. We 60 80 100 120 140 160 include detailed circuit models to estimate the cost for banking Num. Registers Occupied and power-gating the RF. We are able to save up to 50% of the leakage energy vs. a baseline monolithic RF, and save 11% more Fig. 1. Average Reg File occupancy CDF for SPEC2006 workloads. leakage energy than fine-grained VDD-gating schemes. 1 1 Index Terms—Computer architecture, Gate leakage, Registers, SRAM cells 0.8 0.8 I. INTRODUCTION 0.6 0.6 F.cactus I.astar 0.4 0.4 Out-of-order superscalar processors, historically found only F.gems I.libq in high-performance computing environments, are now used in F.milc I.go 0.2 F.pov 0.2 Imcf a diverse range of energy-constrained applications from smart- F.zeus Iomn phones to data-centers.
    [Show full text]
  • (12) United States Patent (10) Patent No.: US 8,102.202 B2 10
    USOO81022O2B2 (12) United States Patent (10) Patent No.: US 8,102.202 B2 Wurth (45) Date of Patent: Jan. 24, 2012 (54) MODEM UNIT AND MOBILE (56) References Cited COMMUNICATION UNIT U.S. PATENT DOCUMENTS (75) Inventor: Bernd Wurth, Landsberg am Lech (DE) 5.335,276 A * 8/1994 Thompson et al. ........... 380.266 5,638,540 A * 6/1997 T13,300 (73) Assignee: Innon Technologies AG, Neubiberg 5,974,5285,809,432 A * 10/19999/1998 YamashitaTsai et al. ................. 455,575..1 (DE) 6,380,031 B1 4/2002 Mehrad et al. 7,162,279 B2 * 1/2007 Gupta ........................... 455,574 (*) Notice: Subject to any disclaimer, the term of this 7.281,144 B2 * 10/2007 Banginwar et al. T13,320 patent is extended or adjusted under 35 73s E: 33 S.aSC halkOWSKI ki etalca. ... 229. U.S.C. 154(b) by 739 days. 2002/0083432 A1* 6/2002 Souissi et al. ................. 717/178 2008/0104428 A1* 5/2008 Nafziger et al. ............. T13,300 (21) Appl. No.: 12/190,183 * cited by examiner (22) Filed: Aug. 12, 2008 Primary Examiner — David Mis (74) Attorney, Agent, or Firm — Eschweiler & Associates, (65) Prior Publication Data LLC US 2010/00401 24 A1 Feb. 18, 2010 (57) ABSTRACT (51) Int. Cl. A modem unit includes a first semiconductor die that includes H04L27/00 (2006.01) ARASE (52) U.S. Cl. ........ ".- - - - - - - - 329/311; 332/106; 375/222 on a first semiconductor die. The first semiconductor die also (58) Field of Classification Search .................. 329/300, includes a power management unit and an embedded flash 329/304,311: 332/100, 103, 106; 375/222, memory.
    [Show full text]
  • A 65 Nm 2-Billion Transistor Quad-Core Itanium Processor
    18 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 1, JANUARY 2009 A 65 nm 2-Billion Transistor Quad-Core Itanium Processor Blaine Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul Gronowski, Dan Krueger, Charles Morganti, and Steve Troyer Abstract—This paper describes an Itanium processor imple- mented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operates at 2.4 GHz at 105 C. High speed serial interconnects allow for peak processor-to-processor bandwidth of 96 GB/s and peak memory bandwidth of 34 GB/s. Index Terms—65-nm process technology, circuit design, clock distribution, computer architecture, microprocessor, on-die cache, voltage domains. I. OVERVIEW Fig. 1. Die photo. HE next generation in the Intel Itanium processor family T code named Tukwila is described. The 21.5 mm by 32.5 mm die contains 2.05 billion transistors, making it the first two billion transistor microprocessor ever reported. Tukwila combines four ported Itanium cores with a new system interface and high speed serial interconnects to deliver greater than 2X performance relative to the Montecito and Montvale family of processors [1], [2]. Tukwila is manufactured in a 65 nm process with 8 layers of copper interconnect as shown in the die photo in Fig. 1. The Tukwila die is enclosed in a 66 mm 66 mm FR4 laminate package with 1248 total landed pins as shown in Fig.
    [Show full text]
  • EN 300 798 V1.1.1 (1997-06) European Standard (Telecommunications Series)
    Draft EN 300 798 V1.1.1 (1997-06) European Standard (Telecommunications series) Digital Audio Broadcasting (DAB); Distribution interfaces; Digital baseband I/Q interface European Broadcasting Union Union Européenne de Radio-Télévision 2 Draft EN 300 798 V1.1.1 (1997-06) Reference DEN/JTC-00DAB-6 (7e000ico.PDF) Keywords DAB, digital, audio, broadcasting, interface ETSI Secretariat Postal address F-06921 Sophia Antipolis Cedex - FRANCE Office address 650 Route des Lucioles - Sophia Antipolis Valbonne - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N° 348 623 562 00017 - NAF 742 C Association à but non lucratif enregistrée à la Sous-Préfecture de Grasse (06) N° 7803/88 X.400 c= fr; a=atlas; p=etsi; s=secretariat Internet [email protected] http://www.etsi.fr Copyright Notification No part may be reproduced except as authorized by written permission. The copyright and the foregoing restriction extend to reproduction in all media. © European Telecommunications Standards Institute 1997. © European Broadcasting Union 1997. All rights reserved. 3 Draft EN 300 798 V1.1.1 (1997-06) Contents Intellectual Property Rights................................................................................................................................4 Foreword ............................................................................................................................................................4 Introduction ........................................................................................................................................................5
    [Show full text]