Synthesizing FPGA Cores for Software Defined Radio

SYNTHESIZING FPGA CORES FOR SOFTWARE DEFINE RADIO John Huie (General Dynamics Decision Systems, Scottsdale, Arizona, john.huie@gdds.com); Price D’Antonio (General Dynamics Decision Systems, Scottsdale, Arizona, price.d’antonio@gdds.com); Robert Pelt (Altera Corporation, San Jose, California, rpelt@altera.com); Brian Jentz (Altera Corporation, San Jose, California, bjentz@altera.com) ABSTRACT modulation and demodulation is performed in the analog domain. The processing power of digital components can The paper describes the integration of two separate now easily perform these operations. The first step in a waveforms (FM and Spread Spectrum) in a new prototype digital radio architecture is to perform the exact analog development of a software define radio. functions in the digital domain. This can be done in three The FM modulator and demodulator were integrated ways: 1) perform the signal processing as software on a soft into one signal processing core capable of performing the core general purpose processor (GPP) or on a soft core modulation and demodulation of a 5Khz audio signal. digital signal processor (DSP), 2) perform the signal Waveform processing for the Spread Spectrum processing as hardware implemented as firmware in the Waveform (SSW) proved to be a challenge due to the wide FPGA, or 3) perform the signal processing as a micro- bandwidth of the waveform, and due to the high signal sequenced co-processor supporting specialized instructions processing requirements for high data rates greater than for the DSP. 10Mbps. Since the waveform is going through Antenna Low Noise Demodulator evolutionary change during its development cycle, the Amplifier Filter prototype design meets both current waveform requirements User and maintains sufficient flexibility to accommodate VCO VCO Interface, additional processing and evolution of the waveform. Switch Audio, Etc Power Modulator 1. BACKGROUND Amplifier Filter The concept of a Software Defined Radio (SDR) has Move from Analog to been around for more than 10 years. The ability to perform VCO VCO Digital Processing field upgrades and reconfiguration of waveforms has a large Figure 1: FM Radio Architecture benefit to the military community. But, only recently has The customary signal processing implementation is to semiconductor technology evolved to make SDR possible. use a microprocessor (or DSP) to perform the radio Typical architectures implement waveforms in the digital functions. This allows the waveform developer to use a domain using Microprocessors, FPGAs, and DSP standard software language, and remain hardware Processors. This paper focuses on implementation using a independent. However, a DSP has limitations in single FPGA. FPGAs have specific features that enable performance that restrict DSP solutions to relatively high performance SDR implementation while retaining cost narrowband waveforms. AN FPGA based solution allows effectiveness. These include: high-bandwidth memories, flexibility to achieve a high degree of parallelism in signal embedded DSP Blocks, phase-locked loops (PLL), general processing, whether using multiple soft core processors or purpose processors (GPP) and high-speed interfaces. In using firmware based coprocessors to substantially addition, soft core processors plus FPGA co-processors outperform DSP based implementations of waveforms. enable reconfiguration of the digital waveforms. 3. PROCESSOR BASED DEMODULATION 2. DIGITAL RADIO ARCHITECTURE Figure 2 shows a typical radio system using a microprocessor (or DSP) as the baseband processor. In this Figure 1 shows a figure of a common FM radio case the processing is performed by a ‘soft core’ architecture. In traditional radio architectures, all of the FM microprocessor. Soft Core processors are built using the Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved generally available resources in an FPGA. Typically these When the processing power needed exceeds that of the processors can provide 100 – 150 Dhrystone MIPS soft core approach, co-processing elements can be added. (DMIPS). This is enough processing power to perform DSP Builder tool is tightly coupled with Matlab Simulink, modulation and demodulation for low bandwidth signals. which provides system level behavior that generates HDL Furthermore, currently available FPGAs can support from 2 code targeted to a specific family of FPGA devices. Figure to 50 soft core processors depending on the size of the 3 shows an example of the same FM radio that uses a FPGA selected. The System on Programmable CORDIC (COordinate Rotation DIgital Computer) co- Configuration (SOPC) Builder allows the user to build processor. The CORDIC co-processor implements a vector custom instructions for the soft core processors, improving rotation engine that can be used to calculate trigonometric the performance of the processors to meet future growth of waveforms for the software defined radio. Low Noise Antenna Amplifier Filter Digital-to- Soft Core Analog Processor Interface (Modulation, VCO VCO Demodulation, Switch Analog- User Interface to-Digital Power Amplifier Memory Filter FPGA-based Soft Core Processor VCO VCO Figure 2: Processor Based FM Radio NCO Low Noise Amplifier CORDIC Filter Co-processor Digital-to- Soft Core VCO Analog Processor Switch Interface Buffer (Modulation, Analog- Demodulation, to-Digital User Interface Filter Power Memory Amplifier NCO FPGA-based Digital IF and Baseband Processing VCO Figure 3: FM Radio with Digital IF functions [1]. In the case of FM, the CORDIC provides the radio architecture with IF processing. In this arctangent function needed to demodulate FM waveforms. implementation the VCO (Voltage Controlled Oscillator) is Table 1 shows typical performance of soft core processors replaced with an NCO (Numerically Controlled Oscillator). and CORDIC co-processors. The analog filtering functions are now replaced by digital Table 1: FM Radio Components FIR (Finite Impulse Response) filters. The Soft Core processor (along with the CORDIC co-processor) still Function Speed Resources performs the baseband processing functions. The Soft Core Soft Core (Altera NIOS) 100 MHz 1500 LE processor can also support adaptive changes of the IF CORDIC 219 MHz 966 LE performance. For example, the Soft Core processor can update the output frequency of the NCO, or change the 4. DIGITAL IF PROCESSING coefficients of the FIR Filter. Today’s FPGAs are capable of supporting IF FPGAs are capable of more than baseband modulation sampling rates up to 150 MHz. and demodulation. Today’s advanced FPGAs have the Table 2 shows some utilization and clock rates for the IF capability to provide IF (Intermediate Frequency) processing processing functions. as well as baseband processing. Figure 2 shows the FM Utilizations based on Altera’s Stratix FPGA Family are: Proceeding of the SDR 03 Technical Conference and Product Exposition. Copyright © 2003 SDR Forum. All Rights Reserved NCO Low Noise CORDIC Co-processor Amplifier FIR CIC Convolutional Spreader Memory Encoder Digital-to- VCO Analog Soft Core Switch Processor Analog- Interface to-Digital De- RAKE Viterbi FFT Spread Receiver Decoder Power Amplifier CIC FIR FPGA-based Digital IF and Baseband Processing NCO VCO • LE: Logic Element, basic element of an FPGA • MSPS: Million Samples Per Second • Mult: The number of 18x18 Multipliers used • Note: Resources based on [2], [3] • M4K: Embedded 4 Kbit memories Figure 4: SSW Implementation Table 2: Digital IF Components 5. IMPLEMENTING SPREAD SPECTRUM WAVEFORM (SSW) Function Speed Resources (LE/Mult/M4K) The concept of ‘co-processing’ can be extended to support Parallel FIR 244.26 MSPS* 1375 / 0 / 30 more computationally intensive waveforms, like the SSW (48 taps, 14-bit) waveform. Table 3 shows that the waveform requires Serial FIR 19.33 MSPS* 360 / 0 / 6 processing rates that are far beyond the reach of traditional (48 taps, 14-bit) microprocessors. Co-processing components increases NCO (24-bit) 278.78 MHz 67 / 8 / 12 performance requirements and provides additional CIC (6th order, 14- 200 MHz 1138 / 0 / 0 computational resources when needed to alleviate software bit) overhead and minimize event cycles in order to reduce power consumption. diagram of the SSW implementation in an FPGA. In this FFT* (8192 ppt) 38.73 _sec 8388 / 18 / 176 implementation, most of the waveform processing is Viterbi Decoder 11 Mbps 1801 / 0 / 0 performed by co-processing components. Each of the co- * Two Radix 4 Engines, 16-bit operation processing components are generated by DSP Builder ** Constraint length = 7, number ACS = 8 through Matlab Simulink. A high level model of the co- Note: Resources based on [4], [5] processing components are simulated in Matlab Simulink. In Simulink, the co-processing components have their own 6. SYSTEM IMPLEMENTATION built-in compiler to generate a RTL (Register Transfer Level) model for simulation in Modelsim with its associate The software defined radio (SDR) form factor drives test bench stimulus. The Simulink models of the co- power requirements for the design. The SDR system processing components are FPGA centric such that it takes comprises of two modules, the digital baseband module and advantage of the hardware architecture for a given family of the RF module. The antenna and Human Machine Interface FPGA devices. But, as in the FM case, the Soft Core (HMI) are part of the chassis frame that enclose the RF and processor performs the initialization, parameterization, Digital module.

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