A Low Power Asynchronous GPS Baseband Processor
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A Low Power Asynchronous GPS Baseband Processor Benjamin Z. Tang, Stephen Longfield, Jr., Sunil A. Bhave, Rajit Manohar School of Electrical and Computer Engineering Cornell University. Ithaca, NY, 14853, U.S.A. Email: {bt48, slongfield}@csl.cornell.edu, [email protected], [email protected] Abstract—We present the design and implementation of an having power consumption of less than 10mW [4]. However, asynchronous Global Positioning System (GPS) baseband pro- more work needs to be done to lower the power consumption cessor architecture designed with a combination of Quasi-Delay- of the GPS baseband processor. Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their A powerful DSP can perform all baseband processing in natural frequency without clocking and all signal processing software [5]. This approach is highly reconfigurable and easy is done on-the-fly. Transistor-level simulations show that our to develop and debug but not suitable for low power applica- system consumes only 1.4mW with position 3-D rms error below tions. An alternative is to use a hardware correlation engine 4 meters, comparing favorably to other contemporary GPS to handle the fast correlation operations and a microprocessor baseband processors. Index Terms—GPS, QDI, Bundled-Data, Asynchronous Cir- to handle the rest of the signal processing tasks [6]. cuits, Low-Power Receiver In applications where the user only requires infrequent position updates, a possible solution is proposed in [7], where I. INTRODUCTION the receiver is only powered intermittently. This approach does A. Motivation not continually track satellites, but instead focuses on rapid re- acqusition. Our lives are increasingly being affected by the use of This work focuses on addressing the power consumption GPS technology. We rely on GPS to navigate from one place issue in the baseband processor when continuous position to another, to locate a person or an object, to provide time information is required. Instead of using a single DSP or a synchronization in our telecommunication networks and power correlation engine with software support to perform baseband grids, and in many other every day applications. processing, we designed a hybrid architecture that decouples Today, high power consumption of existing GPS receiver crucial GPS receiver operations from other post-processing chips can cause overheating issues, and can limit continuous that can either be managed locally by a co-processor or be GPS operation in mobile devices. It is clear that the high power separately managed by the cloud or base station. consumption in GPS receivers must be addressed to pave the Our system performs all baseband processing on-the-fly in way for advances in areas such as location-aware applications hardware, leaving only initialization and navigation solution and micro robotics navigation. computation to software. This approach not only provides an Asynchronous techniques enable very low-power designs, optimized hybrid hardware and software solution but is also especially in systems where the rate of required throughput ideal for applications that need to deploy ultra-low-power mo- may vary over time [1], [2], [3]. As a GPS system involves bile GPS receivers that transmit just enough information back several different components, each of which compute at a to a base station to compute its position and time information. different natural frequency, an asynchronous design could lead Moreover, our clockless data-flow driven baseband processor to benefits in power consumption for baseband processing. can be paired with any conventional GPS L1 RF front end. It A typical GPS receiver consists of an RF front end and is programmable to support different front end sampling and a digital signal processor (DSP). The RF front end receives intermediate frequencies and mixing scheme. the GPS signal from the satellites, mixes it down to an intermediate frequency, and samples it. The DSP acquires a II. GPS SIGNAL STRUCTURE lock to multiple GPS satellite signals present in the front end samples and tracks variations in the signals over time. The GPS uses spread-spectrum signaling to modulate a While the DSP tracks variations in the signal, it also extracts carrier with ranging codes. This technique allows a GPS information from it that can be used to compute the current receiver to use Code Division Multiple Access (CDMA) to position and time—the “navigation solution.” uniquely identify the signal from each satellite by the satellite’s unique ranging code. Modern GPS satellites transmit signals at B. Related Work the L1, L2 and L5 carrier frequencies with civil and military Significant research effort has been devoted to reducing the codes. Since our system is designed to process the L1 civil power consumption of the RF front end, with current designs signal, we will describe its signal structure here. Muxing-demuxing circuits 1575.42MHz L1 carrier MAG math GPS satellite 1.023MHz C/A code, x(t) Channel 5 transmitted signal, Channel 4 sL1 (t) Channel 3 Channel 2 Channel 1 MAG output Channel 0 MAG input Front Demux control 50bps navigation data, D(t) end samples, IP, acq r Acquisition-track L1 QP, acq Fllplldll control IE I IP, fll bus Fig. 1. GPS L1 C/A signal structure Q P, fll-pll Muxing-demuxing circuits E FLL- QP, fll PLL IP QP, fll-pll IP, pll rL1 switch Accumulators QP, pll rL1 cos QP FLL- FLL- IE, dll PLL- PLL- r sin Carrier L1 IL QE, dll DLL DLL Ctrl IL, dll control math NCO Dump QL The GPS L1 Coarse/Acquisition (C/A) signal consists of QL, dll IP, extract Fllplldll updates a 1575.42MHz L1 carrier signal modulated by a periodic xE xP xL E P L Shift 1023-chip C/A ranging code at 1.023Mbps, which in turn is Early, CST Code Muxing-demuxing circuits NCO Overflow Prompt, bus F ig. 1 Late code modulated by the 50bps navigation data as shown in . replica Data CST generator The C/A ranging code has a period of 1ms and is selected epoch CA Count extractor math 1023 from a special class of pseudorandom noise (PRN) sequences CST updates DLL Code NCO step n-1 update Code NCO step n known as Gold codes. Each satellite can be identified by buffer its unique Gold code. The navigation data is a sequence of Carrier NCO step n-1 FLL-PLL Carrier NCO step n update buffer bits that carries satellite orbital information, satellite time and Frame GPS error correction parameters [8]. The L1 C/A signal, transmitted lock time CST with an average power of PL1, from a GPS satellite can be represented mathematically as Fig. 2. System block diagram p sL1(t) = 2PL1D(t)x(t) cos (2πfL1t + θT x) (1) III. SYSTEM OVERVIEW where D is the navigation data; x is the C/A code and fL1 Our dataflow-driven system expects 1-bit samples from an the L1 carrier frequency. RF front end which it uses to acquire, track, and extract crucial The signal from a particular satellite reaches the receiver’s data. It then sends the extracted data to a co-processor or RF front end after some transmission delay. This difference base station for navigation solution computation. In order to in time of flight of the signals from different satellites to solve the four unknowns corresponding to the receiver time, the receiver forms the fundamentals of radio-navigation on X, Y and Z coordinates, a GPS receiver needs to track at least which the GPS system is based. Additional uncertainties in four satellites. To allow for redundancy and the flexibility to the received signal are introduced by the receiver’s front end compute an over-determined least-squares solution, our system oscillator error, and the Doppler frequency shift due to the is capable of tracking up to six satellites simultaneously. This relative movement of the satellite and the receiver. The receiver is accomplished with six GPS channels, where each channel must compensate for these uncertainties so that a correct is responsible for processing the signal from one particular navigation solution can be computed. satellite. We optimize the system to have all channels share a The GPS baseband processor’s role is to first acquire a rough single tracking loop. estimate of the transmission delay and Doppler frequency A comprehensive description of GPS baseband processor ar- shift for each available satellite and then refine the estimates chitectures can be found in [9], [10], [11]. In what follows, we through tracking loops. A delay-locked loop (DLL) tracks summarize the choices we have made in our implementation deviations in the estimate of the transmission delay whereas of a GPS baseband processor. a frequency-locked loop (FLL) or a phase-locked loop (PLL) tracks deviations in the Doppler frequency estimate. A. Acquisition It is important to realize that the signal in (1), after Before a receiver can begin to track a satellite, it needs to conditioning by the front end, consists of several signals with know which satellite to track, and an estimate of the Doppler different intrinsic frequencies, the fastest of which is the RF frequency and code offset of the signal for that particular front end ADC sampling rate, followed by the chipping rate of satellite. Therefore, during signal acquisition, a typical receiver 1.023MHz with a 1ms PRN code period in x, and finally the searches the expected Doppler frequency space and code offset 50Hz navigation data rate in D. In subsequent sections, we space of candidate satellites. will describe how our system exploits these properties when First, for each candidate satellite, the input signal from the processing the signal to produce navigation solution, with the RF front end undergoes a carrier-wipeoff with a candidate ˆ objective of minimizing power consumption while optimizing Doppler frequency fD and a code-wipeoff using a locally- performance.