The Influence of Clock-Gating On NBTI-Induced Delay Degradation

J. Pachito, C. V. Martins, J. Semião M. Santos, I. C. Teixeira, J. P. Teixeira Univ. of Algarve / INESC-ID Lisbon INESC-ID Lisbon / IST-UTL Faro, Portugal Lisbon, Portugal {a38318, cvmartins, jsemiao}@ualg.pt {marcelino.santos, isabel.teixeira, paulo.teixeira}@ist.utl.pt

Abstract²This paper presents an analysis of the implications of gating (and eventually data gating) can save large amounts of clock gating techniques on the increase of aging degradations in power, both in normal and in test mode, even requiring new node digital circuits. NBTI is the dominant effect that cause additional interface circuitry [5], and it is based on the long-term performance degradations over time, and circuit reduction of the switching activity of unused resources, to operating conditions may increase significantly these reduce the dynamic power by gating off the clock signal of degradations, namely with high power-supply voltage values, those resources. sigQDOV¶SUREDELOLW\RIRSHUDWLRQDQGORZRSHUDWLQJIUHTXHQFLHV$ proprietary tool is used, AgingCalc, to predict performance However, the reduction of the switching activity in a degradations caused by NBTI effects over time. SPICE circuit, regardless of the power saving it can introduce, may simulations show that by reducing signal transitions in pipeline inflict important long-term degradation issues, related with the circuits implemented with clock gating techniques, the NBTI effect. Aging effects caused by phenomena like Hot performance degradation in the critical paths could lead to delay Carrier Injection (HCI), Time Dependent Dielectric Breakdown errors captured by the pipeline stages. The solution is to replace (TDDB), or Negative Bias Temperature Instability (NBTI) (the specific flip-flops (FF) ZLWKSHUIRUPDQFHVHQVRUV¶FF, that allow dominant long-term effect in nanometer CMOS technologies predicting the delay error occurrence in the pipeline. Simulation [6]), among others, are gaining increase relevance in new results are presented for five case studies in 65 nm CMOS technologies and degrade circuit performance over time. In technology, using Berkeley Predictive Technology Models (PTM). particular, the NBTI effect occurs in the PMOS transistors and tends to increase the threshold voltage values of PMOS Keywords- clock gating, NBTI, performance sensor; performance failure prediction. transistors, depending on the workload of each PMOS transistor, the frequency of the switching activity, temperature I. INTRODUCTION and power-supply voltage. The reduction of the switching activity may dictate that the transistor stays for long periods in 3RZHU LV RQH RI WKH PDMRU FRQFHUQV LQ WRGD\¶V QHZ QRGH a high NBTI degradation condition, affecting the performance CMOS integrated circuits (IC). As technology scales down, of the circuit. Moreover, all YDULDWLRQV WKDW DIIHFW FLUFXLW¶V power density is increasing, as the areas shrink and the timing operation, operation-dependent or not, may lead to chip frequencies increase, but power supply voltages stop scaling failures, especially if several effects are considered down significantly below 1 volt [1]. Dynamic power is still the simultaneously, or if cumulative degradations occur. Clearly, main concern, however from 65nm and below, leakage power PVTA variations GHJUDGHFLUFXLW¶VGHSHQGDELOLW\DQGUHOLDELOLW\ may become similar [3]. Consequently, leakage power as we move to the lower nanometer range. reduction is also critical. In the context of nanometer CMOS, system performance optimization is also challenging, as In this paper we present an analysis about the influence of enhanced susceptibility to Process, Voltage, Temperature and clock-gating techniques on the NBTI-induced delay Aging (PVTA) variations need to be accounted for in the degradation. It is shown that the reduction of the switching design process. activity changes the workload probabilities of the transistors and imposes the need to account for NBTI long-term aging Low-Power (LP) design techniques at lower levels of effects early in the initial design stages. The use of abstraction have to carefully manage power supply voltages performance sensors in a Performance Failure Prediction (PFP) and clock frequencies in synchronous circuits. Aggressive methodology can guarantee a fault-free operation, especially if techniques may be used (like Dynamic Voltage and Frequency sensor design and insertion is performed using an aging Scaling [2]), but one LP technique widely adopted by the prediction analysis, to determine the infant and the aged delays industry is the clock gating technique. Due to its low impact on of the CPs (which may differ). circuit design, implementation and timing, it is used to restrict dynamic power consumption in current generation high-end, The remainder of the paper is organized as follows. In general purpose processors (like the POWER5 chip [4]). In Section 2 the clock-gating technique is summarized. In Section fact, it is probably fair to say that clock-gating has been 3, presents how NBTI can introduce delay degradations over introduced as the primary means of dynamic power time. The aging prediction methodology is described in Section management in recent server-class microprocessors [1]. Clock 4. Section 5, resumes the Performance Failure Prediction

978-1-4673-2085-6/12/$31.00 c 2012 IEEE 61 solution to overcome the increased delay degradations Regardless of the type of clock-gating technique used, obtained. Section 6 describes experimental results with power savings are related not only with power reductions in the AgingCalc tool analysis and HSPICE simulations. Finally, clock distribution network and clock circuitry, but also by Section 7 summarizes the main conclusions and provides UHGXFLQJXQQHFHVVDU\GDWDVLJQDOV¶WUDQVLWLRQV guidelines for future work. III. NBTI-INDUCED DELAY DEGRADATION II. CLOCK GATING NBTI has been identified as the dominant long-term effect Clock-gating is the most common Register Transfer Level in nanometer CMOS technologies [6]. It primarily affects (RTL) optimization (and probably the oldest technique) for PMOS transistors, increasing |VthP| over time. This will reducing dynamic power. The basic concept is: if certain parts ultimately cause a delay fault. Industrial practice shows that of a design doQ¶W QHHG D FORFN UXQQLQJ GXULQJ D JLYHQ WLPH NBTI has significant impact on circuits for 90nm technology period, then the clock is shut down in those parts, during this and below, and the impact increases with further scaling [9]. time interval. There is a large range of clock-gating techniques available to designers, and clearly not all are equally effective NBTI occurs when PMOS transistors are negatively biased (V < 0). Its effect is magnified at high temperatures. In a in reducing the FLUFXLW¶VVZLWFKLQJDFWLYLW\0RVWFORFN-gating GS is defined at RTL, and the typical algorithms can be grouped digital circuit a PMOS transistor is ON when the gate terminal into three categories: system-level, sequential and LVDWORZOHYHO µ¶ ZKLFKOHDGVWR9GS = VDD. In this stress combinational. System-level clock-gating halts the clock for an phase of the transistor, the electric field in the thin oxide has a entire block, effectively disabling all its functionality, while maximum value. Moreover, if a higher thermal energy (high combinational and sequential clock-gating selectively holds temperature) exists, these conditions work in favor to break the clocking while the block continues to make available its Si and H chemical bonds in the Si-SiO2 interface, creating outputs. interface traps in the channel. Traditionally, this Si-SiO2 interface is annealed in hydrogen ambient during manufacture, Combinational clock-gating is a straightforward and some Si-H bonds are generated. However, PMOS substitution to the RTL code and is a feature in some RTL transistors stress condition favors some of these bonds to break, compilers. It reduces power, by disabling the clock signal on increasing the instability and creating traps in the channel registers when their output is not changing. So, by looking for (which increases the PMOS threshold voltage and decreases its conditional assignments in the code, power-aware synthesis drain current flow). tools identify RTL coding patterns and make the appropriate substitutions. However, as the switching activity is eliminated ,I3026WUDQVLVWRU¶VJDWHOHYHOLVKLJK 9GS = 0V, or VG = only when data is not changing, the actual power savings is VDD), some of these Si-H bonds are reestablished; this phase is limited, and dynamic power can be reduced by about 5-to-10%. also known as recovery. However, not all the chemical bonds are reestablished, which leads to a cumulative degradation of Sequential clock-gating modifies the RTL micro- PMOS transistors. Hence, if the PMOS operates as a switch, architecture without affecting the design functionally. Power is the delay time between the ON and OFF state will increase, optimized by identifying unused computations, data dependent OHDGLQJ WR VORZHU FLUFXLWV 2YHU WLPH WKLV VKRUWHQV FLUFXLW¶V functions and don't-care cycles in the original code. Many lifetime. types of sequential clock-gating transformations are available, and one example of a sequential optimization is turning off The NBTI effect can thus be modeled by an increase of the subsequent pipeline stages, based on a propagated valid magnitude of PMOS transistors threshold voltage, |VthP|. NBTI condition (this transformation is only cost-effective if the data modeling has been widely studied, based on the reaction- path is multiple bits wide, due to the additional logic). It diffusion model [10]. A complete NBTI model has been requires a greater demand on functional verification resources presented in [9], comprehending static and dynamic model (for and can save significant dynamic power, typically reducing short and for long periods of analysis). The model calculates a switching activity by 15-to-25% on a given block. 'VthP value for the PMOS transistor (variations in the VthPMOS magnitude), considering the power-supply voltage, System-level clock-gating shuts off entire RTL blocks. temperature, the probabilities of the transistor to be ON and Because large sections of logic are not switching for many OFF, and some technology dependent parameters. In this work, clock cycles, it has the most potential to save power. It is this dynamic long-term modeling of the NBTI effect [9] is used designed into the original hardware architecture and coded as to predict circuit behavior with aging. part of the RTL functionality. Because large sections of logic are not switching for many clock cycles, it has the most The aging process affects differently each PMOS in a potential to save power. However, these modifications are circuit, according to its temperature, power-supply voltage and, invasive to the design function. The enable logic is part of an especially, the time that each transistor is being stressed. overall power management strategy, and sometime includes Considering different frequencies of operation, the NBTI effect consideration for software control. is relatively insensitive to switching frequency, when it is above 100Hz [9][11] +RZHYHU LQ WRGD\¶V GLJLWDO FLUFXLWV More recently, other types of clock-gating techniques made significant parts remain idle for long periods of time, especially their way through the standard techniques, like deterministic if clock-gating techniques are used, which create a long stress clock-gating [7], or transparent clock-gating [8]. The former is period for some PMOS transistors. A high degradation may XVHG LQ PLFURSURFHVVRUV¶ SRZHU VDYLQJV DQG Whe latter occur for some transistors, even for circuits operating at a introduces a new way of applying clock-gating to pipelines. nominal high clock frequency. Such high degradation can even

62 2012 IEEE 18th International On-Line Testing Symposium (IOLTS) occur in a non-CP that becomes critical over time, and thus, of flip-flops (FF) that capture the selected critical paths, the aging can re-order the timing PDSRIFLUFXLW¶VSDWKVMoreover, critical FF (as will be seen in section 5). Moreover, HSPICE traditional STA (static Timing Analysis) and SSTA (Statistical simulations are performed on small parts of the circuit, to STA) tools do not take these aging effects into consideration analyze degradation with VthP modulation, guaranteeing the and effective critical paths are not only those that have small scalability of the methodology to bigger circuits. time slacks by design, but also those that become critical with aging-induced delay defects. V. PERFORMANCE FAILURE PREDICTION In this work we propose to use a PFP methodology in IV. AGING PREDICTION circuits with clock-gating techniques, as the reduction of the As mentioned, the use of clock gating techniques in new switching activity can have an important impact on critical node technology circuits may introduce unexpected long-term paths degradation over time, to predict circuit failure and allow delay-faults. Hence, considering that non-critical paths, even in the end user to act before the error occurs. worst-case PVTA conditions, have sufficient time slack margin to avoid having a delay fault, and that critical paths are always Various SHUIRUPDQFH VHQVRUV¶ topologies have been more susceptible to the occurrence of a delay fault (even in SUHVHQWHG WR JOREDOO\ GHWHFW FLUFXLW¶V aging degradation [14]. best-case PVTA conditions), it is of major importance the However, if global sensors age differently than the circuit, two existence of aging prediction tools to allow the prediction of things could happen: (1) low slack margins are used, and the the aging-induced delays over time. An aging prediction FLUFXLW PD\ IDLO EHFDXVH WKH FLUFXLW¶V FULWLFDO SDWK &3  KDV analysis should identify which of the near-critical paths may higher delay degradation than the sensor; or (2) large slack become critical in worst-case PVTA conditions. margins are used, and the circuit is not optimized, because global sensors do not have information from each local CP In this work, a methodology for aging prediction is also degradation. presented. Hence, dXH WR 397$ YDULDELOLW\ D XVHU¶V GHILQHG A different aging sensor approach is the circuit failure VDIHW\PDUJLQ Įsafe) is used to distinguish the safe paths (those with sufficient time slack to account for worst-case PVTA prediction technique proposed by M. Agarwal et al. in [15]. variations) from the unsafe paths (the critical paths and the The underlying idea is to anticipate system failure, before it near-critical that require an aging prediction analysis). We really occurs, using an early caption at critical selected memory cells. Their major application was to reduce the pessimistic consider in this work Į = 80%, to define as safe the paths safe worst-case delay to accommodate PVT variations, which whose timing is smaller than × , where is the CP delay Įsafe W0 W0 significantly limits system performance. This concept was (Wsafe < Įsafe×W0). Performing a SSTA on the CUT with a improved in [16] and used to monitor performance errors it allows the VWDQGDUG FRPPHUFLDO WRRO HJ 3ULPH7LPHŒ  GXULQJ SURGXFW¶V OLIHWLPH +RZHYHU WKHVH ORFDO VHQVRUV DUH identification of the safe paths and the unsafe paths. activated periodically, being disconnected most of the time to A proprietary tool (AgingCalc) was developed to perform UHGXFH VHQVRU DJLQJWKXV NHHSLQJ LWV LQLWLDOSHUIRUPDQFH LW¶V the CUT aging prediction analysis, computing the delay not an on-line monitoring methodology). degradation of the selected unsafe paths. AgingCalc computes More recently, the local sensor was again improved to the probabilities of the workload for each PMOS transistor in observe aging in a real on-field situation and perform a the CUT, and estimates the new VthP values for each PMOS constant monitoring of heterogeneous VTA variations [17][12]. transistor, given an aging time frame t7KH³DJHG´9thP values The main advantages were: (1) the sensor adapts itself to VTA are computed using the long term prediction model of 'VthP for variations, enhancing its error prediction capability as dynamic NBTI, described in [9][11]. A Spice description of the variations increase; (2) sensor performs a constant monitoring, circuit is then generated and HSPICE is instantiated to simulate being always active; (3) sensor is easier to use, when compared the aged behavior and evaluate the impact on the selected to previous solutions (adds negligible performance degradation paths¶ delays. For each evaluated aging period, a new delay on the circuit, induces low area overhead and requires a simpler map is obtained for the selected unsafe paths, and an aging local control mechanism). However, using local sensors for on- prediction analysis was performed for each of the unsafe paths, line monitoring does not guarantee a periodic sensor activation, GXULQJ D XVHU¶V GHILQHG DJLQJ WLPH W\SLFDOly the expected therefore it requires a periodic off-line activation (e.g. at system FLUFXLW¶s lifetime). In this work, the expected lifetime start-up or shut-down), with an additional off-line Path Delay considered for the test circuits was 10 years (Tlife = 10 years). Fault oriented test, targeting the subset of long signal paths. The results obtained from the aging analysis should specify In these work we use these aging sensors already presented which will be WKH HIIHFWLYH FULWLFDO SDWKV GXULQJ FLUFXLW¶V in [17][12], as performance failure prediction sensors, to lifetime. To do that, a second XVHU¶V GHILQHG PDUJLQ is used, locally detect abnormal delays, and to predict circuit failure Dcritical, to define which of the unsafe paths have more caused by long-term cumulative aging degradations. In probability of inducing delay errors in the presence of PVTA particular, sensor architecture is based in a new FF cell (the variations (the critical paths). In this work we consider it to be Adaptive Error Prediction Flip-flop ± AEP-FF), used to replace Įcritical = 90%, to define the critical paths with timings above the FF that capture the critical paths described in section IV Į ×W , (W •Į ×W ). critical 0 critical critical 0 (paths with Wcritical •Įcritical×W0), identified as the critical FF. The users¶ defined margins, Įsafe and Įcritical, should be tuned Figure 1 presents the AEP-FF topology, implemented with for each application during silicon validation, but typically the a classic D FF and an aging sensor connected internally to the values of 80% and 90%, respectively, lead to a limited subset master latch. This internal connection minimizes AEP-FF

2012 IEEE 18th International On-Line Testing Symposium (IOLTS) 63 performance degradation when compared to the original D FF. The AEP-FF functionality is as follows: all the late In fact, the loading effect of the sensor circuitry is inside the transients in the signal data path that make the sensor input (Z FF; hence, it does not explicitly impact the signal path (only node) to change during clock low state (when master latch is 5% degradation in the set-up time was measured, which is transparent), will be analyzed by the sensor. These late negligible). The sensor circuitry has two main blocks: the transitions will be delayed by the DE and if the delayed data Delay element (DE) and the Stability Checker (SC). Figure 2 (SC input) changes during clock high state, it means that a late presents three typical architectures for the DE, according to transition at FF input D as occurred. The guard band interval is, their intrinsic delay. The delay is chosen by design, choosing in practice, the intrinsic delay of the DE. For more details about the appropriate topology and changing transistors size. Figure 3 sensor functionality and characteristics, please refer to presents the architecture of the SC, implemented with dynamic [17][12]. logic, which signalizes a transition at the delayed data input when the clock signal is at the high state. This SC has on- VI. SIMULATION RESULTS retention logic to keep a high signal until reset is active (at low Simulation results are presented for the aging prediction state). methodology, and for performance failure prediction sensor. Simulations were performed in HSPICE simulator and using a CMOS 65nm technology (PTM 65nm [13]), with five test circuits: CUT1 (PM4-2, Pipeline Multiplier with 4 bits and 2 balanced pipeline stages, 9 inputs (8 data and 1 clock), 8 data outputs), CUT2 (PM16-4, Pipeline Multiplier with 16 bits and 4 balanced pipeline stages, 33 inputs (32 data and 1 clock), 32 data outputs), and CUT3 to CUT5 (ITC¶EHQFKPDUNcircuits B01, B02, and B06). Moreover, 1.1V nominal VDD was considered and T variations are restricted to 110ºC (representing a worst case condition). Aging fault injection, by VthP modification, is performed by Spice VTHO parameter modulation, and NBTI aging is modulated according to PMOS Figure 1. Adaptive Error-Prediction Flip-flop topology. WUDQVLVWRUV¶ ZRUNORDG SUREDELOLWLHV FDOFXODWHG ZLWK WKH AgingCalc tool.

A. Aging Prediction Results

As mentioned in previous works [9][11], NBTI degradation effect is relatively insignificant for frequencies above 100Hz. In fact, it is expected that the nominal frequency of nanometer circuits is some orders of magnitude above that value. However, for aging prediction purposes, one should not use the (a) (b) nominal frequency value, because the aging prediction calculations here defined use an average time for the switching to occur, and use an ON/OFF state probability for each PMOS transistor (based on the signal probabilities). Moreover, we could also consider that in on-field operation, significant parts remain idle for long periods of time, which creates a long stress (c) period for some PMOS transistors, especially if clock-gating Figure 2. Delay element typical architectures: (a) Low delay; (b) Medium techniques are in use. Hence, let us consider that for aging delay; (c) High delay. prediction the frequency of operation represents an average transition time and that the frequency is always lower than the nominal frequency of the clock (representing a worst case condition). For circuits without clock gating, we will use frequencies in the kHz range and above (e.g., 500kHz) and for circuits with clock gating we will use frequencies in the Hz range and below (e.g., 100Hz). CUT1 aging prediction analysis results show an example of signal path GLVWULEXWLRQRYHUFLUFXLW¶VOLWHWLPHIRUIUHTXHQFLHV of 500kHz (in Figure 4, without significant path reordering), and for frequencies of 100Hz (in Figure 5, with path reordering, due to heterogeneous aging degradation). Results for the delay degradation of the CP and near-CPs are shown in both figures for 23 paths (the ones with the highest delays, ranked from the 1st CP to the 24th CP), but only three were Figure 3. Stability checker architecture with on-retention logic. highlighted (CP #1, #7 and #24), as these one is the critical one

64 2012 IEEE 18th International On-Line Testing Symposium (IOLTS) and the remaining two are the ones with the highest percentage TABLE I. CRITICAL PATHS¶ DEGRADATION IN 10 YEARS, FOR PTM degradation (age faster). 65NM,T=110ºC, VDD =1,1V CP degradation CP degradation Critical paths' aging analysis for PM4-2 # paths 320 for f=500kHz for f=100Hz B01 144 2,01% 9,40% 310 B02 60 2,52% 11,25% B06 246 1,82% 8,51% CP #1 300 PM_4-2 430 1,21% 6,12%

CP #11 PM_16-4 21530 2,61% 12,84%

Delay (ps) 290

CP #24 FF rise delay degradation (Clk input to Q output) 280 14 f=100Hz 270 12 Pclk=90%; 0246810 Pd=10% Years 10 f=100Hz Figure 4. &ULWLFDO3DWKV¶DJLQJDQDO\VLVIRU&873LSHOLQH0XOWLSOLHU ELWV Pclk=50%; 8 Pd=50% 2 levels of pipeline), for PTM 65nm, f = 500kHz, T = 110ºC, VDD = 1,1V. f=100Hz 6

Delay (ps) Pclk=90%; Critical paths' aging analysis for PM4-2 Pd=90% 330 4 f=500kHz 2 Pclk=50%; 320 Pd=50% 0 310 CP #1 0246810 Years 300 CP #7 Figure 6. Flip-flop rise delay degradation for Clk to Q path, for 500kHz and Delay (ps) 290 CP #24 100Hz, and for different probabilities for the clock signal and for the data input signal to be at logic 0 state (for PTM 65nm, T = 110ºC, VDD = 1,1V). 280 But path degradation also depends on the probabilities of 270 0246810 each PMOS transistor to be in the stress mode, obtained from Years the probability of each node to be at logical 0. Hence, an initial Figure 5. &ULWLFDO3DWKV¶DJLQJDQDO\VLVIRU&873LSHOLQH0XOWLSOLHU ELWV probability must be considered for each primary input (PI). If 2 levels of pipeline), for PTM 65nm, f = 100Hz, T = 110ºC, VDD = 1,1V. circuit application is known, one may be able to infer some (or all) real PI workload probability, but this is not usually the It is interesting to see in figure 4, that there is no significant case. Therefore, in this aging prediction analysis, it is important path reorder as aging degradation occurs differently on them. to analyze circuit aging with different PI data signals On the contrary, in figure 5 paths are completely reordered ¶ probabilities. Figure 7 presents the critical path s (CP #1) aging during the same circuit lifetime of 10 years. These results ¶ when considering three different PI data probabilities. As the highlight the fact that by reducing the switching activity, as it is workload probabilities will differ for each sample, according done in circuits with clock gating techniques, the aging effects with its lifetime usage, it means that during circuit s lifetime are significantly amplified during the same circuit lifetime. ¶ each sample could experience a difference path reordering with Table I summarizes the degradation obtained in the five aging. CUTs, in the CP with the highest propagation delay (not Critical path's aging analysis for PM4-2 always the paths with the highest percentage degradation). 345

Interestingly, if clock frequency was reduced, the degradations Ppi = 10% would be much higher (e.g., CUT1 degradation for f=10Hz is 335 110% in 10 years). Ppi = 50% Moreover, the NBTI-induced delay degradations in circuits 325 with clock gating also impacts on the clock signal workload. Delay (ps) Ppi = 90% By reducing the clock activity we also increase the probability 315 of the clock signal applied to the FF to be in the low state (in a non-clock-gating circuit, the clock signal workload probability 305 0246810 is equal for the high and low state, that is 50%). Hence, this Years will impact on the FF¶V FORFN SDWK 3026 WUDQVLVWRUV¶ VWUHVV condition, and ultimately on the FF propagation delay. Figure 6 Figure 7. Critical Path¶s aging analysis for different probabilities for the PIs data signals to be at logic 0 state, for CUT1, PTM 65nm, f = 100Hz, shows the comparison between different probability values for T = 110ºC, V = 1,1V, Pclk=90%. the clock and data signals to be at the low state, and for DD different frequencies, for the delay degradation of one selected B. Sensor Insertion Results path (from clock signal input to the Q output, rising). It can be seen that both clock and data input signals¶ probability change Consider the sensor insertion for CUT1. Using as a first the aging condition. Hence, the use of traditional clock gating approximation that all the paths age equally (without techniques worsens the FF path delay degradation over time.

2012 IEEE 18th International On-Line Testing Symposium (IOLTS) 65 performing aging prediction analysis), Dcritical=90% is defined Future work includes methodology automation and and 2 critical FF are identified and replaced with 2 AEP-FF. integration in a commercial design flow environment, and Note that more than one large delay path converge to the same reports from a TSMC 65nm silicon prototype already I FF. In fact, in this case, 20 long signal paths converge in 2 production. critical FF. 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This is "Predictive Modeling of the NBTI Effect for Reliable Design," in an expected result, as pipeline circuits do not have loops Proceedings of the IEEE Custom Integrated Circuits Conference between internal FFs, and PI probabilities are easier to (CICC), September 2006 propagate through circuit logic. Hence, this highlights that [10] 0$$ODP60DKDSDWUD³$&RPSUHKHQVLYH0RGHORI30261%TI 'HJUDGDWLRQ´-RXUQDORI0LFURHOHFWURQLFV5HOLDELOLW\9RO,VVXH aging degradation must be analyzed, considering different PI pp. 71-81, DOI: 10.1016/j.microrel.2004.03.019, January, 2005. workload probabilities, especially if clock-gating is used. [11] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, Y. Cao, "The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, VII. CONCLUSIONS and Analysis", Tran. Very Large Scale Integration (VLSI'10), IEEE, In this paper, an analysis on the influence of clock-gating Vol. 18 Issue: 2, pp. 173-183, DOI: 10.1109/TVLSI.2008.2008810, Feb., 2010. on NBTI-induced delays was presented. It was shown that by [12] C. Martins, J. Pachito, J. Semião, I. C. Teixeira, J. P. Teixeira, "Adaptive reducing the clock switching (and consequently data switching) Error-Prediction Aging Sensor for On-Line Monitoring of Performance activity can increase the aging degradation effects (due to Errors", Proc. of the 26th. Conference on Design of Circuits and NBTI effect). A proprietary aging prediction tool, AgingCalc, Integrated Systems (DCIS'11), Nov., 2011. was used to perform calculations on circuit probabilities [13] Predictive Technology Model (PTM), http://www.eas.asu.edu/~ptm/. ZRUNORDGDVZHOODVFLUFXLW¶V3026WUDQVLVWRUV¶SUREDELOLW\WR [14] D. Kim, J. Kim, M. Kim, J. Moulic, H. Song, "System and Method for be in the stress mode condition, and also the NBTI-induced Monitoring Reliability of a Digital System", IBM Corp., US Patent 7495519, Feb. 24, 2009. VthP variations over time for each PMOS transistor. Moreover, the aging prediction is obtained by HSPICE simulation on the [15] M. Agarwal, et al., "Circuit Failure Prediction and Its Application to aged circuit, and delay degradations are measured. The solution Transistor Aging". Proc. VLSI Test Symp. (VTS), pp. 277-286, 2007. for the increased delay degradations obtained if clock gating is [16] J.C. Vazquez, et al., "Predictive Error Detection by On-line Aging Monitoring", Proc. IEEE Int. On-Line Test Symp. (IOLTS), 2010. to use a PFP methodology, with the insertion of aging sensors [17] C. Martins, J. Semião, J. C. Vazquez, V. Champaq, M. Santos, I. C. in judiciously selected critical FF. Simulation results Teixeira, J. P. Teixeira, "Adaptive Error Prediction Flip-Flop for demonstrate aging prediction methodology and sensor insertion Performance Failure Prediction with Aging Sensors", Proc. of IEEE criteria. VLSI Test Symposium (VTS), April 2011.

66 2012 IEEE 18th International On-Line Testing Symposium (IOLTS)