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10 nm process

Reliability Evaluation of Finfet-Based Srams in the Presence of Resistive Defects
Introducing 10-Nm Finfet Technology in Microwind Etienne Sicard
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Yield and Reliability Challenges at 7Nm and Below Andrzej J
Introduction to Semiconductor Processing Brendan O'neill
Copyrighted Material
Promising Lithography Techniques for Next-Generation Logic Devices
ASAP7 a 7-Nm Finfet Predictive Process Design

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UC Riverside UC Riverside Electronic Theses and Dissertations
Circuit-Level Approaches to Mitigate the Process Variability and Soft Errors in Finfet Logic Cells Alexandra Lackmann Zimpeck
Circuit-Level Approaches to Mitigate the Process Variability and Soft Errors in Finfet Logic Cells
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