Mark Bohr on Intel's Technology Leadership

technology Leadership MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017

TECHNOLOGY AND MANUFACTURING DAY Legal Disclaimer

DISCLOSURES

China Tech and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year’s program.

Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management’s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings release dated July 27, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC’s website at www.sec.gov.

TECHNOLOGY AND MANUFACTURING DAY 10 nm Hyper Scaling 22FFL technology Future Research

TECHNOLOGY AND MANUFACTURING DAY 14 nm hyper Scaling features

Fin Pitch Interconnect Pitch Cell Height Gate Pitch 60 nm 42 nm 80 nm 52 nm 840 nm 399 nm 90 nm 70 nm .70x .65x .48x .78x

22 nm 14 nm 22 nm 14 nm 22 nm 14 nm 22 nm 14 nm

14 nm uses aggressive feature scaling to deliver unprecedented 0.37x logic cell area scaling

TECHNOLOGY AND MANUFACTURING DAY 14 nm products

Wide range of 14 nm products in volume production on various derivative technologies

TECHNOLOGY AND MANUFACTURING DAY 10 nm Hyper Scaling

Fin Pitch Min Metal Pitch Cell Height Gate Pitch 42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm .81x .69x .68x .78x

14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm

Double Quad Pattern Pattern 10 nm features aggressive pitch scaling - world’s first self-aligned quad patterning

TECHNOLOGY AND MANUFACTURING DAY 10 nm Hyper Scaling

Fin Pitch Min Metal Pitch Cell Height Gate Pitch Dummy Gate Gate Contact 42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm Double Single Std COAG .81x .69x .68x .78x

Contact

14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm

Double Quad Pattern Pattern Aggressive scaling & new features deliver 2.7x transistor density improvement

TECHNOLOGY AND MANUFACTURING DAY 3rd generation finfets

14 nm 10 nm 22 nm

53 nm

34 nm

10 nm fins are ~25% taller and ~25% more closely spaced than 14 nm

TECHNOLOGY AND MANUFACTURING DAY Contact Over Active gate

Transistor Transistor

Fins

Contact Gate Gate

Contact over active gate is a revolutionary feature for another ~10% area scaling

TECHNOLOGY AND MANUFACTURING DAY Single dummy Gate

14 nm 10 nm Active Dummy Active Single Gate Gates Gate Dummy Gate

Process innovations enable denser single dummy gate at cell borders

TECHNOLOGY AND MANUFACTURING DAY Cell Library Height Scaling

14 nm 399nm Height

10 nm 272nm Height (0.68x)

Cell Height Cell Height

Gate Pitch Gate Pitch Fin pitch and metal pitch scaling allow cell height to scale 0.68x from 14 nm

TECHNOLOGY AND MANUFACTURING DAY Logic Transistor density

1 45nm .49x Logic Area Metric

32nm .45x Gate Pitch

22nm Logic .37x Logic Area 0.1 Cell (relative) Height 14nm .37x

Logic Cell 10nm Width

0.01 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Hyper scaling delivers better-than-normal logic area scaling

TECHNOLOGY AND MANUFACTURING DAY Logic Transistor density

10nm 100

14nm 2.7x Intel

2.5x Transistor 22nm Density 60/40 NAND+SFF Density Metric MTr / mm2 10 32nm 2.1x

45nm 2.3x

1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Hyper scaling delivers better-than-normal transistor density improvement

TECHNOLOGY AND MANUFACTURING DAY Logic Transistor density

10nm 100 100.8 14nm Intel

37.5 Transistor 22nm Density 60/40 NAND+SFF 15.3 MTr / mm2 Density Metric MTr / mm2 10 32nm

7.5 45nm

3.3

1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date 10 nm hyper scaling features result in transistor density above 100 MTr/mm2

TECHNOLOGY AND MANUFACTURING DAY Logic Transistor density comparison

100.8 100

48.1 51.6 Transistor 60/40 NAND+SFF Density Density Metric

(MTr/mm2)

Intel nm Intel 14

Intel nm Intel 10

Samsung nm 10Samsung

TSMC nm TSMC 10

Samsung nm 14 Samsung

Intel 22FFLIntel

TSMC nm TSMC 16 Samsung nm 20Samsung 10 nm TSMC 20 20/22 nm 14/16 nm 10 nm

Intel 10 nm is a full generation denser than other “10 nm”

TECHNOLOGY AND MANUFACTURING DAY 10 nm technology density Comparison

Intel TSMC Samsung 10 nm 10 nm 10 nm

Fin Pitch 34 36 42 nm

Gate Pitch 54 66 68 nm

Minimum Metal Pitch 36 42 48 nm

Logic Cell Height 272 360 420 nm

Logic Trans. Density 100.8 48.1 51.6 MTr/mm2

Logic Trans. Density 1x 0.48x 0.51x Relative

Intel 10 nm is ahead of other “10 nm” technologies on every density metric

TECHNOLOGY AND MANUFACTURING DAY SRAM AREA SCALING

SRAM 0.1 Cell Area (um2) HP .0441 LV .0367 HD .0312 um2

0.01 45nm 32nm 22nm 14nm 10nm 7nm

10 nm offers a range of SRAM cells for density and power/performance SRAM cell area scaled ~0.6x from 14 nm TECHNOLOGY AND MANUFACTURING DAY Transistor performance and power Performance Power Performance per Watt

32nm

22nm

14nm

Higher Better Performance 10nm Perf/Watt 10nm Lower Power 10nm 14nm

14nm scale) (log Watt per Performance Dynamic Capacitance (log scale) (log Capacitance Dynamic Transistor Performance (log scale) (log Performance Transistor 22nm 22nm 32nm 32nm 2009 2011 2013 2015 2017 2019 2021 2009 2011 2013 2015 2017 2019 2021 2009 2011 2013 2015 2017 2019 2021 Process Readiness Date Process Readiness Date Process Readiness Date 10 nm transistors provide improved performance per watt

TECHNOLOGY AND MANUFACTURING DAY Transistor performance and power Performance Power Performance per Watt

32nm

22nm 14+ 14++

10++ 14nm 10++ 10+ 10++ 10+

Higher Better 14++ 10+ Performance 10nm Perf/Watt 10nm Lower 14++ 14+ 14+ Power 10nm 14nm

TECHNOLOGY AND MANUFACTURING DAY 10nm performance and power Comparison

10 10++

Active Samsung ~30% Intel Power TSMC ~20% Lower Power

Higher Performance

Performance

Intel 10 nm has a considerable performance lead over other “10 nm”

TECHNOLOGY AND MANUFACTURING DAY Derivative technologies

CPU SoC

High Perf Transistors Yes Yes

Low Leakage Transistors - Yes

Analog/RF Transistors - Yes

HV I/O Transistors - Yes

High-Q Inductors - Yes

Precision Resistors Yes Yes

MIMCAP Yes Yes

Device Options Low Cost Dense High Perf Interconnect Stack Options

Multiple derivative options offered for each technology generation

TECHNOLOGY AND MANUFACTURING DAY 10 nm Summary

• Intel’s 10 nm process technology has the world’s tightest transistor & metal pitches along with hyper scaling features for leadership density • Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies • Intel’s 10 nm process technology is on track to commence manufacturing in 2H’17 • Hyper scaling extracts the full value of multi-patterning schemes and allows Intel to continue the economic benefits of Moore’s Law

TECHNOLOGY AND MANUFACTURING DAY 10 nm Hyper Scaling 22FFL technology Future Research

TECHNOLOGY AND MANUFACTURING DAY Intel’s new 22FFL technology

22FFL is the world’s first FinFET technology for low power IOT and mobile products

. Advanced FinFET transistors based on proven 22 nm and 14 nm features

. >100x leakage power reduction with new ultra-low leakage transistor option

. Simplified interconnects and design rules based on 22 nm technology

. New levels of design automation

. Fully RF design enabled

. Cost competitive with other industry 28/22 nm planar technologies

TECHNOLOGY AND MANUFACTURING DAY 22FFL dimensions

22 nm 22FFL 14 nm

Transistor FinFET FinFET FinFET

Fin Pitch 60 45 42 nm

Gate Pitch 90 108 70 nm

Metal Pitch 80 90 52 nm

Logic Cell Ht 840 540 399 nm

Trans. Density 15.3 19.4 37.5 MTr / mm2

SRAM Cell .092 .088 .050 um2

22FFL is based on proven 22 nm and 14 nm features

TECHNOLOGY AND MANUFACTURING DAY 22FFL devices

 High performance transistors  Low 1/F noise

 Ultra low leakage transistors  Deep N-well isolation

 Analog transistors  Precision resistor

 High voltage I/O transistors  MIM capacitor

 High voltage power transistors  High resistance substrate

 Good device matching  High-Q inductors

22FFL offers a wide range of devices for digital and analog/RF design

TECHNOLOGY AND MANUFACTURING DAY FinFETPerformance and leakage Advantage

2.0 10 1.8 1 1.6 37% 0.1 Faster 32 nm Planar 1.4 Planar Transistor Channel Gate Delay 0.01 Tri-Gate 1.2 Current (normalized) (normalized) 0.001 1.0 22 nm 18% Faster Tri-Gate 0.0001 0.8 Reduced Leakage 0.6 1E-05 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.0 0.2 0.4 0.6 0.8 1.0 Operating Voltage (V) Gate Voltage (V)

FinFETs provide a significant performance and leakage advantage over any planar transistor

TECHNOLOGY AND MANUFACTURING DAY Intel 22 nm Tri-Gate announcement, April 2011 22FFl high performance transistors 100 0.85V

10 >40% Higher Drive 22GP at Same Leakage

1 22FFL

>18x Total 0.1 Lower Leakage Leakage (nA/um)

0.01 Lower Leakage

0.001 Higher Performance

0.0001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Drive Current (mA/um) 22FFL provides high performance transistors with drive currents similar to 14nm++

TECHNOLOGY AND MANUFACTURING DAY 22FFL Low leakage transistors 100 0.85V

10 22GP

1 22FFL

>18x Total 0.1 Lower Leakage Leakage (nA/um) 22FFL Low Leakage 0.01 >500x Lower Lower Leakage Leakage 0.001 Higher Performance

0.0001 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Drive Current (mA/um) 22FFL provides the lowest leakage transistors for any mainstream technology

TECHNOLOGY AND MANUFACTURING DAY Intel Custom Foundry’s robust Ecosystem

Design Service

Design Tools Intel Soft IP & Flows Custom Foundry

Foundation IP Advanced IP

22FFL is fully supported by a robust design ecosystem

TECHNOLOGY AND MANUFACTURING DAY Other names and brands may be claimed as the property of others 22FFL technology

 High transistor drive currents similar to Intel 14 nm  Low leakage transistors with >500x lower total leakage than 22GP  Die area scaling better than industry 28/22 nm technologies  Wide range of advanced analog/RF devices  Extensive use of single patterning for affordable ease-of-design  Mature die yield with use of proven 22/14 nm features  Cost competitive with other 28/22 nm planar technologies  Industry standard PDK1.0 available now  Production readiness in Q4 2017

22FFL is an exciting new technology that provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products

TECHNOLOGY AND MANUFACTURING DAY 10 nm Hyper Scaling 22FFL technology Future Research

TECHNOLOGY AND MANUFACTURING DAY Innovation enabled technology pipeline

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm Manufacturing Development Research

Contact Gate Gate

High-k Metal Gate FinFETs Contact over Gate

SA Double Patterning SA Quad Patterning

Intel has been the industry leader in bringing innovative technologies from research to high volume manufacturing TECHNOLOGY AND MANUFACTURING DAY Innovation enabled technology pipeline

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm Manufacturing Development Research

III-V

Contact

III-V Transistors 3D Stacking Material Synthesis Gate Gate

High-k Metal Gate FinFETs Contact over Gate

2D Materials Nanowires EUV Patterning

10nm

SA Double Patterning SA Quad Patterning Interconnects Beyond CMOS Dense Memory

Future options subject to change We have a wide range of options in research to continue Moore’s Law

TECHNOLOGY AND MANUFACTURING DAY Research projects

Nanowire Transistors III-V Transistors 3D Stacking Dense Memory

10nm

Dense Interconnects EUV Patterning Neuromorphic Computing Spintronics

TECHNOLOGY AND MANUFACTURING DAY Intel Oregon Campus

Intel’s main research & development site

TECHNOLOGY AND MANUFACTURING DAY Intel Oregon Campus

Research Development

Manufacturing

Modeling Sort/Test

Advanced Design

Automation Reliability

Technology leadership is the result of close collaboration at one site

TECHNOLOGY AND MANUFACTURING DAY Summary

• Hyper scaling on Intel 14 nm and 10 nm technologies provides better than normal scaling and delivers improved cost per transistor and performance per watt

• Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies

• 22FFL provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products

• Multiple technology options now in research will enable the continuation of Moore’s Law for at least the next 10 years

TECHNOLOGY AND MANUFACTURING DAY