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Circuit-Level Approaches to Mitigate the Process Variability and Soft Errors in Finfet Logic Cells Alexandra Lackmann Zimpeck

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Circuit-Level Approaches to Mitigate the Process Variability and Soft Errors in Finfet Logic Cells Alexandra Lackmann Zimpeck Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells Alexandra Lackmann Zimpeck To cite this version: Alexandra Lackmann Zimpeck. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells. Micro and nanotechnologies/Microelectronics. Institut Supérieur de l’Aéronautique et de l’Espace (ISAE); Universidade Federal do Rio Grande do Sul (Brésil), 2019. English. tel-02890418 HAL Id: tel-02890418 https://hal.archives-ouvertes.fr/tel-02890418 Submitted on 6 Jul 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. 5)µ4& &OWVFEFMPCUFOUJPOEV %0$503"5%&-6/*7&34*5²%&506-064& %ÏMJWSÏQBS Institut Supérieur de l’Aéronautique et de l’Espace Universidade Federal do Rio Grande do Sul (Brésil) 1SÏTFOUÏFFUTPVUFOVFQBS Alexandra LACKMANN ZIMPECK le mardi 24 septembre 2019 5JUSF Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET ²DPMF EPDUPSBMF et discipline ou spécialité ED GEET : Micro et nanosystèmes 6OJUÏEFSFDIFSDIF Équipe d'accueil ISAE-ONERA OLIMPES %JSFDUFVS T EFʾÒTF M. Ricardo REIS (directeur de thèse) M. Laurent ARTOLA (co-directeur de thèse) Jury : Mme Lirida NAVINER, Professeur Télécom Paris - Rapporteur, Présidente M. Ricardo REIS, Professeur UFRGS Brésil - Directeur de thèse M. Laurent ARTOLA, Ingénieur de Recherche ONERA - Co-directeur de thèse M. Remi BARBIER, Professeur ISAE-SUPAERO Mme Karine COULIÉ, Maître de Conférences Université Aix-Marseille - Rapporteure M. Marc GALLARDIN, Ingénieur CEA M. Paul LEROUX, Professeur KU Leuven Belgique Mme Cecilia MEZZOMO, Ingénieur Thales Alenia Space Acknowledgments I would like to start by thanking my parents, Alexandre and Dulcinara, for the study encouragements since the earliest stages of my life, for all support provided me to achieve my goals, and for never letting me give up on my dreams. I thank my brother, Lucas, for unconditional love even though sometimes he didn’t understand the reasons for the distance between us. Thank you for always been close to me, even when I have been a few thousand kilometers away from you. I also thank my husband, André Furlan, for your patience, support to achieve my goals and mainly, for accompanying me during my internship in Toulouse. I take the opportunity also to thank all my family and friends who always sent positive vibes for me and understood the several important moments when I could not be present. I would like to thank my colleagues from UFRGS, Gracieli Posser, Calebe Micael, Tania Ferla, Jucemar Monteiro, Felipe Rosa, Walter Calienes, Vitor Bandeira, Geancarlo Abich, Mateus Fogaça, Lucas de Paris, Louise Etcheverry, Vladimir Afonso, Leonardo Brendler, Leonardo Moraes, Pablo Silva, for the friendship, confidence and the countless hours discussing a variety of subjects. My thanks to all my colleagues from ONERA, especially to Raphael Vieira and Neil Rostand for sharing studies, knowledge, and ideas, and Virnigie Inguimbert for helping me understand better the French language. I would thank especially Prof. Cristina Meinhardt for all support in my scientific research since 2010, for the professional partnership on most varied subjects and her friendship during all these years. I want to thank my advisor, Prof. Ricardo Reis, for always believing in my potential and for encouraging me to be better every day. I thank so much Prof. Fernanda Kastensmidt for her collaborations, discussions, and all support given for this work. I also thank Laurent Artola and Guillaume Hubert for the research opportunity and for all knowledge obtained inside of ONERA as well as for providing me a fantastic internship in France. Finally, I would like to thank all the supernatural forces that make us go forward until the end. To all of you, my sincere thanks. 2 Abstract Process variability mitigation and radiation hardness are relevant reliability requirements as chip manufacturing advances more in-depth into the nanometer regime. The parameter yield loss and critical failures on system behavior are the major consequences of these issues. Some related works explore the influence of process variability and single event transients (SET) on the circuits based on FinFET technologies, but there is a lack of approaches to mitigate the effects caused by them. For these reasons, from a design standpoint, considerable efforts should be made to understand and reduce the impacts introduced by reliability challenges. In this regard, the main contributions of this Ph.D. thesis are: 1) to investigate the behavior of FinFET logic cells under process variations and radiation effects; 2) to evaluate four circuit-level approaches to attenuate the impact caused by work-function fluctuations (WFF) and soft errors (SE); 3) to provide an overall comparison between all techniques applied in this work; 4) to trace a trade-off between the gains and penalties of each approach regarding performance, power, area, and SET cross-section. Transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor are the four circuit-level mitigation techniques explored in this work. The potential of each one to make the logic cells more robust to the process variability and radiation-induced soft errors are assessed comparing the standard version results with the design using each approach. This Ph.D. thesis also establishes the mitigation tendency when different levels of variation, transistor sizing, and radiation particles characteristics such as linear energy transfer (LET) are applied in the design with these techniques. The process variability is evaluated through Monte Carlo (MC) simulations with the WFF modeled as a Gaussian function using SPICE simulations. The SE susceptibility is estimated using the radiation event generator tool MUSCA SEP3 (developed at ONERA), also based on an MC method, which deals both with radiation environment characteristics, layout features and the electrical properties of devices. In general, the proposed approaches improve the state-of-the-art by providing circuit-level options to reduce the process variability effects and SE susceptibility, at fewer penalties and design complexity. The transistor reordering technique can increase the 3 robustness of logic cells under process variations up to 8%, but this method is not favorable for SE mitigation. The insertion of decoupling cells shows interesting outcomes for power variability control with levels of variation above 4%, and it can attenuate until 10% the delay variability considering manufacturing process with 3% of WFF. Depending on the LET, the design with decoupling cells can decrease until 10% of SE susceptibility of logic cells. The use of Schmitt Triggers in the output of FinFET cells can improve the variability sensitivity by up to 50%. The sleep transistor approach improves the power variability reaching around 12% for WFF of 5%, but the advantages of this method to delay variability depends how the transistors are arranged with the sleep transistor in the pull-down network. The addition of a sleep transistor become all logic cells studied free of faults even at the near-threshold regime. In this way, the best approach to mitigate the process variability is the use of Schmitt Triggers, as well as the sleep transistor technique, is the most efficient for the SE mitigation. However, the Schmitt Trigger technique presents the highest penalties in area, performance, and power. Therefore, depending on the application, the sleep transistor or decoupling cells technique can be the most appropriate to mitigate the process variability effects. 4 Resumo A variabilidade de processo e a resistência a radiação são requisitos de confiabilidade relevantes à medida que a fabricação de chips avança mais a fundo no regime nanométrico. A perda de rendimento paramétrico e as falhas críticas no comportamento do sistema são as principais consequências destes problemas. Alguns trabalhos relacionados exploram a influência da variabilidade de processo e dos eventos transientes únicos (SET) nos circuitos projetados nas tecnologias FinFET, mas existe uma ausência de abordagens para mitigar eles. Por estas razões, do ponto de vista de projeto, esforços consideráveis devem ser feitos para entender e reduzir os impactos introduzidos pelos desafios de confiabilidade. Dessa forma, as principais contribuições desta tese de doutorado são: 1) investigar o comportamento de células lógicas FinFET sob variações de processo e efeitos de radiação; 2) avaliar quatro abordagens em nível de circuito para atenuar o impacto causado por flutuações na função trabalho (WFF) and soft errors (SE); 3) fornecer uma comparação global entre todas as técnicas aplicadas neste trabalho; 4) Traçar um balanceamento entre os ganhos e as penalidades de cada abordagem em relação ao desempenho, potência, área, seção transversal SET e largura de pulso SET. Reordenamento de transistores, e o uso de decoupling
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