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Ipug35 05.0 Table of Contents DDR & DDR2 SDRAM Controller IP Cores User’s Guide February 2012 ipug35_05.0 Table of Contents Chapter 1. Introduction .......................................................................................................................... 5 Quick Facts ........................................................................................................................................................... 5 Features ................................................................................................................................................................ 6 Chapter 2. Functional Description ........................................................................................................ 7 Command Decode Logic.............................................................................................................................. 7 Configuration Interface................................................................................................................................. 8 sysCLOCK PLL............................................................................................................................................ 8 Data Path Logic............................................................................................................................................ 8 Initialization State Machine .......................................................................................................................... 8 Command Application Logic ........................................................................................................................ 8 DDR I/O Modules......................................................................................................................................... 8 Signal Descriptions ............................................................................................................................................... 9 Using the Local User Interface............................................................................................................................ 10 Initialization and Auto-Refresh Control....................................................................................................... 10 Command and Address ............................................................................................................................. 11 Data Write .................................................................................................................................................. 13 Data Read.................................................................................................................................................. 14 Read/Write with Auto Precharge................................................................................................................ 14 Local-to-Memory Address Mapping ........................................................................................................... 14 Mode Register Programming ..................................................................................................................... 15 Memory Interface ................................................................................................................................................ 18 Chapter 3. Parameter Settings ............................................................................................................ 19 Mode Tab ............................................................................................................................................................ 21 Type Tab ............................................................................................................................................................. 22 Select Memory ........................................................................................................................................... 22 Clock .......................................................................................................................................................... 22 Memory Data Bus Size .............................................................................................................................. 22 Configuration.............................................................................................................................................. 22 Data_rdy to Write Data Delay .................................................................................................................... 23 Clock Width................................................................................................................................................ 23 CKE Width.................................................................................................................................................. 23 DIMM Selection.......................................................................................................................................... 23 Fixed Memory Timing................................................................................................................................. 23 Command Burst Enable............................................................................................................................. 23 Use Differential DQS.................................................................................................................................. 23 Setting Tab.......................................................................................................................................................... 24 Row Size.................................................................................................................................................... 24 Column Size............................................................................................................................................... 24 Bank Size................................................................................................................................................... 24 Chip Select Width....................................................................................................................................... 24 User Slot Size ............................................................................................................................................ 24 EMR Prog During Init ................................................................................................................................. 25 Auto Refresh Burst Count .......................................................................................................................... 25 External Auto Refresh Port ........................................................................................................................ 25 Mode Register Initial Setting ...................................................................................................................... 25 Timing Tab .......................................................................................................................................................... 25 DQS Pin Selection Tab (DDR2 Only).................................................................................................................. 27 Synthesis & Simulation Tools Option Tab........................................................................................................... 27 Info Tab ............................................................................................................................................................... 28 © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG35_05.0, February 2012 2 DDR & DDR2 IP Cores User’s Guide Table of Contents Chapter 4. IP Core Generation............................................................................................................. 29 Licensing the IP Core.......................................................................................................................................... 29 Getting Started .................................................................................................................................................... 29 IPexpress-Created Files and Top Level Directory Structure............................................................................... 31 Generated Files................................................................................................................................................... 32 DDR Memory Controller Core Structure ............................................................................................................. 34 Top-level Wrapper...................................................................................................................................... 34 Encrypted Netlist........................................................................................................................................ 34 I/O Modules................................................................................................................................................ 34 Clock Generator........................................................................................................................................
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