Xing Sheng, EE@Tsinghua Principles of Micro- and Nanofabrication for Electronic and Photonic Devices Packaging and Integration Xing Sheng 盛 兴 Department of Electronic Engineering Tsinghua University
[email protected] 1 Xing Sheng, EE@Tsinghua Packaging Si wafers IC chips Video 3 Xing Sheng, EE@Tsinghua Packaging Si wafers IC chips test, wafer thinning, dicing, bonding, ... 4 Xing Sheng, EE@Tsinghua Probe Test 5 Xing Sheng, EE@Tsinghua Wafer Thinning typically, ~100 m can be as thin as 20 m 6 Xing Sheng, EE@Tsinghua Wafer Thinning 7 Xing Sheng, EE@Tsinghua Dicing laser saw plasma ... 8 Xing Sheng, EE@Tsinghua Wire Bonding 9 Xing Sheng, EE@Tsinghua 'Flip-Chip' Die Bonding Metals alloys: Pb, Cu, Ag, Sn, ... low melting point 10 Xing Sheng, EE@Tsinghua Eutectic Bonding Au Si 11 Xing Sheng, EE@Tsinghua Infrared Imaging Si is transparent at near-infrared (> 1100 nm) 12 Xing Sheng, EE@Tsinghua Through-Silicon Via (TSV) Conductive channels through the silicon wafer 13 Xing Sheng, EE@Tsinghua Through-Silicon Via (TSV) Conductive channels through the silicon wafer 14 Xing Sheng, EE@Tsinghua Silicon Interposer A conductive interface between chips and substrates interposer Q: Why shall we use Si? 15 Xing Sheng, EE@Tsinghua Memory Chips . Increase the memory volume by 3D chip stacks 16 Xing Sheng, EE@Tsinghua 2D -> 2.5D - 3D reduced size, faster speed, higher performance, ... Video 17 Xing Sheng, EE@Tsinghua 3D IC . Logic + Memory + Sensing + ... conventional 3D IC M. M. Shulaker, et al., Nature 547, 74 (2017) 18 Xing Sheng, EE@Tsinghua Chip Packaging Q: Why is the package black? 19 Xing Sheng, EE@Tsinghua X-ray Inspection of Circuit X-ray image 20 Xing Sheng, EE@Tsinghua X-ray Inspection of Circuit M.