Plasma-Activated Fusion Bonding for Vacuum Encapsulation of Microdevices Joel Soman Louisiana Tech University
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Wafer Bonding Methods
Wafer Bonding Methods ADVANCED TECHNOLOGY FOR KNOWLEDGE BASE FACT RESEARCH & INDUSTRY SHEET • SCOPE: This document provides an overview of the different wafer bonding methods used in semiconductor manufacturing. Wafer bonding refers to the attachment of two or more substrates or wafers to one another through a range of physical and chemical processes. Wafer bonding is used in a variety of technologies such as MEMS device fabrication, where sensor components are encapsulated within the application. Other areas of application are in three-dimensional integration, advanced packaging technologies and CIS manufacturing. Within wafer bonding there are two main groupings, temporary bonding and permanent bonding, both of which play a key part in the technologies that facilitate three-dimensional integration. The main techniques used in wafer bonding are: • Adhesive • Anodic • Eutectic • Fusion • Glass Frit • Metal Diffusion • Hybrid • Solid liquid inter-diffusion (SLID) Adhesive bonding Adhesive bonding utilises a range of polymers and adhesives to attach the wafers to one another. These polymers include epoxies, dry films, BCB, polyimides and UV curable compounds. Adhesive bonding is widely utilised throughout the microelectronic and MEMS manufacture industry as it is a simple robust and often low cost solution. A major advantage for their use is the comparatively low temperature for protecting sensitive components allowing compatibility with standard integrated circuit materials and processes. Other advantages include the ability to join different types and materials of substrate together and insensitivity to surface topography. Additionally adhesive bonding can be used for both permanent and temporary wafer bonding. In an adhesive bond it is the polymer adhesive that bears the force needed to hold the two surfaces together and also distributes this force evenly across the substrate surfaces to avoid localised any stresses across the join. -
Localized Parylene-C Bonding with Reactive Multilayer Foils
Home Search Collections Journals About Contact us My IOPscience Localized Parylene-C bonding with reactive multilayer foils This content has been downloaded from IOPscience. Please scroll down to see the full text. 2009 J. Phys. D: Appl. Phys. 42 185411 (http://iopscience.iop.org/0022-3727/42/18/185411) View the table of contents for this issue, or go to the journal homepage for more Download details: IP Address: 149.169.115.242 This content was downloaded on 09/02/2015 at 04:04 Please note that terms and conditions apply. IOP PUBLISHING JOURNAL OF PHYSICS D: APPLIED PHYSICS J. Phys. D: Appl. Phys. 42 (2009) 185411 (6pp) doi:10.1088/0022-3727/42/18/185411 Localized Parylene-C bonding with reactive multilayer foils Xiaotun Qiu1, Jie Zhu1, Jon Oiler2, Cunjiang Yu3, Ziyu Wang2 and Hongyu Yu1,2 1 Department of Electrical Engineering, Arizona State University, Tempe, AZ, 85287, USA 2 School of Earth and Space Exploration, Arizona State University, Tempe, AZ, 85287, USA 3 Department of Mechanical and Aerospace Engineering, Arizona State University, Tempe, AZ, 85287, USA Received 1 June 2009, in final form 12 July 2009 Published 4 September 2009 Online at stacks.iop.org/JPhysD/42/185411 Abstract This paper describes a novel bonding technique using reactive multilayer Ni/Al foils as local heat sources to bond Parylene-C layers to another Parylene-C coating on a silicon wafer. Exothermic reactions in Ni/Al reactive multilayer foils were investigated by x-ray diffraction (XRD) and differential scanning calorimetry. XRD measurements showed that the dominant product after exothermic reaction was ordered B2 AlNi compound. -
Copper Thermocompression for Mems Encapsulation
Henri Ailas COPPER THERMOCOMPRESSION FOR MEMS ENCAPSULATION Master’s Programme in Chemical, Biochemical and Materials Engineering Major in Chemistry Master’s thesis for the degree of Master of Science in Technology submitted for inspection, Espoo, 5th of April, 2019 Supervisor Prof. Kari Laasonen Advisors D.Sc. Jaakko Saarilahti D.Sc. Jyrki Kiihamäki Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Henri Ailas Title Copper thermocompression for MEMS encapsulation Degree programme Chemical, Biochemical and Materials Engineering Major Chemistry Code of major CHEM3023 Thesis supervisor Prof. Kari Laasonen Thesis advisors D.Sc. Jaakko Saarilahti, D.Sc. Jyrki Kiihamäki Date 5.4.2019 Number of pages 92+5 Language English Abstract Copper thermocompression is a promising wafer-level packaging technique, as it al- lows the bonding of electric contacts simultaneously to hermetic encapsulation. In thermocompression bonding the bond is formed by diffusion of atoms from one bond interface to another. The diffusion is inhibited by barrier forming surface oxide, high surface roughness and low temperature. Aim of this study was to establish a wafer-level packaging process for MEMS (Micro- ElectroMechanical System) mirror and MEMS gyroscope. The cap wafer of the MEMS mirror has an antireflective coating that limits the thermal budget of the bonding process to 250°C. This temperature is below the eutectic temperature of most com- mon eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C). Thus a thermocompression bonding method needed to be developed. Cop- per was used as a bonding material due to its low cost, high self-diffusivity and re- sistance to oxidation in ambient air. -
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Degree project in Microsystem Technology Second level Stockholm, Sweden 2011 XR-EE-MST 2011:005 Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Master’s Degree Project in Microsystem Technology (MST) KTH Royal Institute of Technology Stockholm, Sweden Supervisor: Henrik Gradin Examine: Wouter van der Wijngaart September 2011 Abstract The objective of this research work was to investigate the low temperature gold silicon eutectic bonding of SMA with silicon wafers. The research work was carried out to optimize a bond process with better yield and higher bond strength. The gold layer thickness, processing temperature, diffusion barrier, adhesive layer, and the removal of silicon oxide are the important parameters in determining a reliable and uniform bond. Based on the previous work on Au-Si eutectic bonding, 7 different Si substrates were prepared to investigate the effect of above mentioned parameters. Cantilevers with different bond sizes were prepared from SMA and steel sheets. Afterwards, these cantilevers were bonded to the prepared substrates. The bond yield and bond strength are the two parameters which establish the bond quality. Quantitative analysis was carried out by shear tests. Scanning Electron Microscopy (SEM) and Mapping were used for the analysis of the bond interface and diffusion of elements across the bond. The research has resulted in bonding of SMA cantilevers onto silicon wafers with high yield and bond strength. Steel cantilever can also be bonded by Au-Si eutectic alloy but the processing of the steel sheet is critical. -
Wafer Bonding Enables New Technologies and Applications Teikoku Taping Systems
Wafer Bonding Enables New Technologies and Applications Teikoku Taping Systems TTS Confidential Document Prepared by: Mark Franklin At a Glance Forecasts for the demise of Moore’s Law are fairly common. There is a limit to making smaller features where cost and complexity issues become prohibitive. The semiconductor industry has established, rather quickly, a new path forward focused around 3D stacking of integrated circuits. Adding a third dimension to an integrated circuit packs more transistors into the same small footprint without the need to shrink the features of the circuit. The layers are stacked like floors in a skyscraper effectively allowing Moore’s law to continue, albeit, down a slightly different path. 3D integration or vertically stacked chips or wafers requires new technology and new equipment. Just as chemical mechanical polishing (CMP) became the enabling technology for the industry years ago; wafer bonding has been identified as its next enabling technology. Changing Landscape Cost of Future Scaling The Governing Paradigm: More than Moore Source: Samsung & Micron Images Temporary Bonding/Debonding Temporary wafer bonding and debonding has emerged as challenging processes necessary for most 3D integration schemes. The selection of a suitable temporary bond process is the key to success. Through silicon via (TSV) processing places significantly higher technical demands on the bond process compared to MEMS or GaAs processing on smaller wafers. The bond process must be able to withstand temperatures of up to 300C or more while at the same time be easily removed at room temperature, opposing objectives. It must be resistant to a wide range of semiconductor chemicals that it will contact, from solvents and acids to plating solutions and cleaning agents. -
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems XIAOJING WANG Doctoral Thesis Stockholm, Sweden, 2019 Front cover pictures: Left: SEM image of an array of vertically assembled microchips that are electrically packaged by wire bonding. Right: Optical image of wafer bonded ultra-thin silicon caps of different sizes for wafer-level vacuum sealing. KTH Royal Institute of Technology School of Electrical Engineering TRITA-EECS-AVL-2019:65 and Computer Science ISBN 978-91-7873-280-7 Department of Micro and Nanosystems Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektroteknik och datavetenskap fredagen den 4:e oktober klockan 10:00 i Sal F3, Lindstedtsvägen 64, Stockholm. Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at KTH Royal Institute of Technology, Stockholm, Sweden. © Xiaojing Wang, September 2019 Tryck: Universitetsservice US AB, 2019 iii Abstract Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high- throughput heterogeneous integration challenges for emerging applications. The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding. -
Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic Metal Bonding of Wafers Is Used in Advanced MEMS Packaging and 3D Integration Technologies
2008 . July Issue Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic metal bonding of wafers is used in advanced MEMS packaging and 3D integration technologies. A unique feature of eutectic metals is the melting of the solder like alloys that facilitate surface planarization and provide a tolerance to surface topography and particles. Advanced wafer level bonding using 2-3um thick metal layers allows precision alignment preventing the aberrant viscous flow of the metal and wafer slippage. Also in this issue: • C4NP Next Generation Wafer Bumping Page 2 index 3 The Age of 3D Integration 12 Application Notes Wilfried Bair Tips to Get The Most Out Vice President Strategic Business Development, of Data Viewer SUSS MicroTec Sumant Sood, SUSS MicroTec 4 C4NP Next Generation Wafer 13 New Office in USA Bumping Anton Wolejnik, Managing Director, SUSS MicroTec Changing bumping requirements driven by 3D Packaging Klaus Ruhmer and Emmett Hughlett, 14 Clif´s Notes SUSS MicroTec You Can Define That Exposure Dose In One Wafer! 6 Precision Wafer to Wafer Clifford J. Hamel, Packaging Using Eutectic SUSS MicroTec Metal Bonding Shari Farrens, Ph.D. and Sumant Sood, SUSS MicroTec 18 SUSS in the News 20 Tradeshows/Conferences SUSS Scores First Place for 10th Year as Material Handling Supplier Page 3 Full View The Age of Integration 3D When commercial wafer bonders processes. A commonly used com- were first introduced to the industry parison of 3D integration with real in the early 90’s the main driver for estate illustrates that when silicon this new equipment type was the space is at a premium or cannot be then emerging MEMS technology. -
Reactive Multilayer Foils and Their Applications in Joining Xiaotun Qiu Louisiana State University and Agricultural and Mechanical College, [email protected]
Louisiana State University LSU Digital Commons LSU Master's Theses Graduate School 2007 Reactive multilayer foils and their applications in joining Xiaotun Qiu Louisiana State University and Agricultural and Mechanical College, [email protected] Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_theses Part of the Mechanical Engineering Commons Recommended Citation Qiu, Xiaotun, "Reactive multilayer foils and their applications in joining" (2007). LSU Master's Theses. 2091. https://digitalcommons.lsu.edu/gradschool_theses/2091 This Thesis is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Master's Theses by an authorized graduate school editor of LSU Digital Commons. For more information, please contact [email protected]. REACTIVE MULTILAYER FOILS AND THEIR APPLICATIONS IN JOINING A Thesis Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Master of Science in Mechanical Engineering in The Department of Mechanical Engineering By Xiaotun Qiu B.S., Tsinghua University, Beijing, China, 2004 August, 2007 ACKNOWLEDGEMENTS I wish to thank my advisor, Dr. Jiaping Wang, for providing me a chance to work on such an innovative project, which paved the way to build my thesis. It is such a great privilege working with her and she is such an inspiration that she got the best out of me. I am also indebted to Dr. Laszlo Kecskes for helping me to conduct the DSC experiment for the cold rolled multilayer foils. I am very thankful to Dr. -
Packaging and Integration
Xing Sheng, EE@Tsinghua Principles of Micro- and Nanofabrication for Electronic and Photonic Devices Packaging and Integration Xing Sheng 盛 兴 Department of Electronic Engineering Tsinghua University [email protected] 1 Xing Sheng, EE@Tsinghua Packaging Si wafers IC chips Video 3 Xing Sheng, EE@Tsinghua Packaging Si wafers IC chips test, wafer thinning, dicing, bonding, ... 4 Xing Sheng, EE@Tsinghua Probe Test 5 Xing Sheng, EE@Tsinghua Wafer Thinning typically, ~100 m can be as thin as 20 m 6 Xing Sheng, EE@Tsinghua Wafer Thinning 7 Xing Sheng, EE@Tsinghua Dicing laser saw plasma ... 8 Xing Sheng, EE@Tsinghua Wire Bonding 9 Xing Sheng, EE@Tsinghua 'Flip-Chip' Die Bonding Metals alloys: Pb, Cu, Ag, Sn, ... low melting point 10 Xing Sheng, EE@Tsinghua Eutectic Bonding Au Si 11 Xing Sheng, EE@Tsinghua Infrared Imaging Si is transparent at near-infrared (> 1100 nm) 12 Xing Sheng, EE@Tsinghua Through-Silicon Via (TSV) Conductive channels through the silicon wafer 13 Xing Sheng, EE@Tsinghua Through-Silicon Via (TSV) Conductive channels through the silicon wafer 14 Xing Sheng, EE@Tsinghua Silicon Interposer A conductive interface between chips and substrates interposer Q: Why shall we use Si? 15 Xing Sheng, EE@Tsinghua Memory Chips . Increase the memory volume by 3D chip stacks 16 Xing Sheng, EE@Tsinghua 2D -> 2.5D - 3D reduced size, faster speed, higher performance, ... Video 17 Xing Sheng, EE@Tsinghua 3D IC . Logic + Memory + Sensing + ... conventional 3D IC M. M. Shulaker, et al., Nature 547, 74 (2017) 18 Xing Sheng, EE@Tsinghua Chip Packaging Q: Why is the package black? 19 Xing Sheng, EE@Tsinghua X-ray Inspection of Circuit X-ray image 20 Xing Sheng, EE@Tsinghua X-ray Inspection of Circuit M. -
Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli
Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli B.Tech., Indian Institute of Technology - Madras, India (2000) S.M., Massachusetts Institute of Technology (2002) Submitted to the Department of Materials Science and Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY February 2007 © Massachusetts Institute of Technology 2007. All rights reserved. Author ................................................................................................................ Department of Materials Science and Engineering 6 November 2006 Certified by ........................................................................................................ Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering Thesis Supervisor Accepted by ....................................................................................................... Samuel M. Allen POSCO Professor of Physical Metallurgy Chair, Departmental Committee on Graduate Students 2 Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli Submitted to the Department of Materials Science and Engineering on 6 November 2006, in partial fulfillment of the requirements for the degree of Doctor of Philosophy Abstract Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and -
Efficient Joining Using Reactive Multilayer Systems
ECEMP – European Centre for Emerging Materials and Processes Dresden EFFICIENT JOINING USING REACTIVE MULTILAYER SYSTEMS Autoren Dietrich, G.1*, Pflug, E.2, Rühl, M.2, Braun, S.1, Leson, A.1, Beyer, E.2 1 Fraunhofer Institute Material and Beam Technologies (IWS), Dresden, Germany 2 Technical University of Dresden, Dresden, Germany * Contact: Dipl.-Ing. G. Dietrich, Scientist Fraunhofer Institute Material and Beam Technologies (IWS), Winterbergstrasse 28, 01277 Dresden, Germany E-mail: [email protected] ECEMP-Sprecher:II Prof. Dr.-Ing. habil. Prof. E. h. Dr. h. c. Werner A. Hufenbach Technische Universität Dresden, Marschnerstraße 39, 01307 Dresden Tel.: 0351 463 38446 Fax: 0351 463 38449 C1 E-Mail: [email protected] INHALTSVERZEICHNIS 1 ABSTRACT .................................................................................................................... 3 2 PRINCIPLE OF REACTIVE MULTILAYER SYSTEMS (RMS) ......................................... 4 Seite 2 1 Abstract 1 ABSTRACT Established joining techniques like welding, soldering or brazing typically are characterized by a large amount of heat input into the components. Especially in the case of heat sensitive structures like MEMS this often results in stress induced deformation and degradation or even in damaging the parts. Therefore, there is an urgent need for a more reliable and reproducible method for joining, which is characterized by a well defined and small heat input for only a short time period. So-called reactive nanometer multilayers offer a promising approach to meet these needs. Reactive nanometer multilayers consist of several hundreds or thousands of alternating nanoscale layers, which can exothermicly react with each other. Placing a reactive nanometer multilayer coated with a solder or brazing layer between two surfaces, it can be used as a controllable local heat source for joining. -
Investigation of Eutectic and Solid State Wafer Bonding of Silicon with Gold
Investigation of Eutectic and Solid State Wafer Bonding of Silicon with Gold by Maryam Abouie A thesis submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Materials Engineering Department of Chemical and Materials Engineering University of Alberta © Maryam Abouie, 2014 ABSTRACT Permanent wafer bonding technology is a very important process for different types of applications such as MEMS (microelectromechanical systems), LED (light-emitting diode) devices, advanced packaging, 3D stack and SOI (silicon on isolator) substrate applications. Depending on the type of application, several bonding technologies exist. The MEMS market road map suggests the market for MEMS will be close to $21B in 2017. The driving force for development of different wafer bonding processes is the large applications that need to be addressed. The wafer bonding market generated almost 5 million 8-inch wafers bonded for BSI (back-illuminated sensor), CIS (CMOS image sensor) and MEMS device applications and it is expected to reach 16 million 8-inch bonded wafers in 2019. The growing demand is mainly driven by the miniaturization required for 3D Stack TSV (through- silicon via) applications. Among different wafer bonding techniques, eutectic bonding is more appealing due to its good hermeticity, ability to create electrical connection, good mechanical strength and low temperature processing. In this study, Au-Si eutectic bonding was applied due to its high bonding strength, excellent hermeticity and good tolerance to surface topology prior to bonding. Au/a-Si wafer bonding was introduced in order to reduce the risk of possible damage to active devices in Au/c-Si wafer bonding due to formation of large craters in c-Si.