Lecture 24 Wafer Bonding and Packaging
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Copper Wire Bond Failure Mechanisms
COPPER WIRE BOND FAILURE MECHANISMS Randy Schueller, Ph.D. DfR Solutions Minneapolis, MN ABSTRACT formation with copper wire. Wire bonding a die to a package has traditionally been performed using either aluminum or gold wire. Gold wire If copper were an easy drop-in replacement for gold the provides the ability to use a ball and stitch process. This industry would have made the change long ago. technique provides more control over loop height and bond Unfortunately copper has a few mechanical property placement. The drawback has been the increasing cost of the differences that make it more difficult to use as a wire bond gold wire. Lower cost Al wire has been used for wedge- material. Cu has a higher Young’s Modulus (13.6 vs. 8.8 2 wedge bonds but these are not as versatile for complex N/m ), thus it is harder than gold and, more significantly, package assembly. The use of copper wire for ball-stitch copper work hardens much more rapidly than gold. This bonding has been proposed and recently implemented in means that during the compression of the ball in the bonding high volume to solve the cost issues with gold. As one operation, the copper ball becomes much harder while the would expect, bonding with copper is not as forgiving as gold remains soft and deforms more easily. A thin layer of with gold mainly due to oxide growth and hardness oxide on the copper also makes bonding more challenging, differences. This paper will examine the common failure especially on the stitch side of the bond. -
Wafer Bonding Methods
Wafer Bonding Methods ADVANCED TECHNOLOGY FOR KNOWLEDGE BASE FACT RESEARCH & INDUSTRY SHEET • SCOPE: This document provides an overview of the different wafer bonding methods used in semiconductor manufacturing. Wafer bonding refers to the attachment of two or more substrates or wafers to one another through a range of physical and chemical processes. Wafer bonding is used in a variety of technologies such as MEMS device fabrication, where sensor components are encapsulated within the application. Other areas of application are in three-dimensional integration, advanced packaging technologies and CIS manufacturing. Within wafer bonding there are two main groupings, temporary bonding and permanent bonding, both of which play a key part in the technologies that facilitate three-dimensional integration. The main techniques used in wafer bonding are: • Adhesive • Anodic • Eutectic • Fusion • Glass Frit • Metal Diffusion • Hybrid • Solid liquid inter-diffusion (SLID) Adhesive bonding Adhesive bonding utilises a range of polymers and adhesives to attach the wafers to one another. These polymers include epoxies, dry films, BCB, polyimides and UV curable compounds. Adhesive bonding is widely utilised throughout the microelectronic and MEMS manufacture industry as it is a simple robust and often low cost solution. A major advantage for their use is the comparatively low temperature for protecting sensitive components allowing compatibility with standard integrated circuit materials and processes. Other advantages include the ability to join different types and materials of substrate together and insensitivity to surface topography. Additionally adhesive bonding can be used for both permanent and temporary wafer bonding. In an adhesive bond it is the polymer adhesive that bears the force needed to hold the two surfaces together and also distributes this force evenly across the substrate surfaces to avoid localised any stresses across the join. -
Thermosonic Wire Bonding
Thermosonic Wire Bonding General Guidelines Application Note – AN1002 1. Introduction 1.1. Wire Bonding Methods Wire bonding is a solid state welding process, where two metallic materials are in intimate contact, and the rate of metallic interdiffusion is a function of temperature, force, ultrasonic power, and time. There are three wire bonding technologies: thermocompression bonding, thermosonic bonding, and ultrasonic bonding. Thermocompression bonding is performed using heat and force to deform the wire and make bonds. The main process parameters are temperature, bonding force, and time. The diffusion reactions progress exponentially with temperature. So, small increases in temperature can improve bond process significantly. In general, thermocompression bonding requires high temperature (normally above 300°C), high force, and long bonding time for adequate bonding. The high temperature and force can damage some sensitive dies. In addition, this process is very sensitive to bonding surface contaminants. Thermocompression is, therefore, seldom used now in optoelectronic and IC applications. Thermosonic bonding is performed using a heat, force, and ultrasonic power to bond a gold (Au) wire to either an Au or an aluminum (Al) surface on a substrate. Heat is applied by placing the package on a heated stage. Some bonders also have heated tool, which can improve the wire bonding performance. Force is applied by pressing the bonding tool into the wire to force it in contact with the substrate surface. Ultrasonic energy is applied by vibrating the bonding tool while it is in contact with the wire. Thermosonic process is typically used for Au wire/ribbon. Ultrasonic bonding is done at room temperature and performed by a combination of force and ultrasonic power. -
Copper Wire Bonding
Copper Wire Bonding Preeti S. Chauhan • Anupam Choubey ZhaoWei Zhong • Michael G. Pecht Copper Wire Bonding Preeti S. Chauhan Anupam Choubey Center for Advanced Life Cycle Industry Consultant Engineering (CALCE) Marlborough, MA, USA University of Maryland College Park, MD, USA Michael G. Pecht Center for Advanced Life Cycle ZhaoWei Zhong Engineering (CALCE) School of Mechanical University of Maryland & Aerospace Engineering College Park, MD, USA Nanyang Technological University Singapore ISBN 978-1-4614-5760-2 ISBN 978-1-4614-5761-9 (eBook) DOI 10.1007/978-1-4614-5761-9 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2013939731 # Springer Science+Business Media New York 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. -
For Copper Wire Bonds E
Body of Knowledge (BOK) for Copper Wire Bonds E. Rutkowski1 and M. J. Sampson2 1. ARES Technical Services Corporation, 2. NASA Goddard Space Flight Center Executive Summary Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate – approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. -
Chapter 9 Chip Bonding At
9 CHIP BONDING AT THE FIRST LEVEL The I/O interface to the die primarily interconnects electrical power, ground and signals. It must provide for low impedance for the power distribution system, so as to keep switching noise within specification, and controlled impedance for the signal leads to allow adequate signal integrity. In addition it must accommodate all the I/O and power and ground leads required, and at the same time, minimize the cost for high volume assembly. The secondary role of chip bonding is to be mechanically robust, not interfere with thermal man- agement and be the geometrical transformer from the die features to the next level of packaging features. There are many options for the next level of interconnect, including: ¥ leadframe in a single chip package ¥ ceramic substrate in a single chip package ¥ laminate substrate in a single chip package ¥ ceramic substrate in a multichip module ¥ laminate substrate in a multichip module ¥ glass substrate, such as an LCD (liquid crystal display) ¥ laminate substrate, such as a circuit board ¥ ceramic substrate, such as a circuit board For all of these first level interfaces, the chip bonding options are the same. Illustrated in Figure 9-1, they are: ¥ wirebond ¥ TAB (tape automated bonding) ¥ flip chip; either with a solder interface, a polymer adhesive or a welded joint Because of the parallel efforts in widely separated applications involving similar, but slightly dif- ferent variations of chip attach techniques, seemingly confusing names have historically evolved to describe some of the attach technologies. COG (chip on glass) refers to assembly of bare die onto LCD panels. -
Copper Thermocompression for Mems Encapsulation
Henri Ailas COPPER THERMOCOMPRESSION FOR MEMS ENCAPSULATION Master’s Programme in Chemical, Biochemical and Materials Engineering Major in Chemistry Master’s thesis for the degree of Master of Science in Technology submitted for inspection, Espoo, 5th of April, 2019 Supervisor Prof. Kari Laasonen Advisors D.Sc. Jaakko Saarilahti D.Sc. Jyrki Kiihamäki Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Henri Ailas Title Copper thermocompression for MEMS encapsulation Degree programme Chemical, Biochemical and Materials Engineering Major Chemistry Code of major CHEM3023 Thesis supervisor Prof. Kari Laasonen Thesis advisors D.Sc. Jaakko Saarilahti, D.Sc. Jyrki Kiihamäki Date 5.4.2019 Number of pages 92+5 Language English Abstract Copper thermocompression is a promising wafer-level packaging technique, as it al- lows the bonding of electric contacts simultaneously to hermetic encapsulation. In thermocompression bonding the bond is formed by diffusion of atoms from one bond interface to another. The diffusion is inhibited by barrier forming surface oxide, high surface roughness and low temperature. Aim of this study was to establish a wafer-level packaging process for MEMS (Micro- ElectroMechanical System) mirror and MEMS gyroscope. The cap wafer of the MEMS mirror has an antireflective coating that limits the thermal budget of the bonding process to 250°C. This temperature is below the eutectic temperature of most com- mon eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C). Thus a thermocompression bonding method needed to be developed. Cop- per was used as a bonding material due to its low cost, high self-diffusivity and re- sistance to oxidation in ambient air. -
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Degree project in Microsystem Technology Second level Stockholm, Sweden 2011 XR-EE-MST 2011:005 Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Master’s Degree Project in Microsystem Technology (MST) KTH Royal Institute of Technology Stockholm, Sweden Supervisor: Henrik Gradin Examine: Wouter van der Wijngaart September 2011 Abstract The objective of this research work was to investigate the low temperature gold silicon eutectic bonding of SMA with silicon wafers. The research work was carried out to optimize a bond process with better yield and higher bond strength. The gold layer thickness, processing temperature, diffusion barrier, adhesive layer, and the removal of silicon oxide are the important parameters in determining a reliable and uniform bond. Based on the previous work on Au-Si eutectic bonding, 7 different Si substrates were prepared to investigate the effect of above mentioned parameters. Cantilevers with different bond sizes were prepared from SMA and steel sheets. Afterwards, these cantilevers were bonded to the prepared substrates. The bond yield and bond strength are the two parameters which establish the bond quality. Quantitative analysis was carried out by shear tests. Scanning Electron Microscopy (SEM) and Mapping were used for the analysis of the bond interface and diffusion of elements across the bond. The research has resulted in bonding of SMA cantilevers onto silicon wafers with high yield and bond strength. Steel cantilever can also be bonded by Au-Si eutectic alloy but the processing of the steel sheet is critical. -
Wafer-To-Wafer Permanent Bonding
REVERSE COSTING® – STRUCTURAL, PROCESS & COST REPORT Wafer Bonding Comparison Permanent Bonding – Physical analysis and Cost Overview MEMS, Imaging, LED, Packaging report by Audrey LAHRACH November 2018 – Sample 22 bd Benoni Goullin 44200 NANTES - FRANCE +33 2 40 18 09 16 [email protected] www.systemplus.fr ©2018 by System Plus Consulting | Wafer to Wafer Permanent Bonding Comparison 2018 1 Table of Contents Overview / Introduction 5 o Thermo-compression Bonding o Executive Summary o MEMS RF o Reverse Costing Methodology o MEMS Inertial Sensor Permanent Wafer Bonding Technology 9 Physical Comparison 140 Permanent Wafer Bonding Definition and Process Description 13 o Without intermediate layer Cost Comparison 164 o Fusion Bonding o CMOS Image Sensor Feedbacks 168 o MEMS Inertial Sensor SystemPlus Consulting services 170 o Cu-Cu/Oxide Hybrid Bonding o CMOS Image Sensor o Anodic Bonding o MEMS Pressure Sensor o With intermediate layer o Glass Frit o MEMS Pressure Sensor o MEMS Inertial Sensor o Adhesive Bonding o MEMS Micro-mirror o Eutectic Bonding o MEMS Inertial Sensor o Microbolometer o LED ©2018 by System Plus Consulting | Wafer to Wafer Permanent Bonding Comparison 2018 2 Executive Summary Overview / Introduction o Executive Summary This comparative review has been conducted to provide insights into the structures, processes and costs of the main o Reverse Costing Methodology permanent wafer bonding technologies. o Glossary Wafer Bonding Technology Among these technologies, we have identified two main groups. One, bonding wafers without intermediate layers, includes Wafer Bonding Definition and fusion, copper-copper hybrid and anodic bonding approaches. The second group involves bonding wafers with intermediate Process Description layers using an insulator like a glass frit, or a metal in eutectic and thermocompression approaches. -
Mechanical Characterization of Glass Frit Bonded Wafers
IMEKO TC15 - Experimental Mechanics - Proceedings of the 11th Youth Symposium on Experimental Solid Mechanics Brasov, ROMANIA, 2012, May 30-June 2 MECHANICAL CHARACTERIZATION OF GLASS FRIT BONDED WAFERS K. VOGEL1, 2 D. WUENSCH2 S. UHLIG 2 J. FROEMEL1 F. NAUMANN3 M. WIEMER1 T. GESSNER1, 2 Abstract: Wafer bonding is a key technology in the manufacturing of microelectronic and micromechanical systems on industrial scale. Especially glass frit bonding is often used for the encapsulation of MEMS devices on wafer level. To ensure the reliability of these bonds and to prevent critical failure of the systems, characteristic mechanical properties of the bonded interface are required. The fracture toughness and the shear strength are suitable values to characterize the bonding strength and can be determined by micro chevron and shear testing. They depend on the bonding parameters as well as the test speed. Due to the correlation between measured bonding strength and test speed a maximum test speed has to be identified to obtain reliable failure criteria regarding the fracture toughness and the shear strength. Key words: glass frit bonding, stress intensity coefficient, fracture toughness, shear strength, influence of test speed. 1. Introduction the bonding strength. They enable an estimation of lifetime for the whole MEMS Wafer bonding is a key technology in the device as well as the comparison of manufacturing of micro electro mechanical different bonding technologies and process systems (MEMS) on industrial scale. It parameters during bonding. describes various techniques of joining two wafers with or without thin intermediate 2. Technology and Methods layers. Thereby, glass frit bonding is used in a wide range of industrial applications, 2.1. -
Copyrighted Material
1 Part One Technologies COPYRIGHTED MATERIAL A. Adhesive and Anodic Bonding 3 1 Glass Frit Wafer Bonding Roy Knechtel Glass frit wafer bonding is widely used in industrial microsystems applications where fully processed wafers have to be bonded. This end - of - process - line bonding must fulfi ll some very specifi c requirements, such as: process temperature limited to 450 ° C to prevent any temperature - related damage to wafers, no aggressive cleaning to avoid metal corrosion, high process yield since wafer processing to this stage is expensive, bonding of wafers with certain surface roughness or even surface steps resulting from metal lines electrically running at the bonding inter- face to enable electrical connections into the cavity sealed by the wafer bonding, as well as a mechanically strong, hermetically sealed, reliable bond. All of these requirements are fulfi lled by the glass frit wafer bonding process, which addition- ally can be very universally applied since it can be used to bond almost all surfaces common in microelectronics and microsystem technologies. 1.1 Principle of Glass Frit Bonding The basic principle of glass frit bonding is the use of glass as a special intermedi- ate bonding layer. This glass must have a low - temperature melting point. In the bonding process, the glass between the wafers to be bonded is heated, so that its viscosity continually decreases until the so - called wetting temperature is reached, at which point the glass is soft enough and liquid enough to fl ow and wet the wafer surface. In this fl owing process, the glass comes into contact with the surface to be bonded at the atomic level, and fl ows into surface roughnesses and around surface steps. -
Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding
Transactions of The Japan Institute of Electronics Packaging Vol. 8, No. 1, 2015 [Technical Paper] Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding Kazuya Nomura*, Akiko Okada*, Shuichi Shoji*, Toshinori Ogashiwa**, and Jun Mizuno* *Waseda University, 3-4-1 Okubo, Shinjyuku, Tokyo 169-8555, Japan **Tanaka Kikinzoku Kogyo K.K., 2-73 Shinmachi, Hiratsuka, Kanagawa 254-0076, Japan (Received July 30, 2015; accepted November 4, 2015) Abstract We propose a novel fabrication methodology for a hermetic sealing device using an O2 plasma-assisted low temperature Intrinsic-Silicon (I-Si) and glass bonding technique. Glass substrates were used as the cap and base wafers, while I-Si was applied selectively to the contact surface of the cap wafer as an interlayer. A 180-μm-deep cavity was formed in the cap glass by wet etching using a double-layer (photoresist/I-Si) etching mask. I-Si/glass bonding was conducted at 200°C using an I-Si layer-covered glass wafer and a bare glass wafer. Water contact angle measurements and tensile test results showed that the bonding strength increased with promoting surface hydrophilicity through O2 plasma pretreatment. Moreover, scanning acoustic microscope observations revealed that I-Si/glass bonding was achieved successfully without significant voids. Our results indicate that the proposed method could become an indispensable technique for future functional hermetic sealing devices. Keywords: Glass-to-glass Structure, Hermetic Sealing, HF Wet Etching, Intrinsic-silicon/glass