Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems

XIAOJING WANG

Doctoral Thesis Stockholm, Sweden, 2019

Front cover pictures:

Left: SEM image of an array of vertically assembled microchips that are electrically packaged by wire bonding.

Right: Optical image of wafer bonded ultra-thin silicon caps of different sizes for wafer-level vacuum sealing.

KTH Royal Institute of Technology School of Electrical Engineering TRITA-EECS-AVL-2019:65 and Computer Science ISBN 978-91-7873-280-7 Department of Micro and Nanosystems

Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektroteknik och datavetenskap fredagen den 4:e oktober klockan 10:00 i Sal F3, Lindstedtsvägen 64, Stockholm.

Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at KTH Royal Institute of Technology, Stockholm, Sweden.

Tryck: Universitetsservice US AB, 2019 iii

Abstract

Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high- throughput heterogeneous integration challenges for emerging applications.

The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding. Two low-temperature wafer-level vacuum packaging approaches are realized using narrow footprint metal-based sealing rings (Cu- Cu and Al-Au bonding, respectively). As Cu and Al are standard materials used in complementary metal-oxide-semiconductor (CMOS) wafers, these two methods can be used for system-on-chip (SoC) integration of vacuum packaged MEMS with CMOS circuits. Then, an integration method for transferring large-area 2D materials, including graphene, hexagonal boron nitride (h-BN), and molybdenum disulfide (MoS2), from their growth substrates to target substrates and formation of graphene/h-BN heterostructures by adhesive wafer bonding is demonstrated. Such a method would facilitate large-scale fabrication of novel 2D material-based devices.

The second part of this thesis describes two different heterogeneous assembly approaches enabled by wire bonding. The first work realizes scalable vertical integration of microchips that are in-plane fabricated from the source wafer into a separate receiving substrate. The contactless assembly of microchips is realized by magnetic assembly and the electrical contacting is achieved by wire bonding on the sidewalls of the vertically assembled microchips. The second work deals with transfer of carbon nanotubes and Si microstructures from their growth/fabrication substrates to target substrates by utilizing wire bonder as an automated manipulation tool. These methods could be useful for high- throughput 3D integration of microstructures and nanomaterials for various applications.

Keywords: Micro-electromechanical systems (MEMS), heterogeneous integration, wafer bonding, vacuum packaging, hermetic packaging, wire bonding, magnetic assembly, 2D materials, 2D heterostructures, graphene, hexagonal boron nitride(h-BN), molybdenum disulfide (MoS2), carbon nanotubes (CNTs).

Xiaojing Wang, [email protected] Department of Micro and Nanosystems School of Electrical Engineering and Computer Science KTH Royal Institute of Technology, SE 100 44 Stockholm, Sweden iv

Sammanfattning

Heterogen integration förverkligar montering och förpackning av separat tillverkade mikrokomponenter och nya funktionella nanomaterial på samma substrat. Det har varit en nyckelteknologi för att avancera diskreta mikro- och nano-elektromekaniska systemenheter (MEMS/NEMS) och mikroelektroniska komponenter mot kostnad- seffektiva och yteffektiva multifunktionella enheter. Utmaningar kvarstår dock, särskilt när det kommer till skalbara lösningar för att uppnå heterogen integration med hjälp av standardmaterial, processer, och verktyg. Den här avhandlingen presenterar flera integrations- och förpackningsmetoder som använder konventionella skivbindnings- och trådbindningsverktyg för att ta itu med integrationsutmaningar associerade med skal- ning och genomströmning för nya applikationer.

Den första delen av denna avhandling rapporterar tre storskaliga förpacknings- och integrationsteknologier som möjliggörs av skivbindning. Två vakuumförpacknings- metoder med låg temperatur på skivnivå realiseras med hjälp av smala metalbaserade tätningsringar (Cu-Cu respektive Al-Au-bindning). Eftersom Cu och Al är standardmaterial som används i komplementära metalloxidhalvledare (CMOS) -skivor, kan dessa två metoder användas för system-på-chip (SoC) integration av vakuumförpackade MEMS med CMOS-kretsar. Sedan demonstreras en integrationsmetod för att överföra 2D- material med stor yta, inklusive grafen, hexagonal bornitrid (h-BN) och molybdendisulfid (MoS2), från deras tillväxtunderlag till målsubstrat, och bildning av grafen/h-BN heterostrukturer genom klisterbindande skivbindning. En sådan metod skulle underlätta storskalig tillverkning av nya 2D-materialbaserade enheter.

Den andra delen av den här avhandlingen beskriver två olika heterogena monteringsmetoder möjliggjorda genom trådbindning. Det första arbetet realiserar en skalbar vertikal integration av mikrochip som är fabrikerade planparallella med källskivan och överförda till ett separat mottagande substrat. Den kontaktlösa monte- ringen av mikrochip realiseras genom magnetisk montering och den elektriska kontakten uppnås genom trådbindning på sidoväggarna på de vertikalt sammansatta mikrochipen. Det andra arbetet handlar om överföring av kolnanorör och Si-mikrostrukturer från deras tillväxt/tillverkningssubstrat till målsubstrat genom att använda trådbindning som ett automatiserat manipuleringsverktyg. Dessa metoder kan vara användbara för 3D- integration med hög genomströmning av mikrostrukturer och nanomaterial för olika applikationer.

Xiaojing Wang, [email protected] Avdelningen för Mikro- och Nanosystem Skolan för Elektroteknik och Datavetenskap, Kungliga Tekniska Högskolan, 100 44 Stockholm, Sverige v

Contents

Contents ...... v List of Publications ...... vii Abbreviations ...... ix 1 Introduction ...... 1 1.1 Micro and Nanosystems as foundations for a smarter planet ...... 1 1.2 Heterogeneous integration enabling future micro and nanosystems ...... 1 1.2.1 Integration of MEMS and ICs ...... 2 1.2.2 Integrated microsystems based on nanomaterials and flexible substrates ...... 4 1.3 Challenges in heterogeneous integration ...... 4 1.4 Wafer bonding and wire bonding ...... 5 1.4.1 Introduction to wafer bonding ...... 5 1.4.2 Introduction to wire bonding ...... 6 1.5 Objectives of this thesis ...... 7 1.6 Structure of this thesis ...... 8 2 Wafer-level vacuum packaging methods ...... 9 2.1 Background ...... 9 2.1.1 Introduction to vacuum packaging ...... 9 2.1.2 Challenges in wafer-level vacuum packaging ...... 11 2.2 Vacuum sealing by narrow copper sealing rings ...... 11 2.2.1 Concept and process ...... 12 2.2.2 Sealing yield evaluation ...... 13 2.2.3 Bond interface inspection ...... 14 2.2.4 Hermeticity evaluation ...... 15 2.2.5 Bond strength evaluation ...... 17 2.3 Vacuum sealing by ultra-thin caps with narrow Al-Au seals ...... 17 2.3.1 Concept and process ...... 18 2.3.2 Sealing yield evaluation ...... 19 2.3.3 Bond interface inspection ...... 21 2.3.4 Hermeticity evaluation ...... 22 2.3.5 Bond strength evaluation ...... 22 2.3.6 Temperature stress testing ...... 23 3 Large-area integration of 2D materials ...... 25 3.1 Background ...... 25 vi

3.1.1 Introduction to integration of 2D materials ...... 25 3.1.2 Challenges in integration of 2D materials ...... 26 3.2 Method ...... 26 3.3 Evaluation ...... 28 3.3.1 Transfer of monolayer graphene ...... 28 3.3.2 Formation of suspended graphene ...... 29 3.3.3 Formation of graphene/h-BN heterostructure ...... 30 3.3.4 Transfer of MoS2 ...... 31 4 Vertical integration of microchips ...... 33 4.1 Background ...... 33 4.1.1 Introduction to 3D microchip assembly ...... 33 4.1.2 Challenges in 3D microchip assembly ...... 34 4.2 Method and experiments ...... 34 4.2.1 Concept and microchip design ...... 34 4.2.2 Magnetic assembly ...... 36 4.2.3 Edge wire bonding ...... 37 4.3 Evaluation ...... 37 4.3.1 Assembly efficiency analysis ...... 37 4.3.2 Contact resistance of the wire bonds ...... 40 4.3.3 Bond strength evaluation ...... 41 4.3.4 Application demonstrator ...... 42 5 Transfer of carbon nanotubes and silicon microstructures ...... 43 5.1 Background ...... 43 5.1.1 Introduction to heterogeneous integration of nanomaterials and microstructures ...... 43 5.1.2 Challenges in transfer printing ...... 44 5.2 Concept and experiments ...... 44 5.2.1 General principle ...... 44 5.2.2 Transfer printing of CNTs ...... 45 5.2.3 Transfer printing of Au FABs with CNTs ...... 46 5.2.4 Transfer printing of Si microstructures ...... 47 5.3 Evaluation ...... 48 5.3.1 Transfer printing of CNTs ...... 48 5.3.2 Transfer printing of Au FABs with CNTs ...... 49 5.3.3 Transfer printing of Si microstructures ...... 51 6 Summary and outlook ...... 53 6.1 Achievements ...... 53 6.2 Impact and prospects ...... 56 Acknowledgement ...... 57 Bibliography ...... 61 Paper Reprints ...... 71

vii

List of Publications

This thesis is based on the following papers in peer-reviewed international journal:

I. "Wafer-level vacuum packaging enabled by plastic deformation and low- temperature welding of copper sealing rings with a small footprint," X. Wang, S. J. Bleiker, M. Antelius, G. Stemme, and F. Niklaus, Journal of Micro- electromechanical Systems, vol. 26, no. 2, pp. 357-365, 2017.

II. "Wafer-level vacuum sealing by transfer bonding of silicon caps for small footprint and ultra-thin MEMS packages," X. Wang, S. J. Bleiker, P. Edinger, C. Errando-Herranz, N. Roxhed, G. Stemme, K. B. Gylfason, and F. Niklaus, Journal of Microelectromechanical Systems, vol. 28, no. 3, pp. 460-471, 2019.

III. "Large-area integration of two-dimensional materials and their heterostructures using wafer bonding," A. Quellmalz, X. Wang, S. Wagner, S. Sawallich, M. Prechtl, O. Hartwig, S. Luo, G. S. Duesberg, M. Lemme, K. B. Gylfason, N. Roxhed, G. Stemme, and F. Niklaus, manuscript, 2019.

IV. "Vertical integration of microchips by magnetic assembly and edge wire bonding," F. Ribet* & X. Wang*, M. Laakso, S. Pagliano, F. Niklaus, N. Roxhed, and G. Stemme, Microsystems and Nanoengineering, under review, 2019. *The authors contributed equally to the work.

V. "Transfer printing of nanomaterials and microstructures using a wire bonder," X. Wang, S. Schröder, A. Enrico, F. Niklaus, G. Stemme, and N. Roxhed, Journal of Micromechanics and Microengineering, under review, 2019.

viii

The contribution of Xiaojing Wang to each publication, major (•••), partial (••), or minor (•):

Design Fabrication Experiments Analysis Writing I. •• ••• ••• ••• ••• II. ••• ••• ••• ••• ••• III. •• •• •• •• •• IV. •• ••• •• •• ••• V. ••• ••• ••• ••• •••

This work has also been presented at the following reviewed international conferences:

6. “Narrow footprint copper sealing rings for low-temperature hermetic wafer- level packaging,” X. Wang, S. J. Bleiker, M. Antelius, G. Stemme, and F. Niklaus, in Proceedings of 19th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), pp. 423–426, Jun. 2017.

7. “Wafer-scale transfer of graphene by adhesive wafer bonding,” A. Quellmalz, X. Wang, S. Wagner, M. Lemme, K. B. Gylfason, N. Roxhed, G. Stemme, and F. Niklaus, in Proceedings of IEEE 32th International Conference on Micro Electro Mechanical Systems (MEMS), pp. 257–259, Jan. 2019.

Other reviewed international conference papers by the author, not included in this thesis:

8. “High aspect ratio silicon field emitter arrays (FEAS) as miniaturized stable electron source for catheter-based radiotherapy,” X. Wang, G. Stemme, and N. Roxhed, in Proceedings of IEEE 30th International Conference on Micro Electro Mechanical Systems (MEMS), pp. 522–525, Jan. 2017.

9. “Silicon photonic MEMS: exploiting mechanics at the nanoscale to enhance photonic integrated circuits,” N. Quack, H. Sattari, A. Y. Takabayashi, Y. Zhang, P. Edinger, C. Errando-Herranz, K. B. Gylfason, X. Wang, F. Niklaus, M. A. Jezzini, H. Y. Hwang, P. O'brien, M. A. G. Porcel, C. L. Arce, S. Kumar, B. Abasahl, P. Verheyen, and W. Bogaerts, in Optical Fiber Communication Conference (OFC) 2019, p. M2D.3, Mar. 2019.

Abbreviations

2D Two-Dimensional 3D Three-Dimensional BCB Benzocyclobutene BOX Buried Oxide (on SOI wafer) CMOS Complementary Metal-Oxide-Semiconductor CNT Carbon Nanotube CTE Coefficient of Thermal Expansion CVD Chemical Vapor Deposition DRIE Deep Reactive Ion Etching (Bosch Process) EDS Electron-Dispersive X-ray Spectroscopy EFO Electronic Flame Off FAB Free Air Ball FIB Focused Ion Beam FWHM Full Width at Half Maximum IMC Intermediate Metal Compound IC Integrated Circuit IOT Internet of Things IPA Isopropanol IR Infrared LED Light-Emitting Diodes MEMS Micro-Electromechanical Systems MHDA 16-Mercaptohexadecanoic Acid NEMS Nano-Electromechanical Systems MtM More-than-Moore (Paradigm) PECVD Pressure-Enhanced Chemical Vapor Deposition PDMS Polydimethylsiloxane RF Radio-Frequency RGA Residual Gas Analysis RIE Reactive Ion Etching SAB Surface Activated Bonding SAM Self-Assembly Monolayer SEM Scanning Electron Microscope SiP System in Package SWCNT Single-Walled Carbon Nanotube SLID Solid-Liquid Inter-diffusion SoC System-on-Chip x

SOI Silicon on Insulator THz-TDS Terahertz Transmission Time-Domain Spectroscopy TC Thermal Compression TSV Through Silicon Via TGV Through Glass Via

Chapter 1

Introduction

This chapter describes the background of heterogeneous integration, the typical applications, the importance to the future of micro- and nanosystems, and the challenges to be addressed. Then, wafer bonding and wire bonding are introduced as promising technologies that enable potential solutions to address the challenges in heterogeneous integration. Finally, the objectives and the structure of this thesis are presented.

1.1 Micro- and nanosystems as foundations for a smarter planet Micro- and nanosystems conventionally refer to micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS), which are transducer systems with movable or suspended parts having their smallest features in micrometer and nanometer range, respectively. MEMS products, such as digital micromirror devices used in projectors and accelerometers in mobile phones, have long been supportive hardware units for modern technologies and bring more convenient lives to people. The evolution of MEMS and NEMS has also paved their way for applications in chemical sensing, medical diagnosis, and optical communication, serving people’s lives in different aspects. In one word, the advancement of micro- and nanosystems technologies has enabled various emerging industries, including smartphones, intelligent automobiles, point-of-care testing, Internet of things (IOT), and cloud of data, etc., which are foundations for building a smarter planet.

1.2 Heterogeneous integration enabling future micro- and nanosystems Heterogeneous integration, according to the International Technology Roadmap for Semiconductor (ITRS), refers to the integration of separately manufactured components into a higher-level assembly that, in the aggregate, provides enhanced functionality and improved operating characteristics [1]. It is considered as a key technology to meet future challenges on realizing further miniaturized, cost- efficient, and multi-functional devices demanded by the abovementioned industries, such as smartphones, intelligent automobiles, and IOT, etc. [1]. For instance, high-performance electronics and emerging NEMS devices require the use of materials, such as III-V compounds, carbon nanotubes (CNTs), and nano-

1 2 CHAPTER 1 INTRODUCTION wires, that are not typically compatible with standard MEMS process. In addition, combing integrated circuits (ICs) (for electrical interfacing) with MEMS and NEMS is also essential for realizing miniaturized devices and enhanced performance [2]. Heterogeneous integration is proposed to address these challenges by assembling and packaging microstructures and nanomaterials that are fabricated individually using specialized processes on the same substrate. Two major types of applications that are enabled by heterogeneous technologies are integration of MEMS with ICs and integrated microsystems based on nanomaterials and flexible substrates. The former typically deals with integration technologies, e.g. wafer bonding, to combine MEMS or NEMS components with ICs on the same silicon (Si) substrate, which enables further miniaturization and function diversification of end-user devices, e.g. smartphones. The latter forms electronics or transducer microsystems on flexible substrates, typically made of various polymers, and uses heterogeneously integrated nanomaterials as the functional layer to serve for emerging applications, such as bendable and wearable electronics for health monitoring.

1.2.1 Integration of MEMS and ICs Integration of MEMS with ICs is the key technical roadmap to realize scaling of the functionalities provided by a device in More-than-More (MtM) paradigm [3]. Since the spatial down-scaling (Moore’s Law and More Moore) of complementary metal-oxide-semiconductor (CMOS) ICs on Si substrates is approaching to its physical limit, MtM paradigm becomes an important strategy for increasing the density of functionalities incorporated into a device, as shown in Fig. 1.1.

Heterogeneous integration ...

14nm

7nm

Figure 1.1. More-than-More paradigm. Adapted from [3].

1.2 HETEROGENEOUS INTEGRATION ENABLING FUTURE MICRO- 3 AND NANO-SYSTEMS

There are various approaches to integrate MEMS with ICs. The dominant method is called hybrid integration, i.e. MEMS chips and IC chips diced from separately manufactured wafers are placed together in a shared package, typically a printed circuit board (PCB), to form a fully functional unit. More specifically, if the MEMS chips and IC chips are placed side by side, and connected by either wire bonding or flip-chip bonding, such hybrid integration scheme is called 2D system- in-package (SiP); if the MEMS chips and IC chips are placed on top of each other, such hybrid integration scheme is called 3D SiP, as depicted in Fig. 1.2. Compared to 2D SiP solution, 3D SiP solution is more space-efficient. However, to achieve even higher integration density, system-on-chip (SoC) integration scheme has to be implemented.

Figure 1.2. Different schemes of integrating MEMS with ICs. (a) 2D system-in-package (SiP) integration. (b) 3D SiP integration. (c) System-on-chip (SoC) integration by monolithic approach. (d) SoC integration by heterogeneous approach.

SoC integration puts MEMS and IC components in a single chip, therefore, it provides the highest possible packing density. SoC integration can be further categorized into monolithic integration [4]–[7], and heterogeneous integration [2], [7]–[10]. The monolithic approach realizes the integration by directly fabricating MEMS components on IC substrates, while in heterogeneous integration, the MEMS and IC components are partially or fully fabricated on different substrates and finally joined together on the same substrate, as shown in Fig. 1.2c, d. The advantage of the monolithic approach is that it potentially offers the lowest footprint of the final integrated device. However, the requirement on process compatibility limits the choices of materials and processing for the MEMS fabrication. In contrast, heterogeneous integration overcomes this problem by allowing separate fabrication of components to be assembled together, thus being more flexible and promising for integration of NEMS and other exotic microstructures and nanomaterials with ICs. A typical example is the encapsulation lids for hermetic packaging of the MEMS devices. The caps are prepared on a separate substrate and bonded to the device substrate, without affecting the production of the MEMS devices themselves. 4 1.3 CHALLENGES IN HETEROGENEOUS INTEGRATION

1.2.2 Integrated microsystems based on nanomaterials and flexible substrates Apart from MEMS and IC industries, heterogeneous integration technologies also enable other emerging applications, such as portable bio-sensing devices and flexible electronics [11]–[13]. These devices are typically built on fabric or paper- based or polymeric substrates, with functional materials heterogeneously integrated by methods such as screen printing and transfer printing.

CNTs GaN GaAs Si PDMS stamp

Nanotubes, wires and ribbons

Device substrate (PI)

Source wafer Repeat printing

Figure 1.3. Heterogeneously integrated transistors on flexible polymeric substrates by transfer printing. Adapted from [11].

One of the most successful heterogeneous integration methods on flexible substrates is transfer printing. It was firstly demonstrated by J. A. Roger’s group to fabricated transistors on flexible polyimide (PI) substrates using transfer printed “inks”, i.e. Si nanoribbons, III-V nanowires, and CNTs [11], as shown in Fig. 1.3. Transfer printing typically employs a stamp made of polydimethylsiloxane (PDMS) to transfer the nanomaterials from their different growth substrates to a target host substrate. The control over the adhesion force of the nanomaterials with respect to stamp, the growth substrate, and the host substrate determines whether the correct operation of pick-up or placement is achieved. After transfer, another polymer is usually spin coated on the transferred nanomaterials to both provide electrical insulation and enable further stacking of additional layers. Interconnects between the layers can be formed by metal deposition in combination with photolithography and dry/wet etching.

1.3 Challenges in heterogeneous integration Despite the success of existing heterogeneous integration technologies in various applications, there are niches where these technologies resign supreme. On the one hand, a higher integration density of different functional components requires that the integration process to be versatile and conducted at low temperatures to enable wider choices of materials, and the footprints of individual components to be reduced so that the final device is further miniaturized. On the other hand, low- cost and scalable integration technologies based on established infrastructure are 1.4 WAFER BONDING AND WIRE BONDING 5

demanded for high-volume production, so that the transition from research demonstration towards commercial production can be facilitated. These two types of challenges need to be addressed for the future development of heterogeneous technologies. A typical example related to the first type of challenge is the large footprint consumption of the packages in integrated devices, especially the caps for hermetic sealing of various MEMS devices, such as accelerometers, gyroscopes, and infrared (IR) radiation detectors. Bulky caps and wide hermetic sealing structures consume large footprints of the final packaged devices, thus hindering the miniaturization of the devices and increasing the overall production cost. Regarding the second type of challenge, the practical application of transfer printing is facing obstacles, since typically manual or custom-built tools for reliable alignment and stamping operations are needed, thus standardized infrastructure has to be established to facilitate its industrial application. Therefore, it is beneficial to utilize well-established and standard tools as generic platforms to realize versatile, scalable, and low-cost heterogeneous integration of emerging micro/nano-materials and components. Such platforms could enable promising solutions for the abovementioned challenges in heterogeneous integration. Wafer bonding and wire bonding are extremely mature and high-throughput processes in industry, and thus, they are potential ideal platforms to fulfill this mission. Although wafer bonding has long been used as joining technology for wafer-level heterogeneous integration, further investigation of its use in demanding applications and for emerging materials needs to be conducted. Wire bonding is commonly used as an electrical packaging process. However, it has also been investigated for unconventional applications [14], [15]. Further exploration of wire bonding in heterogeneous integration may enable new solutions for current problems.

1.4 Wafer bonding and wire bonding 1.4.1 Introduction to wafer bonding Wafer bonding is a process of joining wafers to form a bonded wafer stack. It is one of the most standard tools used in IC and MEMS industry, for the sake of integrating materials on wafer-scale. Typical applications include formation of electrical interconnections between multiple wafers to be stacked and encapsulation of MEMS and/or IC devices for high volume production. The tool used for such a process, i.e. wafer bonder, mainly consists of a fixture for wafer handling, a pair of chucks for applying forces, heat, or voltages to the wafer stack from the top/bottom, and a chamber for atmosphere control, e.g. vacuum or specific gas atmospheres, during the bonding process. The schematic of the key components of the wafer bonder and an image of an actual wafer bonder (Suss CB8, Suss Tech. Corp., Germany) used in our cleanroom are shown in Fig. 1.4. Depending on the bonding mechanism, wafer bonding can be categorized into direct bonding, anodic bonding, and intermediate layer bonding [16]. Direct bonding employs either very high temperature or smooth and flat surfaces to assist direct joining of wafers. Anodic bonding applies voltage and heat to the wafer pair 6 1.4 WAFER BONDING AND WIRE BONDING to achieve bonding between glass wafers and conductive wafers, with silicon to glass bonding as the most common application. These two types of bonding approaches are demanding in the choices of substrate materials and surface roughness, while intermediate layer bonding serves as a more versatile method. Intermediate layer bonding leverages on intermediate bonding materials that are different from the wafer materials, to realize joining of the wafers. Polymers, glasses, and metals have all been investigated for this approach. Exploring new materials and interface structures in wafer bonding process can potentially lead to new solutions for challenges in heterogeneous integration.

Figure 1.4. (a) Schematic of the key components of a wafer bonder and (b) an image of the wafer bonder used in the thesis work.

1.4.2 Introduction to wire bonding Wire bonding is an extremely mature back-end technology for realizing die-to- substrate wire interconnections. After decades of development, today’s wire bonding tools can easily achieve high-throughput of about 20 bond wires per second, high placement accuracy of less than 3 µm, and lost cost of ~2 USD per 1000 bond wires [15], [17]. The dominant process used for wire bonding is ball stitch wire bonding (> 90% in current bond wires), as shown in Fig. 1.5. A standard ball stitch wire bonding cycle starts with the formation of a free air ball (FAB) by an electronic flame off (EFO). Next, the ball bond is performed on the bond pad on the fabricated MEMS or IC die, followed by a stitch bond performed on the bond pad on the hosting substrate. Thus, a wire connection is built between the die and the substrate. Afterwards, the wire is ripped off from the stitch bond and ready for the next wire bonding cycle. During the wire bonding process, ultrasonic vibration is typically applied to the bond interfaces to help reduce the required bonding temperature and force. Gold (Au) wire is so far the most reliable and frequently used bond wire in industry. In the meantime, copper (Cu) wire is gradually increasing the market share due to lower material cost. The commonly used bond pad materials are aluminum (Al), Au, and Cu, although other metals have been also investigated for wire bonding. As a high-throughput, high-precision, and low-cost tool, wire bonder 1.5 OBJECTIVES OF THIS THESIS 7

can be further investigated for realizing scalable and cost-efficient heterogeneous integration.

Figure 1.5. Schematic drawing of a conventional ball stitch wire bonding cycle. Reprinted from [15]. (a) Formation of free air ball (FAB) by an electronic flame off (EFO). (b) Centering of the FAB under the wire bonder capillary and aligning FAB to the bond pad of the die. (c) Ball bond performed on the bond pad using thermo-sonic bonding. (d) Shaping the bond wire using the defined trajectory. (e) Completing the defined wire loop profile by moving the wire bonder capillary accordingly towards the bond pad on the substrate. (f) Stitch bond using thermo-sonic bonding. (g) Defining the tail length of the wire for the next FAB generation. (h) Ripping off the wire at the defined tail height.

1.5 Objectives of this thesis This thesis aims to utilize mature wafer bonding and wire bonding infrastructure to enable new solutions for challenges in heterogeneous integration that are exceeding the limits of the state-of-the-art technologies. Specifically, the objectives are:

• develop wafer bonding-based vacuum packaging approaches that feature low process temperature (< 300 °C), narrow sealing footprints (< 10 µm), and ultra- thin caps (< 30 µm) for realizing ultra-compact SoC integration of encapsulated MEMS with ICs; • present a wafer-scale method for integrating large-area 2D materials, including graphene, h-BN, MoS2, and graphene/h-BN heterostructures on standard Si wafers, to enable scalable solutions for fabricating heterogeneously integrated 2D electronic devices; • exploit wire bonding for realizing vertical integration of heterogeneously assembled microchips for potential 3D sensing applications; 8 1.6 STRUCTURE OF THIS THESIS

• demonstrate the use of a standard wire bonder as an automated “pick-and-place” tool for versatile and high-throughput integration of nanomaterials and microstructures.

1.6 Structure of this thesis This thesis consists of six chapters, with each chapter (Chapter 1 – 5) addressing one aspect of the challenges in heterogeneous integration. Chapter 1 gives an overview of the heterogeneous integration technologies and applications, introduces existing and emerging challenges to be addressed in heterogeneous integration, and presents the motivation, objectives, and structure of this thesis. Chapter 2 presents and examines two wafer-scale vacuum packaging approaches using metal-based wafer bonding (Paper I and Paper II). Firstly, the challenge for accomplishing low-temperature, low-profile, small footprint, and mechanically stable vacuum packaging is introduced. Second, a vacuum packaging approach using narrow Cu sealing rings is presented and characterized for wafer- scale yield, hermeticity, and mechanical robustness. Third, another vacuum sealing approach using narrow Au-Al seals and ultra-thin Si caps is presented and characterized for yield, hermeticity, bond strength, and temperature reliability. Chapter 3 presents and characterizes a method for large-area integration of 2D materials using adhesive wafer bonding (Paper III). First, the challenge in scalable integration of 2D material for making nanoelectronics and photonics is introduced. Then, the method of using BCB adhesive wafer bonding for the integration of graphene, h-BN, MoS2, and formation of graphene/h-BN heterostructures is presented. The yield and quality of the transferred 2D materials and heterostructures are evaluated by various means. Chapter 4 proposes and evaluates a method for realizing vertical assembly of microchips and subsequent electrical contacting enabled by magnetic assembly and wire bonding (Paper IV). The need for scalable solutions for heterogeneous vertical integration of microchips is introduced and the proposed innovative method is presented. The efficiency and scalability of the microchip assembly, and the contact resistance and strength of the wire bonds formed on the sidewalls of the vertically standing microchips are assessed. Chapter 5 describes a new method for integrating CNTs and Si microstructures from the fabrication substrate to a new host substrate using a wire bonder (Paper V). First, different methods on integrating nanomaterials and microstructures are compared and the proposed method of using a standard wire bonder as a high- throughput, cost-efficient, and versatile “pick-and-place” tool for material transfer is introduced. Then, the method is evaluated on the transfer of CNTs from a source substrate to different flexible substrates, and to a Si host substrate as field emission sources, respectively. In addition, the method is also demonstrated on the transfer of stiff Si microstructures. Chapter 6 summarizes the achievements of the thesis work, and discusses the potential application, impact, limitations, and prospects of the presented heterogeneous integration technologies.

Chapter 2

Wafer-level vacuum packaging methods

This chapter introduces the background of vacuum packaging and the encountered challenges for its use in increasingly demanding MEMS and NEMS applications. Then, two wafer-level vacuum sealing technologies are presented and examined to meet these challenges. The first approach features narrow Cu sealing rings (down to 8 µm in width), high bond strength, and excellent long-term hermeticity. The second approach achieves vacuum sealing by narrow Al-Au seals (down to 6 µm in width) and ultra-thin caps (25 µm thick). The achieved CMOS compatibility, low wafer bonding temperature, narrow sealing footprint, and ultra-low cap profile could pave the way for space-efficient capping solutions for SoC integration of MEMS/NEMS and ICs.

2.1 Background 2.1.1 Introduction to vacuum packaging Vacuum packaging is a critical step for ensuring the reliable operation of various MEMS devices[8], [18], [19], as shown in Table 2.1. Accelerometers, gyroscopes, IR detectors are typical examples where vacuum sealing has to be incorporated to fulfill their designed functionalities. In order to reduce the overall cost in high volume production, industrial MEMS fabrication realizes the vacuum packaging of the MEMS devices on wafer-scale.

Table 2.1. Vacuum requirements of different MEMS devices. Adapted from [19].

Required working pressure MEMS device type (mbar) Accelerometer ≈ 300 – 700 Absolute pressure sensor ≈ 1 – 10 Resonator 10–4 – 10–1 Gyroscope 10–4 – 10–1 RF switch 10–4 – 10–1 Microbolometer ≤ 10–4 Optical MEMS Moisture free Digital micro-mirror and Moisture free light processing MEMS

9 10 CHAPTER 2 WAFER-LEVEL VACUUM PACKAGING METHODS

Wafer-level vacuum packaging technologies are generally categorized into two types: thin film deposition and wafer bonding of caps. Thin film deposition typically uses a sacrificial layer to cover the structures to be sealed, followed by a cap film deposition. The sacrificial layer is subsequently removed by etching through access holes or by thermal decomposition. Finally, a sealing film is conformally deposited over the cap film to seal the access holes [19]–[28]. The total thickness of the capping film stack is usually only a few micrometers, which offers very low profile as well as small footprint seal in the lateral dimension. However, there are several drawbacks associated with this approach [29]. First, the packaging process is complex, especially if MEMS or NEMS movable structures must also be released, since in this case multiple sacrificial layers have to be incorporated. Second, this approach suffers from a lack of flexibility and universality. The sacrificial and sealing films made of silicon oxide, silicon nitride, or poly-silicon typically involve high deposition temperatures, which may hinder its use for many applications, e.g. sealing of MEMS on ICs. In contrast, hermetic sealing of devices by bonding caps on top of the devices is a more versatile approach. Since the preparation of the caps is separated from the preparation of the devices to be sealed, this approach overcomes the abovementioned drawbacks of sealing by thin film deposition.

Figure 2.1. Gas permeabilities of different sealing materials as a function of the material thickness. Adapted from [33].

Wafer bonding technologies for realizing hermetic packaging can be divided into direct bonding, anodic bonding, and intermediate layer bonding. As introduced in Chapter 1, direct bonding techniques either rely on high bonding temperatures [30], making them unsuitable for CMOS substrates, or require ultra-fine surface roughness and cleanness of the substrates [31]. For intermediate layer bonding, polymers, glasses, and metals are used. However, polymers are typically not fully hermetic due to their high permeability to gases and moisture [31]–[33], as shown in Fig. 2.1. Glass-based methods, including glass frit bonding and anodic bonding, typically consume comparably large areas for the sealing rings since the sealing structures have to be at least several hundreds of micrometers wide to ensure high

2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS 11

bond strength and sufficient hermeticity [33]–[36]. As alternatives, metals have drawn extensive attention as intermediate bonding layers because they provide excellent hermeticity and mechanical strength, while enabling size reduction in the sealing ring area by nearly a hundredfold [33], as indicated in Fig. 2.1, thus facilitating significant reduction in die size. Various metal-based wafer-level hermetic packaging methods have been investigated, including solder bonding [37]–[40], eutectic bonding [41]–[44], solid- liquid inter-diffusion (SLID) bonding [39], [45], [46], surface activated bonding (SAB) [47], [48], and thermo-compression bonding [49]–[54]. All these technologies have their own advantages and disadvantages. The typical drawbacks of the abovementioned methods are: reflow of solders/alloys used in solder bonding and eutectic bonding [39], [40], [44], voids present in the intermetallic compound layer formed in SLID bonding [45], [46], [55], strict requirements on surface planarity /roughness of the substrates in surface activated bonding [47], [56], and high employed temperatures (300 – 450 °C) and bonding pressures in thermocompression bonding [49]–[54], [57]. However, low bonding temperatures (< 300 °C) during vacuum packaging are desired to avoid thermally induced damages of MEMS devices and CMOS circuits. For such a propose, investigations have been made on achieving low-temperature wafer-scale sealing using intermediate bonding metals, including Al [58], indium (In) [59], Au [60]–[65], and Cu [66]–[68]. Although low-temperature sealing is realized in these work, problems remain in other aspects, such as complex processes [58], [64], specific bonding surface preparation [61], [65]–[67], incorporation of additional bond enhancement materials [62], [63], and use of wide sealing rings ranging from 60 – 200 µm [59], [60], [65].

2.1.2 Challenges in wafer-level vacuum packaging As vacuum packaging becomes increasingly important for MEMS, NEMS, vacuum electronics, and emerging quantum devices, more requirements need to be fulfilled by wafer-level vacuum packaging technologies. The cost reduction and device miniaturization require that the sealing footprints and the cap thickness are minimized. The process compatibility with CMOS and other temperature-sensitive substrate demands the packaging process to be a low-temperature and low- complexity process. In the meantime, to ensure the reliability of the sealed devices, the hermetic seals have to be mechanically robust and hermetically stable. How to accomplish these requirements all together becomes a big challenge. Although metals are the promising materials for achieving such a goal, the existing wafer- scale vacuum packaging approaches cannot fully resolve this challenge.

2.2 Vacuum sealing by narrow copper sealing rings This thesis proposes a low-temperature wafer-level vacuum sealing approach using narrow Cu sealing rings to push the limit of the sealing footprint to be below 10 µm, without incorporation of additional bond enhancement materials such as polymeric underfill or solder patches [69]. Compared to other abovementioned 12 2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS metallic bonding materials, Cu is increasingly used as the interconnect material in the state-of-the-art CMOS circuits and in 3D IC integration [70], due to high electrical conductivity, low electron migration, and excellent mechanical strength. Therefore, it is a preferred bonding and sealing material for vacuum packaging of next-generation integrated microsystems. Cu has been investigated for low- temperature hermetic sealing [66]–[68]. However, these methods either require very flat and clean Cu surfaces, additional capping layer, and large total bonding area [66], [67], or are not compatible with wafer-level processing [68].

2.2.1 Concept and process The designed sealing structure based on low-temperature welding of Cu is illustrated in Fig. 2.2. Electroplated Cu rings prepared on the device wafer are pressed against the matching grooves (covered by 300 nm-thick Cu) in the cap wafer, at a low temperature of 250 °C. Due to the small contact area between the wafers, high localized pressures are present at the bond interfaces, thus inducing plastic deformation of the Cu rings and facilitating the subsequent solid-state Cu- Cu diffusion bonding procedures. As a result, hermetic sealing is formed and the required bonding temperature is reduced to 250 °C, compared to conventional Cu- Cu thermo-compression bonding of 300 – 450 °C [71]. Three different type sealing interfaces are included on the same wafer to evaluate their influence on the resulting sealing yield and hermeticity.

Cap wafer (Transparent for illustration)

Cavity to be sealed Device wafer Groove (Covered by thin Cu layer) Overlap width Cu ring

Design with three grooves Design with two grooves

Figure 2.2. Schematic of the sealing structures using narrow Cu rings (adapted from Paper I). Three different designs feature different numbers of grooves.

The wafer bonding process flow is illustrated in Fig. 2.3. After the alignment of the two wafers, the bonding was performed in a wafer bonder (Suss BA8). The bonding pressure force and time were 20 kN and 25 min, respectively. The bonder 2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS 13

chamber was pumped to a vacuum of 7 × 10–5 mbar during the bonding and sealing. The calculated localized pressure at the start of the bonding is 550 MPa, which is 2.4 times the reported yield strength of electroplated Cu [72], ensuing the plastic deformation of the Cu sealing rings. After bonding, the cap wafer was thinned down by Si reactive ion etching (RIE) to assist visualize the sealing yield.

Si SiO2 Cu Ti/Cu

Cap wafer Annular groove

Cu ring

Device wafer

(a) Bonding force (20 kN for 25 min) High localized pressure (b)

Vacuum cavity

Temperature: 250 °C Vacuum chamber (b) Deflected diaphragm due Cap wafer thinning to differential pressure Atmosphere

Vacuum cavity

(c)

Figure 2.3. Process flow of the wafer bonding process using narrow Cu sealing rings (adapted from Paper 6). (a) Preparation and alignment of the cap wafer and device wafer. (b) Wafer bonding in a vacuum chamber at 250 °C. (c) Cap wafer thinning to help visualize the sealing yield.

2.2.2 Sealing yield evaluation The wafer-scale sealing yield distribution after bonding and cap thinning is exhibited in Fig. 2.4. As seen in Fig. 2.4a, 92 cavities out of 124 cavities were successfully sealed, and only one cavity leaked during the following three months of storage in atmospheric pressure. Many leaked cavities were located at the edges of the wafers, since most of these cavities used the narrowest 6 µm-wide Cu sealing rings. Such designs feature only 1 µm overlap width at the edges of the Cu rings (Fig. 2.2), and thus are prone to leak since any wafer-to-wafer misalignment of over 1 µm would damage the seals. Another region where many leaked cavities 14 2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS aggregate was in the bottom-left part of the wafer. This was probably attributed to irregularities in the thickness of the Cu rings from the electroplating process or surface contamination from other sources. In terms of the influence of the Cu ring width on the sealing yield, no significant dependency was found, except for the 6 µm-wide Cu rings, as shown in Fig. 2.4b. The design with 13.5 µm-wide Cu rings even achieves a sealing yield of 100% after three months of storage.

Figure 2.4. Sealing yield distribution as a function of location on the wafer and width of the Cu sealing ring (adapted from Paper 6). (a) Wafer-scale sealing yield distribution after bonding and after three months of storage in atmospheric pressure. (b) Sealing yield as a function of the Cu sealing ring width after three months of storage in atmospheric pressure.

2.2.3 Bond interface inspection

(a) (b) (c)

Figure 2.5. Cross-sectional SEM images of three bond interfaces (adapted from Paper I). (a) 1-groove bond interface. (b) 2-groove bond interface. (c) 3-groove bond interface.

The bonded Cu-Cu interfaces were inspected by scanning electron microscopy (SEM), as shown in Fig. 2.5. Three representative cavities featuring different 2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS 15

numbers of grooves were diced along the middle axis of the samples and polished. It is clear that all the three designs exhibit large-scale plastic deformation of the Cu rings. They show a uniform, welded Cu layer where parts of the Cu rings have been pressed into the grooves as intended.

2.2.4 Hermeticity evaluation The long-term hermeticity of the narrow Cu seals was investigated by monitoring the cap deflection of the sealed cavities. White-light interferometry (Wyko NT9300, Veeco Inc., US) was used to record the cap deflection over a period of 97 days. The resulting cap deflection variations are shown in Fig. 2.6. The measured cap deflections range from 4.15 µm to 8.80 µm due to non-uniform thickness of the caps resulted from non-uniform cap wafer thinning process by Si RIE.

Cap deflection (µm)

Time (days) Figure 2.6. Measured cap deflections by white-light interferometry over a duration of 97 days (reprinted from Paper I). 24 cavities from different locations of the wafer are randomly chosen for the evaluation. The data have been compensated for varying ambient pressure.

Since square cap diaphragms were used in our experiments, the diaphragm in the center of the cap is proportional to the pressure difference of the inside sealed vacuum and outside atmosphere [73]. Therefore, the leak rate � can be expressed using the following formula: � = ln (2.1) where � and � are the cap deflections at the time point � and �, respectively. � stands for the volume of the sealed cavity and � represents the ambient reference pressure. Since both positive and negative changes of the cap deflections are present in the recorded data and they are on the same level as the noise of the measurement setup, such a calculation actually reflects the detection limit of this measurement. A leak rate of 1.3 × 10–12 mbarL/s can be calculated conservatively 16 2.2 VACUUM SEALING BY NARROW COPPER SEALING RINGS using (1) with the largest measured deflection deviation. The true leak rate of the sealed cavities should be lower than this value, which is already much better than reported values of 10–10 – 10–8 mbarL/s using helium fine leak test by Cu-Cu thermo-compression bonding [66], Ni/Sn solder bonding [38], and Au-Sn eutectic bonding [43]. To obtain the absolute pressures inside the sealed cavities, residual gas analysis (RGA) was conducted on three representative samples featuring different numbers of grooves. The results are summarized in Table 2.2. The achieved vacuum levels of the tested three samples were on the order of 10–2 mbar 146 days after bonding, which is well below achieved sealed vacuum ranging from 0.3 mbar to 10 mbar using other vacuum packaging methods including thin SiN film deposition by PECVD [19], glass frit bonding [34], and solid-liquid inter-diffusion bonding [39]. No traces of N2 and O2 were found in the sealed vacuum, indicating excellent hermeticity of the Cu seals. The sources for the present H2, CO2, and CO could result from reactions between the trapped wafer vapor and the metal sealing structures during heating [74], and the light hydrocarbons could stem from organic impurities remained in electroplated Cu [75]. Ar could be desorbed from implanted Ar into the Cu on the cap wafer during the sputtering process [76].

Table 2.2. Residual gas analysis results of three evaluated cavities (reprinted from Paper I).

Pressure (2 grooves, Pressure (2 grooves, Pressure (3 grooves, 3 Gas 2 µm overlap) 3 µm overlap) µm overlap) (mbar) % (mbar) % (mbar) %

H2 2.9 × 10–2 63.07 0 0 0 0

CO2 1.1 × 10–2 23.92 0 0 0 0 CO 5.1 × 10–3 11.09 0 0 0 0

CH4 0 0 2.5 × 10–2 97.66 1.7 × 10–2 55.77 HCs* 6.7 × 10–4 1.46 4.5 × 10–4 1.76 7.0 × 10–4 2.30 Ar 2.1 × 10–4 0.46 1.3 × 10–4 0.51 1.2 × 10–2 39.37 He 0 0 1.8 × 10–5 0.07 7.8 × 10–4 2.56

O2 0 0 0 0 0 0

N2 0 0 0 0 0 0

H2O 0 0 0 0 0 0

Total 4.6 × 10–2 100 2.6 × 10–2 100 3.0 × 10–2 100

* HCs represents the contribution of light hydrocarbons (C2H6 and C3H8).

The achieved vacuum level and moisture-free atmosphere can be potentially used for accelerometers, pressure sensors, and optical MEMS devices. However, for demanding applications such as bolometers and gyroscopes, getter materials can be incorporated inside the cavities and activated after sealing to realize much higher vacuum. Assuming absolute vacuum was sealed right after bonding, a worst-case estimation of the leak rate using the achieved vacuum of 2.6 × 10–2 mbar after 146 days derives a value of 3.6 × 10–16 mbarL/s, which is already two orders 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU 17 SEALS of magnitude lower than the reported values by Au-based sealing [63], [64]. This again demonstrates the excellent hermeticity of the achieved Cu seals.

2.2.5 Bond strength evaluation The mechanical strength of the realized bonds was evaluated by shear testing (PC2400, Dage Ltd., UK). All the extracted shear strength of all the twelve tested cavities were above 90 MPa, which his much higher than the reported values of 8 MPa using Ni/Sn solder bonding [38], 28 MPa to 51.7 MPa using Au-Sn eutectic bonding [39], [43], and 25 MPa using Cu-Cu thermo-compression bonding [67]. The excellent bond strength in combination with the narrow Cu sealing rings achieved at a low bonding temperature in the proposed method provides a more space- saving solution for wafer-level vacuum packaging, compared to other metal-based approaches using sealing rings that are typically over 100 µm in width [39], [40], [42], [44], [49], [50], [52], [59], [62], [63], [65].

2.3 Vacuum sealing by ultra-thin caps with narrow Al-Au seals Here, another low-temperature wafer-level vacuum sealing method featuring ultra-thin silicon caps in combination with narrow metal sealing rings is proposed [77]. 25 µm-thin Si caps together with 6 µm-wide sealing rings are achieved by Au- to-Al bonding. Using thin caps for hermetic packaging offers many advantages over thick caps [20], [78], [79]. Thin caps result in low packages and device thicknesses and can enable significant device miniaturization and cost reduction if combined with small sealing footprints. Furthermore, transparent caps made of silicon oxide, silicon nitride, or silicon (for infrared light), are useful for low-loss transmission of light signals and optical interfacing, e.g. in micro-opto-electro-mechanical systems (MOEMS) [78]–[81]. Another important merit of a thin cap is that if the cap height is shorter than the solders and stud bumps used in flip-chip bonding process, direct stacking of encapsulated substrates can be realized without incorporation of through-cap-vias. Thus, extremely high-density 3D heterogeneous SoC integration is enabled. As discussed previously, thin film deposition method offers very thin capping layers. However, the sealing and MEMS release processes are complex and are restricted in the choices of sealing and substrate materials. Wafer bonding of thin caps servers as a more versatile and flexible alternative. Two kinds of wafer bonding-based schemes are typically used: transfer bonding of pre-defined thin caps and post-bonding cap thinning. Post-bonding cap thinning applies grinding on the cap wafer from the backside until the desired cap thickness is realized [82]– [85]. It has been successfully commercialized for packaging of film bulk acoustic resonator (FBAR) filters [82], [83]. However, the achieved cap thicknesses were relatively thick, ranging from 60 – 80 µm, since the grinding process poses challenges in realizing uniform ultra-thin cap thickness (e.g. 5 µm) on wafer-scale without impairing the structural integrity and hermeticity of the seals. Transfer bonding of pre-defined thin caps overcomes such issues since the thin caps are precisely defined on a carrier wafer and bonded to the device wafer. After bonding, 18 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU SEALS the carrier wafer is removed, thus leaving only the pre-defined thin caps on the device wafer [29], [39], [79], [86]–[94]. However, most of the reported methods using polymers as either cap materials [89]–[93], or sealing materials [29], [86], [87], [94], which are not fully hermetic. The other attempts used poly-silicon [88] or nickel (Ni) [39], [79] caps in combination with metal sealing rings for realizing thin cap hermetic packaging, but the seals either leaked after bonding or after 50 days of storage. Therefore, reliable hermetic sealing achieved by ultra-thin caps (< 30 µm) in combination with narrow sealing footprints (< 10 µm) remains an unsolved challenge.

2.3.1 Concept and process

Si sealing rings covered by Au BOX layer

Cap wafer (SOI) Handle layer

Al sealing rings Device layer Cavity to be sealed

Cavity wafer

Handle and BOX layers removal

Transferred thin Si cap

Sealed cavity

Cavity wafer

Figure 2.7. Schematic drawing of the hermetic packaging method by transfer bonding thin Si caps.

The proposed method by transfer bonding of thin Si caps is illustrated in Fig. 2.7 (adapted from [77]). The thin caps are prepared on the device layer (30 µm thick) of a silicon-on-insulator (SOI) cap wafer. 5 µm-high Si sealing rings are patterned along the edges of the designed cap perimeters, thus defining the cap thickness to be 25 µm. The benefits of using the Si device layer to fabricate the thin caps are that: first, the monocrystalline Si caps offer both excellent mechanical strength and hermeticity, especially when the thin caps deflect due to pressure difference between the sealed vacuum cavities and the ambient atmosphere; second, the used Si caps have good thermal match with commonly used MEMS and CMOS substrates which are also made of Si, thus reducing the risk of thermally induced bond failure; third, the ultra-thin thickness of the caps can be precisely and uniformly defined by choosing the desired device layer thickness of the SOI cap wafer. To achieve sealing with narrow footprints, Au-Al thermo-compression bonding is used. A 1.8 µm-thick Au layer was sputtered on top of the Si sealing rings on the 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU 19 SEALS cap wafer (100 mm diameter) and a 650 nm-thick Al layer was patterned correspondingly on the cavity wafer. The Au-Al bonding and vacuum sealing was realized in a vacuum chamber using a bonding force of 25 kN and a bonding temperature of 250 °C for a duration of 45 min. Narrow Si/Au sealing rings ranging from 3 µm to 27 µm are used for the bonding, aiming to induce high bonding pressure at the Au-Al interface. Thus, plastic deformation of the Al and Au rings would occur and potential surface oxide formed at the Al surface would break, resulting in close and improved contact between the Au and Al layers. Eventually, hermetic Au-Al compound seals are formed. After bonding, the backside of the SOI cap was removed by Si RIE and the remaining BOX layer was removed by SiO2 RIE, leaving only the transferred thin Si caps on the cavity wafer. The benefit of using Al on the cavity wafer is that Al is a standard bond pad material on MEMS dies and on complementary metal-oxide-semiconductor (CMOS) wafers. Thus, the Al sealing rings can be patterned together with the bond pads in the same process, which introduces minimal changes to the standard processing flow for producing the device wafer. Au is chosen to assist the bonding between the Si rings and the Al rings, which has been previously demonstrated for hermetic packaging, although at a higher temperature of 300 °C [95]. Other options such as Al-Al bonding typically employ high temperatures of 400 – 450 °C [52], [53], while Al-Ag bonds suffer from contact corrosion issues [96], therefore they are not considered here.

2.3.2 Sealing yield evaluation

Large Al sealing frame (single cavity) Small Al sealing frame (single cavity) Transferred and sealed large / extra-large / small thin Si caps

Extra-large Al sealing frame (multiple cavities) Detached Si cap with 3 μm- wide Si/Au sealing ring

2 mm 2 mm

(a) (b)

Figure 2.8. Optical image of the cavity wafer before and after the transfer bonding of thin Si caps. (a) Image of a part of the cavity wafer before cap transfer. (b) Image of the same site after cap transfer.

The resulting successfully transferred thin Si caps are shown in Fig. 2.8. Three different cap dimensions were incorporated, with side length from 300 µm to 3 mm. All of the tested caps demonstrate successful transfer, except for 5 out of 432 large Si caps with only 3 µm-wide Si/Au sealing rings. The protrusions of the transferred Si caps out of the cavity wafer plane were within 31±1 µm, which is below typical solder and stud bump heights of ~50 µm after flip-chip bonding [97]. The cap thickness was further reduced by an additional Si DRIE to about 12 µm. Thus, the 20 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU SEALS proposed method is dimensionally compatible with various flip-chip bonding interfaces [98].

(a) (b) 0.15 μm 0.14 μm 0 μm 0 μm

3 mm 1.5 mm

1.5 mm -3.61 μm 3 mm -5.61 μm Figure 2.9. Measured cap deflections by white-light interferometry. (a) A large Si cap (~25 µm thick) with a 15 µm-wide Si/Au sealing ring. (b) An extra-large Si cap (~25 µm thick) with an 18 µm-wide Si/Au sealing ring. The extra-large Si cap landed on the separation walls between the multiple cavities. The zero level refers to the initial top surface of the thin Si caps.

The sealing yield was evaluated by measuring the cap deflections using white- light interferometry (Wyko NT9300, Veeco Inc., US) for a period of two months. The typical measured cap deflections are show in Fig. 2.9. The sealing yield with respect to the width of the Si/Au sealing ring is plotted in Fig. 2.10. It is clear that, even after dicing and after two months of storage in ambient pressure, all the caps with 6 – 27 µm-wide Si/Au sealing rings exhibit sealing yields of 98% or 100%, demonstrating the excellent hermeticity and bond strength of the seals. The low sealing yield of thin caps with 3 µm-wide Si/Au sealing rings is most likely due to insufficient bond strength.

Figure 2.10. Wafer-scale sealing yield of large caps (1.5 mm × 1.5 mm, 25 µm thick) as a function of the Si/Au sealing ring width before and after dicing, after two months of storage in ambient pressure at room temperature. The data were collected from all the 432 large caps.

2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU 21 SEALS

2.3.3 Bond interface inspection To inspect the inter-atomic diffusion condition of the formed Au-Al intermediate metal compound (IMC) layers, representative cavities with different Si/Au sealing ring widths were diced. The SEM images of the cross-sections are shown in Fig. 2.11. The original 2.65 µm-high Au-Al metal stacks were all compressed, confirming the occurrence of the plastic deformation at the bond interfaces. The difference in thickness of the Au-Al IMC layers was attributed to resulting non- uniform bonding pressure at different sealing ring structures (different widths) on the cap wafer.

1 μm 1 μm 1 μm Si sealing ring 6 μm 15 μm 27 μm

Au-Al IMC layer 1.10 μm 1.37 μm 1.75 μm

SiO2 Cavity wafer Si (a) (b) (c)

Si 500 nm

Au-Al IMC layer TiW Si map O map Au map Al map Ti map

SiO2 500 nm (d) (e) (f) (g) (h) (i)

Figure 2.11. Cross-sectional SEM images of the Au-Al bond interfaces. (a)-(c) Bond interfaces of 6 µm, 15 µm, and 27 µm-wide Si/Au sealing rings, respectively. (c) Focused ion beam (FIB) milled bond interface of the region marked in (c). (e)-(f) Silicon, oxygen, gold, aluminum, titanium element maps of (d) measured by electron-dispersive X-ray spectroscopy (EDS).

The bond interface was further analyzed by electron-dispersive X-ray spectroscopy (EDS) after polishing by a focused ion beam (FIB). The resulting element maps are shown in Fig. 2.11e-f. Clearly, the Au and Al had uniformly inter-diffused within the Au-Al IMC layers, although individual micro-voids were sometimes found at the bond interfaces. An Au to Al atomic ratio of more than 4.8 was derived from the EDS analysis, indicating the formed IMCs were likely to be Au4Al or a combination with Au8Al3. This is in agreement with the reported IMC components of the Au-Al wire bonds that underwent a similar thermal process at 250 °C [99]. In addition, the exposed Au-Al IMCs exhibited a tan color after shear testing, indicating the presence of Au4Al or Au8Al3. These two types of Au-rich IMCs are considered as ductile materials [100], [101], in contrast to brittle “purple plague” AuAl2, thus are potentially beneficial for the reliability of the bond.

22 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU SEALS

2.3.4 Hermeticity evaluation The long-term hermeticity was evaluated by monitoring the cap deflections for over a period of two months by white-light interferometry, similar to Section 2.2.3. A conservative calculation using (1) derives a leak rate of 1.2 × 10–12 mbarL/s, which again reflects the detection limit of this measurement. A more precise estimation was achieved by RGA performed on the three representative sealed cavities featuring different Si/Au sealing ring widths. The RGA results are shown in Table 2.3. The achieved vacuum level was on the order of 1 – 3 mbar 101 days after bonding. This corresponds to a worst-case estimated leak rate of 2.8 ×10–14 mbarL/s. The detected gas species revealed no traces of H2O and O2, demonstrating the excellent hermeticity of the seals. The achieved vacuum level is suitable for application such as pressure sensors, accelerometers [19], as well as NEMS relays and MOEMS devices where O2-free and H2O-free atmospheres are required [102], [103]. An additional outgassing step, and a more thorough pumping during bonding should help achieve lower vacuum in the sealed cavities, as indicated by previous work [64]. If very high vacuum is desired, getters can be incorporated inside the cavities and activated after sealing.

Table 2.3. Residual gas analysis results of three evaluated cavities.

Pressure Pressure Pressure Gas (6 µm-wide seal) (15 µm-wide seal) (27 µm-wide seal) (mbar) % (mbar) % (mbar) % Ar 4.3 × 10–1 31.88 7.3 × 10–1 31.91 2.0 59.28

CO2 4.1 × 10–1 30.40 6.0 × 10–1 25.40 3.4 × 10–1 10.08

H2 2.0 × 10–1 14.83 5.7 × 10–1 24.13 5.5 × 10–1 16.30

CH4 2.0 × 10–1 14.83 2.5 × 10–1 10.58 2.6 × 10–1 7.71 CO 9.4 × 10–2 6.97 1.9 × 10–1 8.04 1.9 × 10–1 5.63 HCs* 1.3 × 10–2 0.96 2.1 × 10–2 0.89 3.3 × 10–2 0.98 He 1.6 × 10–3 0.12 1.0 × 10–3 0.04 8.7 × 10–4 0.03

O2 0 0 0 0 0 0

N2 0 0 0 0 0 0

H2O 0 0 0 0 0 0 Total 1.3 100 2.4 100 3.4 100 * HCs represents the contribution of light hydrocarbons (C2H6 and C3H8).

2.3.5 Bond strength evaluation The bond strength of the seals was characterized by shear testing (PC2400, Dage Ltd., UK). The resulting shear forces and corresponding shear strengths as a function of the width of the Si/Au sealing ring are plotted in Fig. 2.12. All the calculated average shear strengths were higher than 60 MPa, which is four times higher than the pass criterion of 12.4 MPa for die shear strength in the military standard [104]. The narrow 6 µm and 9 µm-wide seals demonstrated high mean 2.3 VACUUM SEALING BY ULTRA-THIN CAPS WITH NARROW AL-AU 23 SEALS shear strengths of 156 MPa and 127 MPa, respectively, which are higher than other reported metal-based seals of 25 – 90 MPa [39], [43], [67], [69], [105].

Figure 2.12. Measured shear force and shear strength as a function of the Si/Au sealing ring. 54 cavities with large Si caps (1.5 mm × 1.5 mm, 25 µm thick) were used for the tests, with 6 samples for each sealing ring width.

2.3.6 Temperature stress testing High temperature storage testing was performed on 45 sealed large cavities with different sealing ring widths in an oven. The temperature was ramped up to 300 °C in a N2 atmosphere for a duration of 1 hour. No gross leakage was found in all the tested samples. Since the required temperature during flip-chip bonding process for the reflow of solders and the curing of underfill materials is typically lower than 300 °C, the seals are potentially compatible with the flip-chip bonding process. In addition, a thermal cycling test was performed on other 45 cavities with large caps. The temperature was varied between −5 °C and 100 °C for 700 cycles with a cycle rate of 1.5 cycles/h and a soak time of 5 minutes at the endpoint temperatures, all in accordance with JEDEC standards [106], [107]. All the tested samples passed the test, demonstrating excellent temperature reliability of the achieved seals

Chapter 3

Large-area integration of 2D materials

This chapter describes the background of the integration of 2D materials and the challenges to be addressed in their application for large-scale production. Then, we propose a method for realizing large-area integration of 2D materials using BCB adhesive wafer bonding. The integration method is demonstrated on monolayer graphene, h-BN, MoS2, and formation of 2D heterostructures. The proposed method can potentially enable large-scale fabrication of 2D material-based electronics and offer a platform for material property research provided by stacking of different 2D materials.

3.1 Background 3.1.1 Introduction to integration of 2D materials 2D materials refer to sheets of materials that feature the thickness of a single layer of atoms or molecules constituting the materials. Reaching such a material dimension limit of sub-nanometer scale brings extraordinary properties that could have not been attained by their typical bulky state in nature. Graphene, h-BN, MoS2, and various other 2D materials have found their remarkable applications in field-effect transistors (FETs) [108]–[110], flexible and transparent electronics [111], [112], photodetectors/photoemitters [113]–[115], and memtransistors [116], etc. A critical step to enable practical application of 2D materials is to produce and integrate large-area 2D materials in standard industrial fabrication substrates, e.g. Si wafers, in a cost-efficient and scalable way. To date, the cheapest large-area production of industrial-grid graphene and h-BN is by chemical vapor deposition on Cu foils [117], [118]. How to achieve large-area transfer of these 2D materials from their growth substrate to various device fabrication substrates in a cost- efficient, clean, damage-free way has become the focus of tremendous studies. The conventional method for transfer CVD graphene is wet transfer, which employs a polymeric carrier layer, such as PMMA [119], [120] or PC [121], [122], coated on the graphene/Cu substrate. Then, the Cu substrate is etched in a FeCl3 solution, thus, leaving only the carrier/graphene sheet floating on the surface of the solution. After this, the device substrate is immersed in the solution and gently scoops up the carrier/graphene sheet. Finally, the carrier polymer is removed by wet transfer method leads to improved solutions, including bubble-delamination of graphene [126], enhanced RCA cleaning [127], and utilizing other polymeric

25 26 CHAPTER 3 LARGE-AREA INTEGRATION OF 2D MATERIALS carriers, e.g. paraffin [128]. However, these methods are either not suitable for massive production, or still rely on polymeric carriers that cannot be completely removed. On the other hand, dry transfer methods are also reported using tools such as rollers, laminators, and hot presses, etc. [120], [129]–[137]. Compared to wet transfer methods, these methods are advantageous in terms of the possibility of recycling the Cu foils and eliminating the liquid-induced wrinkles on the graphene. However, either polymer residues are inevitable due to the use of conventional polymeric carriers [120], [134], [137], or the damage is induced on the graphene during the transfer process [133]. The other dry transfer methods are demonstrated on different polymeric target substrates [129]–[132], [135], [136]. These approaches could find potential applications, e.g. in flexible electronics, but the used polymers are not compatible with standard microfabrication process on Si wafers.

3.1.2 Challenges in integration of 2D materials The challenge remains to be solved is how to realize large-area transfer of 2D materials from their growth substrate to standard microfabrication substrates (Si wafers) without the use of carrier polymer coating. In addition, since heterostructures by stacking different 2D materials have shown great potential in realizing high-performance electronic and photoelectric devices [138]–[142], an ideal transfer method for integrating 2D materials should be capable of forming heterostructures. However, no such demonstration has been shown to meet these challenges in the state-of-the-art solutions.

3.2 Method Here, we present a method for integrating large-area 2D materials by adhesive wafer bonding. The method is evaluated for transfer of monolayer graphene, h-BN, and MoS2 from their growth substrates on standard Si wafers and for creation of graphene bilayers and graphene/h-BN heterostructures by multiple transfer cycles on the same substrate. The advantages of our approach are: no carrier polymer coating on the device side of the 2D materials, thus avoiding organic contamination; utilizing standard wafer bonding tool for the transfer, thus involving no manual transfer operations; using bisbenzocyclobutene (BCB) as the adhesive, which is compatible with semiconductor fabrication process and has tunable curing extent [143] that could enable stacking of different 2D materials. The transfer process of integrating large-area 2D materials is illustrated in Fig. 3.1 [144]). The process starts with spin coating of BCB on the Si substrate. Then, the 2D material together its growth substrate is placed on the BCB layer, followed by wafer bonding to attach the 2D material to the BCB layer. After bonding, the growth substrate is removed, e.g. Cu etching for CVD graphene and h-BN on Cu foils, thus leaving only the 2D materials left on the BCB/Si substrate. During the process, the device side of the 2D material is never in contact with any organic materials, thus ensuring the cleanness of its surface. As shown in Fig. 3.1, the transfer cycles can be repeated on the same BCB layer since the bonding

3.2 METHOD 27

temperature can be adjusted to partially cure the BCB layer to the desired extent for every transfer cycle.

Figure 3.1. Illustration of the 2D material transfer process (adapted from Paper 7). The same BCB layer can be used for multiple times of the bonding for stacking different 2D materials, thus creating heterostructures.

Temperature (°C) Temperature

Time Figure 3.2. The curing extent of BCB as a function of temperature and time. Reprinted from [145].

The processing parameters for the used BCB (CYCLOTENE 3022-46, Dow Inc.) are spin coating at 5000 rpm (2.5 µm thick), soft-baking at 100 °C for 4 minutes, a low bonding pressure of 0.25 MPa, and a curing/bonding temperature of 190 °C for 20 minutes in a vacuum environment (wafer bonder). This leads to a BCB curing extent of 35% – 40% and a relatively low viscosity of the BCB [143], as shown in Fig.3.2. Such effects facilitate the formation of close and gentle contact between 28 3.3 EVALUATION the BCB and the 2D material and enable multiple BCB bonding for forming 2D heterostructures.

3.3 Evaluation 3.3.1 Transfer of monolayer graphene

Figure 3.3. Raman spectroscopic characterization of the transferred graphene on BCB/Si substrate (Paper 7). Left: the measured Raman spectrum of the monolayer graphene, by subtracting the spectrum of the BCB/Si from the spectrum of graphene on BCB/Si. Middle: photograph of the transferred graphene on the 4-inch Si wafer. Thirteen regions were selected for the Raman characterization. Right: summary of the graphene transfer yield of different inspected regions.

The results of the wafer-level transfer of monolayer graphene (100 mm diameter) on BCB/Si substrate are shown in Fig. 3.3. The yield of the transfer is characterized by Raman spectroscopy (WITec Alpha 300R, 532 nm laser, 0.6 mW). Thirteen regions located at different parts of the wafer were inspected. For each region, a 60 × 60 spectra scanning was conducted. The presence of the monolayer graphene was verified by the presence of 2G and G peaks of in the spectrum. Despite the loss of graphene at limited locations, the overall transfer yield of the monolayer graphene (13 regions) is as high as 99.36%, demonstrating the remarkable yield of the presented transfer method. The electrical property of the transferred graphene is characterized by terahertz transmission time-domain spectroscopy (THz-TDS). Another transfer was performed to prepare the sample for this inspection. Part of the graphene/Cu sheet was cut out and treated by oxygen plasma to remove the graphene. The resulting partially transferred graphene is shown in Fig. 3.4. The THz-TDS measurement result clearly confirmed the transfer of graphene on the desired region. The derived sheet resistance of 800 – 1400 Ω/sq. agrees with the typical 3.3 EVALUATION 29

sheet resistance of monolayer graphene. Despite slightly increase in the center of the wafer, the sheet conductivity over the wafer exhibits good homogeneity.

(a) (b) Reference Region of interest No graphene With graphene

Graphene BCB BCB Si Si Cross-section A-A’ Cross-section B-B’

Figure 3.4. Sheet resistance characterization of the transferred monolayer graphene by Terahertz transmission time-domain spectroscopy (THz-TDS). (a) Photograph of the wafer with graphene partially transferred on the BCB layer. (b) Sheet resistance map derived by the THz-TDS measurement.

3.3.2 Formation of suspended graphene

Intact graphene

broken graphene 3 µm 2 µm

Suspended graphene

Figure 3.5. Suspended graphene over cavities formed in the BCB layer.

The possibility to create suspended 2D materials was demonstrated on graphene. The cavity (circular opening) was formed in the BCB layer by standard photolithography and plasma etching, after the pre-cure of the BCB. Then, a sheet of monolayer graphene was transferred onto the patterned BCB layer by the proposed method. The resulting suspended monolayer graphene on cavities is shown in Fig. 3.5. Circular cavities of different dimensions were evaluated. The graphene on openings of over 5 µm in dimeter almost all broke, and the highest yield was observed on openings of 1 – 2 µm in diameter. The suspended graphene 30 3.3 EVALUATION can be used for studies of material properties where the influence of the substrate is eliminated.

3.3.3 Formation of graphene/h-BN heterostructure Graphene/h-BN heterostructure was realized by two consecutive bonding for transfer of h-BN and graphene. A 2.5 cm × 2.5 cm sheet of multilayer CVD h-BN on a Cu foil was used for the first transfer bonding on the center of the BCB layer on a 4-inch Si wafer (190 °C, 20 min). After removal of the Cu foil, the 4-inch monolayer graphene was then transferred to the 4-inch wafer by the second transfer bonding (190 °C, 20 min). Therefore, a graphene/h-BN heterostructure was successfully yielded in the center of the wafer, as shown in Fig. 3.6a. The sheet resistance of the whole sheet was characterized by THz-TDS, as depicted in Fig. 3.6b. The derived sheet resistance showed good homogeneity over the wafer and exhibited no significant difference in the sheet resistance between the graphene and graphene/h-BN regions. Therefore, the presence of the h-BN underneath the graphene does not have a significant impact on the sheet resistance of the graphene.

(a) (b) Graphene on BCB Graphene/h-BN on BCB Graphene BCB Si C C’ Cross-section C-C’

D D’ Graphene h-BN BCB Si Cross-section D-D’

Figure 3.6. Transferred graphene/h-BN heterostructure on BCB and THz-TDS characterization. (a) Photograph of the transferred graphene/h-BN heterostructure in the middle of the Si wafer. (b) Sheet resistance map of the transferred graphene and graphene/h-BN regions over the wafer by THz-TDS.

The influence of the h-BN on the graphene property was further investigated by Raman spectroscopy. The results are shown in Fig. 3.7. The 2D and G peak positions of the measured spectra were used for creating the correction plot (Fig. 3.7a, b). Information on the doping condition and internal strain can be interpreted from these plots [146]. It is clear that p doping was present in both the graphene on BCB and graphene on h-BN. Compared to graphene on BCB, the doping level in graphene on h-BN is lower, indicating the reduced doping effect from the BCB substrate. The presence of both tensile and compressive strain in the graphene (both graphene on BCB and graphene on h-BN) were indicated by the plot. The average strain of the graphene on BCB is close to the intrinsic level, while for the 3.3 EVALUATION 31

graphene on h-BN, the overall strain moves more to the tensile status. This was likely ascribed to the higher viscosity of the BCB during the second bonding cycle, so that the tensile stress exerted on the graphene was not fully relaxed after cooling of the BCB. This effect might be useful for intentional strain tuning of 2D material to excite or manipulate their interesting properties [141]. In addition, the full width half maximum (FWHM) of the 2D peaks (Γ) of the spectra is used as an indicator for the process-induced defects or contamination on the graphene (Fig. 3.7c, d). The measured values of Γ for both the graphene on BCB and graphene on h-BN were similar (mean 28.8 cm-1 and 27.3 cm-1, respectively) and represented a low level compared to other transfer methods such as wet transfer and bubble transfer [137]. This indicates that the presented transfer process induces little defects and contamination on the transferred graphene.

(a) (b)

Figure 3.7. Raman characterization of the transferred graphene and graphene/h-BN heterostructure on BCB. (a, b) Plot of the correlation of the 2D and G peak positions (ω and ω respectively) for both samples. The full width half maximum of the 2D peak (Γ) positions are represented in the colormap. (c, d) Histogram of extracted Γ with Gaussian fit (µ: mean, σ: standard deviation). The total numbers of spectra for the graphene on BCB and graphene on h-BN are 430 and 124, respectively.

3.3.4 Transfer of MoS2 The applicability of our method on the transfer of other 2D materials was demonstrated by the transfer of MoS2. The MoS2 monolayer was grown on SiO2/Si chips by CVD. During the transfer, the MoS2 side of the chip was in contact with 32 3.3 EVALUATION

BCB on a Si wafer, surrounded by dummy Si chips of the same height to help uniformly distribute the bonding pressure. After wafer bonding (190 °C, 20 min), the bonded chip-wafer stack was placed in a KOH solution (2 M). After tens of seconds, the chip delaminated from the wafer due to KOH intercalation at the MoS2/SiO2 interface, thus completing the transfer process. The optical image of the transferred MoS2 on the Si wafer is shown in Fig. 3.8a, matching the dimension of the growth substrate (10 mm × 6.8 mm). The Raman spectra (WITec Alpha 300R, 532 nm laser, 0.1 mW) before and after transfer were collected from five random positions (from the same region) on the 1 MoS2 monolayer (Fig. 3.8b). Typical E 2g and A1g modes of the pristine MoS2 at 384.0 cm-1 and 405.2 cm-1 are clearly observed for the spectra before and after the transfer, which is in good agreement with reported values for monolayer MoS2 [147]–[149]. The minor measured changes in the characteristic Raman shift peaks 1 are below the detection limit of the tool, especially for the E 2g which is highly sensitive to uniaxial strain [150]. These facts demonstrate that the transfer process preserved the high quality of the MoS2 monolayer.

(a) (b) (c) Blue: Pre-Transfer E1 A Other: After-Transfer 2g 1g Several Pos. 4000 2000 0 CCD cts CCD -2000 2000 µm 360 380 400 420 440 rel. cm-1 Figure 3.8. Raman characterization of the transferred monolayer MoS2 on the BCB on a Si wafer. (a) Cropped optical image of the transferred MoS2 region on the BCB on the Si wafer. (b) Raman spectra of the five locations on the MoS2 layer before and after the transfer. (c) Changes in the characteristic peaks of the measured five spectra in the same regions before and after the transfer.

Chapter 4

Vertical integration of microchips

This chapter introduces the background of 3D assembly of microchips and the challenges to be addressed in realizing heterogeneous vertical integration of microchips. Then, a method is presented for achieving scalable vertical assembly of microchips that are in-plane fabricated from a source substrate to a separate receiving substrate, and subsequent high-throughput electrical contacting of the assembled microchips. Magnetic field-assisted assembly and wire bonding are used to realize the scalable heterogeneous vertical assembly and the electrical contacting, respectively. The proposed method based on standard microfabrication process and well-established wire bonding process potentially enables emerging MEMS applications that require 3D out-of-plane assembly of microchips.

4.1 Background 4.1.1 Introduction to 3D microchip assembly Conventional silicon microfabrication techniques for high-volume production of microchips are mature, scalable, and cost-efficient, yet typically do not allow the creation of out-of-plane 3D microstructures. However, many existing and emerging MEMS applications, such as inductors [151], RF antennas [152], optical attenu- ators [153], flow sensors [154], and biosensors [155], require their key components to be out-of-plane standing to fulfill their designed function. Therefore, the assembly and electrical packaging of micromachined in-plane structures into out- of-plane functional devices has become a key need for MEMS integration [156]. Ideally, the assembly and electrical contacting processes should not affect the functionality and the fabrication complexity of the planar microchips, hence not involving high temperatures, harsh chemicals, or unconventional materials. Initial attempts put efforts on realizing out-of-plane in-situ assembly of micro- components attached to the fabrication substrate using different principles, such as magnetically induced bending [151]–[154], [157], [158], bimorph-based bending by differential internal stress [159], [160] or thermal stress [161], [162], surface tension-driven assembly [163]–[165], and other more complex principle [166], [167]. However, these techniques do not allow assembly of the microchips in a separate substrate, which is needed, e.g. for sensing applications [155]. Besides, these methods typically either require the use of unconventional materials or high temperatures or do not form electrical connections. To enable heterogeneous out-

33 34 CHAPTER 4 VERTICAL INTEGRATION OF MICROCHIPS of-plane assembly, self-assembly principles have been investigated to achieve placement of discrete components on a surface of into a template of holes, including magnetic attraction [168], [169], dynamic fields provided by gravitational and magnetic force [170], and vibration stimuli [171]. Another interesting approach is to use magnetic field-assisted assembly for heterogeneous integration, as demonstrated on natively-ferromagnetic components [172]–[175]. However, these techniques do not allow assembly of microchips, and no directional control of the insertion of the components is realized. In addition, in the state-of-the-art solutions, the electrical contacts were made on both the frontside and backside of the receiving substrate where the two terminals of the embedded components were exposed [171], [173]. This also limits the number of electrical connections to a maximum of two. Another drawback found in these approaches is that the contacting methods involve harsh processes, such as high temperatures, physical polishing, chemical exposure, and plasma etching, which are not compatible with, e.g. biosensors.

4.1.2 Challenges in 3D microchip assembly The challenge remains unsolved in 3D microchip assembly is a generic and scalable method that achieves directional vertical 3D assembly of microchips into a separate receiving substrate and realizes the microchip-substrate electrical connections. Such a method should ideally use standard tools and micromachining methods that do not involve harsh processing or use of exotic materials, so that no adverse impact is exerted on the produced devices. Magnetic assembly serves as an interesting option for non-contact assembly but has not been realized on microchips yet. For contacting, it is preferable to use a well-established and high- throughput process, such as wire bonding. However, wire bonding is typically applied to in-plane metallic bond pads, although it has also been used for unconventional applications [14], including direct bonding on in-plane-patterned holes in silicon [176]. The possibility of using wire bonding on vertically standing microchips for bridging chip-substrate connections is still not demonstrated yet.

4.2 Method and experiments 4.2.1 Concept and microchip design This thesis presents a scalable integration method for vertical integration of microchips from their fabrication substrate into a separate receiving substrate. The vertical assembly of microchips is realized by magnetic assembly via ferromagnetic Ni coating on the backside of the microchips, thus enabling the manipulation of microchips using an external dynamic magnetic field. The electrical contacting is realized by standard ball stitch wire bonding cycles. The ball bonds are performed on the sidewall trenches of the vertically assembled microchips, which further contact the corresponding frontside electrodes on the chips. Thus, microchip-receiving substrate connections are established. The concept is schematically drawn in Fig. 4.1.

4.2 METHOD AND EXPERIMENTS 35

Metallic contacts Magnetic field Ball bond

In-plain electrodes N S Ni coating Wire bonder capillary Receiving holes Stitch bond Au wire

Microchips Receiving substrate Bond pads (a) (b)

Figure 4.1. Schematic drawing of the microchip vertical integration method. (a) Heterogeneous vertical assembly of in-plane fabricated microchips into a separate receiving substrate by magnetic assembly. (b) Electrical contacting of the microchips to the receiving substrate by wire bonding on the sidewall trenches of the vertically assembled microchips.

A suitable design of the microchip is critical for realizing directional control while microchips falling into the receiving holes and for reliable ball bonds on the sidewalls of the chips. First, the Ni coating (3 µm thick) on the backside of the microchips were stripped to provide preferable lifting direction of the microchips. Second, the microchips feature a “T” shape, as illustrated in Fig. 4.2, which comprises a main rectangular body and a slightly wider top over-hanging part. This feature only allows them to fall into the trenches in the correct direction, so that the wider top sidewalls, where the electrical connections will be created, remain outside of the matching holes because of their sizes. Third, the top sidewall trenches should induce proper plastic deformation of the Au free-air-balls (FABs), to both mechanically fix the ball bonds and create electrically contact with the frontside electrodes. For such a propose, different trench geometries were tested and eventually two reliable options were selected, as shown in Fig. 4.2. The first geometry (design A) features single trapezoid trenches, as illustrated in Fig. 4.2a. A suitable combination of opening width, trench depth, and base angle can help achieve sufficient plastic deformation of Au FAB, so that both the frontside edge metallic contacts and wedging of the Au FABs into the tapered trench walls can be achieved. The second design (design B), features double- trapezoid trench geometries (Fig. 4.2b). This is to increase the potential metallic contact area between the ball bond and the frontside electrodes. While several combinations of shape and dimensions were tested, these two geometries provided the simplest and most stable solutions. Metallic lines are incorporated on the frontside of the microchips as simple resistors between the left- and the right electrodes, to help evaluate the contact resistance of the metallic contacts. The central electrode is electrically separated from the other two electrodes to verify the correct insulation. The detailed geometries of the two microchip designs are 36 4.2 METHOD AND EXPERIMENTS summarized in Table 4.1. Different aspect ratios of the microchips are used for the testing.

(a) (b) Trench depth Opening width Base angle Chip head width

Overhang width

Chip length Thin film resistor

Design A Design B

Figure 4.2. Two designed microchip geometries for magnetic assembly and sidewall wire bonding.

Table 4.1 Key dimensions of the two types of microchip designs.

Dimensions of features Design Opening width Trench depth Base angle (µm) (µm) (degrees) A Trench 60 40 76 Top trench 60 25 68 B Bottom trench 30 20 63 Overhang width (µm) Chip length (µm) 40 750 Other parameters Chip thickness (µm) Chip head width (µm) 70 ± 5 330 / 500 / 1000 / 1500

4.2.2 Magnetic assembly The microchips were in-plane fabricated using standard silicon micromachining and were released from the Si wafers by breaking the supporting tabs surrounding the microchips using either laser ablation or ultrasonication under water, with the former option being a gentler process. Then, the collected microchips were spread on the receiving substrate. A magnet (1.37 – 1.42 T) was placed under the substrate and moved along the long edges of the arrays of receiving holes to manipulate the microchips until the receiving hole array was fully assembled. The studied array size varies from 1 hole to 6 holes. Each array was assembled for 50 times to collect sufficient data for statistical analysis. The number of movements of the magnet 4.3 EVALUATION 37 from one side of an array to the other (hereafter called magnet sweep) needed to fill each hole in an array was recorded.

4.2.3 Edge wire bonding The wire bonding for electrical contacting the vertically assembled microchips followed standard ball stitch wire bonding cycles. Epoxy glue was applied to the overhang edges to temporarily fix the microchips for reliable wire bonding and can be removed by acetone after the wire bonding if needed. The substrate temperature was set to be 30 °C during the entire process. Other used parameters are: Au wire diameter of 25 µm, a FAB diameter of 90 µm, an average ball bond force of 575 mN for design A and 650 mN for design B (100 ms bond time, no ultrasonic energy applied), and a stitch bond force of 500 mN (50 ms, 30% ultrasonic energy applied). The ball bonds were performed with a certain offset towards the frontside electrodes, to enhance the edge contact area. However, if this offset value was too small (as defined in Fig. 4.3), it could result in weak mechanical fixation of the Au balls inside the trenches. Experiments showed that for the used geometries, an offset of 10 – 20 µm is a suitable range to get reliable bonding.

(a) (b)

Free air ball (FAB)

Sidewall trench

Offset

Figure 4.3. Ball bond alignment settings during the sidewall wire bonding.

4.3 Evaluation 4.3.1 Assembly efficiency analysis The lifting directionality control was verified by comparing the lifting behaviors of microchips with uniform/stripped Ni coating and microchips of different aspect ratios, as shown in Fig. 4.4. It is clear to see that Ni stripping has a critical impact on the lifting directionality control, and the lifting principle works for all the tested microchip aspect ratios. Magnetic assembly is typically seen as a stochastic process, as reported by previous work [172], [177], [178]. Similar to previous work, we found that the number of magnet sweeps needed to fill one hole inside each array, being it the filling of the first hole the last hole of the array, followed an exponential probability distribution, as shown in Fig. 4.5a. The fitting parameter for the exponential distribution is the mean number of magnet sweeps � to fill an individual hole. Thus, the probability density function �(�) of such a distribution can be expressed 38 4.3 EVALUATION

(a) (b) Striped Ni layer S N N S

Uniform Ni layer

Switching magnetic polarity

300 µm 300 µm

Different microchip aspect ratios N N S S

Ni layer striped with 90° orientation Switching striping orientation

500 µm 500 µm

Figure 4.4. Reliable lifting directionality control of the microchips due to the striped Ni coating on the backside. (a, b) Switching the lifting directionality of microchips by changing the magnet polarity. (c, d) Lifting directionality of microchips independent of the microchip aspect ratios (length/width). using the following equation: �(�) = � (4.1) where � stands for the variable, i.e. the number of magnet sweeps. The mean number of magnet sweeps needed for each consecutive hole filling, scaled with the number of remaining empty holes in the studied array, is larger for the first assembly event in all the array sizes. However, the mean then converges to a stable lower value (Fig. 4.5b). The difference between the first single-hole assembly event and the rest of the events is explained by the increased number of microchip rotations caused by the protruding top parts of the already assembled microchips. The hypo-exponential distribution represents a series of exponentially distri- buted events and is thus suitable for modelling the stochastic process of completely filling an array. The information gathered from the exponential distributions of each consecutive hole filling was used to create the corresponding hypo-exponential distributions. The resulting probability density function of the modeled hypo- exponential distribution �(�) can be expressed using the following equation: �(�) = ∑ � ∏, (4.2) 4.3 EVALUATION 39

where � represents the mean number of magnet sweeps to fill the � hole in the studied array of � holes. The resulting hypo-exponential distributions matched well with the data representing the probability distributions of completely filling holes arrays of different sizes, as indicated by the example of data from the assembly of a 6-hole array (Fig. 4.5c). These distributions were also used for creating forecasts for the assembly of even larger arrays. A worst-case scenario with the largest mean number of magnet sweeps observed in the experiments (Fig. 4.5b, dashed line) was selected for such a purpose. The forecasted probability of completely filling a large array asymptotically approaches 100% after a relatively low number of magnet sweeps (Fig. 4.5d). For example, an array of 1000 holes would be completely filled with 99.8 % probability after only 180 magnet sweeps. Each manual sweep took a maximum of 2 seconds during our tests, and the assembly efficiency could possibly be further increased by using a robotic assembly setup with multiple magnets [177].

Figure 4.5. Statistical analysis of the magnetic assembly process of the microchips (500 µm wide, 25 µm gap between the designed microchip and the sidewalls of a receiving hole). (a) Histogram of the probability density distribution of filling an individual hole. The narrow blue lines show the measured number of magnet sweeps needed to fill a single hole in each of the 50 repetitions (rug plot of the number of occurrences). The exponential fitting curve uses the mean value as the fitting parameter. (b) Mean number of magnet sweeps to consecutively fill a hole in an array for different array sizes. The mean values are scaled with the number of empty holes left in the array. The dashed line shows the worst-case measured values used for making prognosis for larger arrays. (c) Histogram of the 40 4.3 EVALUATION probability density distribution of completely filling an array of six holes. The hypo- exponential fitting curve is modeled using mean values from (b) as parameters. (d) Probability density distribution of completely filling an array for different array sizes.

One critical factor affecting the assembly efficiency of filling an individual receiving hole is the range of microchip’s rotational freedom when falling into the hole. The rotational freedom can be defined as the range of rotational angles that the microchip can have while still fitting into the receiving hole, as a result of the relative size of the microchip with respect to the hole. Larger gap and narrow chip width would tend to increase the assembly efficiency, as verified by the additional tests. Therefore, a circular hole is expected to drastically increase the assembly efficiency, however at the cost of sacrificing the rotational position control of the microchips and the maximum assembly density.

4.3.2 Contact resistance of the wire bonds

100 μm 400 μm

(a)

Front view Side view Close-up side view Back view Design A Design

20 μm 20 μm 8 μm 20 μm (b) (c) (d) (e) Design B

20 μm 20 μm 8 μm 20 μm (f) (g) (h) (i)

Figure 4.6. SEM images of the wire bonded microchips that are already assembled. (a) SEM image of an array of wire bonded microchips (design A). Inset: close-up SEM image of a single wire bonded microchip. (b-i) SEM images of the ball bonds on the sidewall trenches of the microchips from different viewing angles and magnification for both designs. 4.3 EVALUATION 41

The feasibility of sidewall wire bonding is verified both on microchips with design A and design B, as shown in Fig. 4.6. 4 × 4 arrays of microchips with design A and design B both were successfully assembled, and both exhibited desired mechanical fixation of the ball bonds and the creation of the over-the-edge metallic contacts. The only difference between the two designs is that for microchips with design B, a higher average ball bonding force is needed. The quality of the over-the-edge contacts of different microchip designs was characterized by quantifying their contact resistance. This was achieved by measuring the resistance (four-wire configuration) of the microchip resistor before and after wire bonding. The difference would reflect the maximum contact resistance of the realized edge contact. The results for both designs are shown in Table 4.2. The changes in the mean resistance (16 samples) before and after wire bonding for design A and design B are 0.19 Ω and 0.08 Ω, respectively. These values are smaller than the corresponding standard error of the sample mean. This indicates that the contact resistance is negligible, thus demonstrating the excellent electrical conductance of the edge contacts. In addition, the resistance between the central electrode and the two adjacent electrodes was also measured before and after wire bonding. All the measured values exceeded the dynamic range of the instrument (R > 200 MΩ), confirming the correct insulation as designed.

Table 4.2. Measured resistance values of the microchip resistors before and after wire bonding (n = 16). Mean Before wire bonding After wire bonding variation (on the microchip frontside pads) (on the receiving substrate pads) Design ΔR (Ω) Standard error of the Mean Standard error of the Mean (Ω) sample mean (Ω) (Ω) sample mean (Ω) A 121.31 0.52 121.50 0.50 +0,19

B 116.78 0.44 116.86 0.52 +0,08

4.3.3 Bond strength evaluation The strength of the achieved wire bonds was characterized by a pull tester (Dage 4000Plus, Inseto Ltd., UK). The measured mean pull force to break the wire bonds (12 pairs each design) was 91.9 mN and 96.6 mN, with a minimum of 63.8 mN and 54.8 mN, for microchips with design A and B, respectively. All the broken points occurred at the stitch bond side, not on the ball bond side (chip edges). This demonstrated strong mechanical fixation of the ball-to-trench bonds. In fact, these values are already two to four times larger than the required value of 24 mN defined by military standard [104]. In order to evaluate the bond strength of the ball bonds, the stitch bonds of the microchips were fixated by epoxy glue for the pull tests (6 pairs for each design). In this case, all the tested Au wires were torn before any failure at the ball-to-trench bond interfaces occurred. The measure mean pull force when the Au wires broke were 175.4 mN and 173.5 mN, with a minimum of 168.6 mN and 166.6 mN, for design A and B, respectively. This again 42 4.3 EVALUATION proves the excellent bond strength of the ball bonds achieved in the sidewalls of the microchips.

4.3.4 Application demonstrator The potential use of the proposed vertical integration method was demonstrated on assembly and contacting of “T”-shaped microprobes vertically inserted in the lumen of hollow silicon microneedles. These microprobes have the same thickness and length as the presented microchips, but a narrower body, as shown in Fig. 4.7. The microchips, although not functionalized, aim to represent miniaturized sensors, similar to enzymatic biosensors embedded in microneedle lumens developed in a previous work [155]. Despite the fragility of such miniaturized devices, the microprobes were intact after edge wire bonding, demonstrating the applicability and further miniaturization possibility of the proposed technology. Hence, this is an example in which the presented process could possibly be useful, even with a sparse array of receiving holes, because of the impracticality to mechanically handle and contact such tiny and fragile devices.

(a) (b) 50 µm

280 µm Electrical pads m µ Microneedle 750 opening

Probe with electrodes

65 µm 100 um

Figure 4.7. Demonstrator of the presented contacting method by edge wire bonding on vertically assembled microprobes. (a) Illustration of the microprobe design and major dimensions. (b) SEM image of the microprobe vertically placed inside a microneedle lumen and electrically connected using edge wire bonding.

Chapter 5

Transfer of carbon nanotubes and silicon microstructures

This chapter introduces the background of heterogeneous integration of nanomaterials and microstructures for emerging electronic and sensing applications and the facing challenges. Then, this chapter presents a high-throughput and flexible method for transfer of nanomaterials and microstructures using a standard wire bonder. The method is demonstrated on the transfer of carbon nanotubes and Si microstructures from their fabrication substrates to various flexible and rigid host substrates for potential applications in flexible electronics, field emission sources, and rigid semiconductor assembly.

5.1 Background 5.1.1 Introduction to heterogeneous integration of nanomaterials and microstructures Heterogeneous integration of nanomaterials and microstructures from their original fabrication substrate to new a host substrate is a key step for realizing various systems with enhanced functionalities, such as MEMS, photonics, and electronics based on emerging materials [2], [7], [11], [179], [180]. Heterogeneous system-on-chip integration for combing MEMS and ICs and flexible electronics based on low-dimensional materials are typical examples that are enabled by material integration technologies. To realize such integrated microsystems, various methods have been proposed. Manual assembly of semiconductor photonic crystals, nanowires, and micro-fabricated MEMS components onto separate substrates has been demonstrated using microgrippers or probes [181]–[183]. However, these methods are not suitable for high-volume production. Therefore, different parallel heterogeneous integration methods have been developed, such as wafer bonding [184]–[189], screen printing [190]–[193], and transfer printing [11], [194]–[200]. Wafer bonding was used to transfer epitaxially grown III-V compound semiconductors (e.g. GaAs and GaN) to silicon or other substrates for Si photonic and photovoltaic applications [184]–[189]. These methods are scalable and potentially compatible with CMOS substrates. However, for the integration of materials that are fabricated on different wafer sizes, or integration of components having different dimensions, wafer bonding may not be a cost-efficient solution. As an alternative method, screen printing has the advantage of being a low-cost and

43 44 CHAPTER 5 TRANSFER OF CARBON NANOTUBES AND SILICON MICROSTRUCTURES scalable process. Using inks made of carbon nanotube (CNTs), nanowires, graphene oxide, etc., transfer printing has shown possible applications in displays, transistors, and paper-based sensors [190]–[193]. The problems associated with screen printing are the limitations in the achievable resolution of the printing process, and the potential degradation and contamination of the employed nanomaterials due to incomplete removal of solvents in the ink. Transfer printing, compared to wafer bonding and screen printing, is more versatile in the choices of source and host substrate materials/sizes and the type of materials to be transferred. Transfer printing uses a stamp, typically made of an elastomer, e.g. polydimethylsiloxane (PDMS), to realize the material transfer. The desired pick-up and placement operations are enabled by controlling the relative magnitude between the material-stamp and material-substrate adhesion forces. Previous work has demonstrated transfer printing of nanowires, CNTs, graphene flakes, III-V photonic components, or Si microstructures [11], [195]–[200] for electronic and photonic applications. Transfer printing has great potential for large-scale integration due to its versatility, flexibility, and high yield. However, it typically involves manual operation and/or custom-built tools to achieve reliable and precise pick-up, placement, and release of the transfer printed materials and structures.

5.1.2 Challenges in transfer printing The challenge in transfer printing is how to replace the custom-built tools with existing high-speed, high-precision, and cost-efficient manufacturing tools and infrastructure. For example, wire bonder is a mature platform that is widely used in the semiconductor industry. Features such as fast and precise movement control, substrate temperature tunability, and pattern recognition function are typically default capabilities of a wire bonder. Wire bonding has been investigated for use in various unconventional applications [14], [201]–[203], but not for the purpose of achieving material transfer. Exploiting wire bonding infrastructure into transfer printing can potentially provide a solution for low-cost, high-throughput, and versatile transfer of nanomaterials and microstructures.

5.2 Concept and experiments In this thesis, we present a high-throughput and versatile integration method using conventional wire bonding tools to realize the transfer printing of CNTs and Si microstructures. Standard ball stitch wire bonding cycles were used as scalable and high-speed pick-and-place operations to achieve the material transfer.

5.2.1 General principle Conventionally, ball stitch wire bonding cycles are used to bridge electrical connections between the fabricated semiconductor IC or MEMS dies and the hosting substrates. In our approach, the ball bonds and stitch bonds are used for either pick-up or placement of the single-walled carbon nanotubes (SWCNTs) and

5.2 CONCEPT AND EXPERIMENTS 45

Si micro-structures, instead of forming wire bonds. A commercial and non-modified automated wire bonder (ESEC 3100+, ESEC Ltd., Switzerland) together with Au wires (25 µm/50 µm) was used for testing. The substrate temperature during all the wire bonding operations was set to be 70 °C, making the transfer process a low- temperature process.

5.2.2 Transfer printing of CNTs The SWCNTs were synthesized by aerosol chemical vapor deposition (CVD) on a nitrocellulose film (source substrate). The aerosol CVD produces high-quality SWCNTs with precisely defined morphology, bundle formation, and layer thickness [204]. The diameters of the SWCNTs were about 2 nm, and the layer thickness was about 110 nm. The CNT layer was patterned by a femtosecond pulsed laser (Spirit One-4-SHG, Spectra-Physics, US), with near-IR radiation (1040 nm) in low power regime (24 nJ pulse energy, 100 kHz repetition rate) and a sample stage moving speed of 1000 µm/s. The resulting CNT patches of 100 µm in diameter were then used for the transfer printing process.

Figure 5.1. Schematic drawing of the process for transfer printing of CNTs from a source substrate to a target substrate by wire bonder. The transfer process consists of two wire bonding cycles.

The approach of transfer printing CNT patches from the source substrate to a target substrate by wire bonder is illustrated in Fig. 5.1. Two successively performed standard ball stitch wire bonding cycles are used. The first cycle begins 46 5.2 CONCEPT AND EXPERIMENTS with the formation of the free-air-ball (FAB, 200 µm diameter) by an electronic flame off (EFO). Next, a dummy “ball bond” (3500 mN, 50 ms) is performed on a silicon surface to flatten the bottom of the FAB, which serves as a “stamp” for the transfer printing. This is followed by a dummy “stitch bond” (1200 mN, 50 ms) to pick up the CNT patch. The porous nitrocellulose film has relatively weak adhesion to the CNT layer compared to the CNT-Au adhesion (Van der Waals force), thus facilitating its pick-up by the Au “stamp”. The second wire bonding cycle starts with the prevention of the FAB formation by passing the EFO current through a grounded wire adjacent to the target substrate instead of affecting the previously generated FAB. Then a dummy “ball bond” is performed on the target substrate to place the CNT patch as a result of the affinity between the CNTs and the target substrate, followed by a dummy “stitch bond” to dispose of the used “stamp”. After this, a new wire is generated and ready for the next transfer printing cycle. Thus, a clean stamp is used for every transfer cycle, ensuring the repeatability of the transfer process. The transfer approach was tested on PDMS, parylene, and parylene/Au target substrates since these are commonly used substrates for flexible and wearable electronics. Another merit of these polymeric substrates is that they exhibit good affinity to the CNTs, thus being beneficial for the placement of the CNT patches.

5.2.3 Transfer printing of Au FABs with CNTs

Figure 5.2. Schematic drawing of the process for transfer printing of Au FABs with CNTs to a target substrate for realizing field emission sources. The transfer process consists of a single wire bonding cycle.

The approach of transferring Au FABs (160 µm diameter) with stamped CNTs to an Au-coated Si substrate for realizing field emission sources is illustrated in Fig. 5.2. Field emission sources are key components of various electronic devices, such as displays, ionization sources, and X-ray sources. The hosting structures for the Au FABs with CNTs are through holes (130 µm diameter) prepared on 100 µm- or 200 µm-thick Si membranes. As indicated by Fig 5.2, the transfer process features 5.2 CONCEPT AND EXPERIMENTS 47 only one standard wire bonding cycle. The cycle begins with the formation of a FAB stamp, followed by a dummy “ball bond” (1200 mN, 50 ms) to pick up the CNT patch directly from the source substrate. Then, a dummy “stitch bond” (4000 mN, 25% ultrasonic energy, 50 ms) places and embeds the Au FAB together with the stamped CNT patch into a through-hole of the target Si substrate. After this, a new wire is generated for the next transfer cycle. The field emission measurement setup is illustrated in Fig. 5.3. A high voltage (AU-50P6-L, Matsusada Precision Inc., Japan) was applied between the transferred CNT-Au cathode and a tungsten (W) anode. The cathode and anode were all placed inside a vacuum chamber. The applied voltage was remotely controlled by a DC power source (Keithley2220-30-1) and the emission current were recorded using digital multimeters (HP34401A) and LabVIEW.

(a) (b) Anode side Vacuum High voltage source chamber Tunnelling electrons Embedding depth Tungsten anode

250 µm

A Si wafer

100 µm/200 µm CNTs/Au cathode Cathode side Vacuum chamber R Vacuum pump system

Figure 5.3. Field emission measurement setup. (a) Schematic of the measurement setup. (b) Image of the vacuum chamber components and related connections.

5.2.4 Transfer printing of Si microstructures The approach of transfer printing of Si microstructures from a source SOI substrate to a target substrate is illustrated in Fig. 5.4. The Si square dies prepared on the device layer of an SOI substrate serve as dummy microstructures for validating the transfer printing of microchips but could be potentially replaced by III-V components and other materials. The narrow pillars formed in the BOX layer function as temporary support of the Si dies. The transfer process consists of two standard wire bonding cycles. The first cycle starts with the formation of a FAB (100 µm diameter), followed by a dummy “ball bond” (500 mN, 50 ms) to flatten the FAB and ink the FAB with dry adhesive (drop cast MHDA, Sigma- Aldrich) simultaneously. Then, a dummy “stitch bond” (500 mN, 50 ms) picks up the Si die by breaking the BOX supporting pillars on the source SOI substrate. The second wire bonding cycle starts with a dummy “FAB formation” step by setting the EFO current to almost zero to avoid damage on the attached Si die. Then, a dummy “ball bond” (100 mN, 100 ms) places the Si die on an adhesive layer (Nitto Denko Corp., Japan) on the target substrate, followed by disposal of the used FAB 48 5.3 EVALUATION by a dummy “stitch bond” (500 mN, 30% ultrasonic energy, 50 ms). After this, a new wire is ready for the next cycle of die transfer. The adhesive layer can be released from the target substrate, thus serving as a flexible polymeric substrate for hosting the Si dies.

Figure 5.4. Schematic drawing of the process for transfer printing of Si microstructures from a source SOI substrate to a target substrate by wire bonder. Two wire bonding cycles constitute the transfer process.

5.3 Evaluation 5.3.1 Transfer printing of CNTs Successful transfer printing of CNTs on PDMS, parylene, and Au/parylene substrates by wire bonder was demonstrated, as shown in Fig. 5.5. Twenty cycles of transfer process were performed for each type of substrate, and the results turned out to be repeatable. The CNT patches picked up by the deformed Au FABs are clearly visible in the SEM image in Fig. 5.5b. For all the tested substrates, the achieved placement accuracy was within ±4 µm, which is close to the specified alignment accuracy of the wire bonder (±3 µm, at ±3� ). The contact of the transferred CNT patches to Au electrodes on the Au/parylene substrate was characterized by a four-wire resistance measurement. All the seven tested CNT patches on the Au/parylene substrate were found to be electrically conductive with an average measured resistance of 195±50 Ω. The transfer speed of approximately 0.35 second per CNT patch was realized without elaborate process optimization. 5.3 EVALUATION 49

The demonstrated CNT patches on the Au/parylene substrate could find applications in flexible electronics, for example as skin contact pads.

(a) (b) Flattened Au FAB CNT patch

ø100 µm

CNT patches

Nitrocellulose source substrate 200 µm 40 µm 400 nm

Transferred CNT patches Transferred CNT patches

Au electrodes

PDMS substrate 100 µm Parylene substrate 100 µm Parylene substrate 100 µm

Figure 5.5. CNT patches before and after the transfer process. (a) Optical image of an array of CNT patches (100 µm diameter) on its original growth substrate—a nitrocellulose film, after patterning by femto-laser ablation. The pitch size between the CNT patches is 250 µm. (b) SEM image of a CNT patch picked up by the flattened Au FAB (200 µm in diameter) after the first wire bonding cycle (Fig. 5.1). Inset: close-up SEM image of the CNTs. (c-e) Optical image of an array of CNT patches that were transferred to PDMS, parylene, and Au/parylene substrates.

5.3.2 Transfer printing of Au FABs with CNTs Successful transfer of CNT patches together with the Au balls into the through- holes of a Si substrate was demonstrated, as shown in Fig. 5.6a, b. A high yield of 90% (twenty tests) and a transfer speed of approximately 0.25 second per CNT/Au electrode were achieved without elaborate process optimization. The CNT patches were located 10 µm below the surface of the backside opening. By adjusting the backside etch depth, different CNT embedding depths with respect to the backside opening surface can be achieved (Fig. 5.4a), thus, the turn-on voltage of the field emission can be tuned accordingly due to different shielding effects. For example, for a cathode array with 2 × 2 CNT patches, a backside etch depth of 100 µm resulted in a CNT embedding depth of 110 µm and a turn-on voltage of ~2.6 kV (two tests). Instead, a backside etch depth of 200 µm resulted in a CNT embedding depth of 10 µm and a turn-on voltage of ~1 kV (six tests), as shown in Fig. 5.6c. According to the Fowler-Nordheim (F-N) theory [205], the dependence of the field emission current on the local electrical field can be expressed using the following equation:

50 5.3 EVALUATION

� = �� exp − , (5.1) � = � /(8�ℎ�), (5.2) � = (8�2�� )/(3�ℎ), (5.3) � = ��, (5.4) where �is the emission area of the CNT emitters, � is the local electric field at the CNT emission tips, � is the electron charge, ℎ is Plank’s constant, � is the work function of carbon, � is the effective mass of an electron, and � is the applied voltage. � is the local electric field enhancement factor, which reflects the local amplification effect on the electric field at the CNT emission tips due to the nanoscale sharp features of the CNTs. Transforming the above equation, the linear relationship between ln (�/�) and 1/� can be expressed using: ln (�/� ) = (−�/�)(1/�) + ln (�� ). (5.5) The typical measured emission data can be plotted (F-N plot) in this format, as shown in the inset of Fig. 5.6c. The plot exhibits good linearity, indicating the emission data is in agreement with the F-N field emission model. From the plot, a high � value of 8.55 × 106 m-1 was extracted (using a carbon work function of 5 eV), demonstrating the significantly high field enhancement effect of the CNTs.

(a) (b) CNT patch on Au ball

2 x 2 CNT patches cathode array

Through-Si hole

Si substrate 200 µm 20 µm

Linear fit ) 2 ln(I/U

β=8.55x106 m-1 Voltage (v) Voltage

1/U Emission current (µA) Emission current (µA)

U-Voltage (V) Time (s) Figure 5.6. Transferred CNT patches together with Au FABs for field emission characterization. (a) SEM image of a transferred 2 × 2 CNT patches cathode array together with Au balls embedded inside the through-holes in the Si substrate. (b) Close-up SEM image of a CNT patch on an embedded Au ball. (c) Measured field emission of a 2 × 2 CNT 5.3 EVALUATION 51 patches cathode array. Inset: Fowler-Nordheim (F-N) plot of the field emission data and the corresponding linear fit. (d) Stability of the field emission. The measurement was conducted at a constant voltage of 1560 V, at a chamber pressure of 1 × 10–5 mbar.

The field emission stability was investigated (two tests) by applying a constant voltage and recording the emission current variations over time (Fig. 5.6d). Despite slight degradation, the CNT cathodes demonstrated a stable emission current of ~10 µA at 1560 V for over 12 min. The chamber pressure stayed constant at 1 × 10– 5 mbar during the entire measurement period. The demonstrated field emitters can be used as miniaturized electron sources for applications such as micro- ionization sources and x-ray sources.

5.3.3 Transfer printing of Si microstructures Successful transfer printing of Si microstructures from a source SOI substrate to an adhesive target substrate was demonstrated, as shown in Fig. 5.7. A yield of 93.3% (thirty tests) and a transfer speed of about 0.35 second per die were achieved without elaborate process optimization. The adhesion between the Si dies and the flattened Au balls was enhanced by the inked MHDA dry adhesive. The thiol groups of MHDA can form thiol-Au semi-covalent bond [206] on the Au ball surface, thus, the carboxyl tail groups of MHDA adhesive tune the Au ball stamp to be hydrophilic, thus improving its affinity to the top native oxide of the Si die. Residues of the MHDA remained on the top surface of the Si dies right after the transfer and were easily removed by rinsing in isopropanol (IPA), as shown in Fig. 5.7c.

Si die attached to a flattened Au ball

Transferred Si dies (after IPA cleaning)

Residues of BOX pillars

Residues of the BOX pillar 50 µm 15 µm 50 µm (a) (b) (c) Figure 5.7. Results of transfer printing of Si dies using a wire bonder. (a) Optical image of the residues of the supporting BOX pillars after the removal of the Si dies by wire bonder. (b) SEM image of a Si die attached to a flattened Au ball. (c) Optical image of a 3 × 3 array of Si dies (200 µm pitch) transferred to an adhesive layer on a glass substrate. The residues of the MHDA adhesive on top of the Si dies were removed in isopropanol.

While the achieved placement accuracy of the Si dies was good (within ±4 µm), there was a significant rotational misalignment (±30°) of the Si dies, as shown in Fig. 5.7c. We believe this can be related to the straining and relaxation of the Au wires during the dummy ball stitch bonding steps. Nevertheless, the demonstrated approach can potentially be useful for transfer printing of light-emitting diodes (LEDs) from their fabrication substrate to a different host substrate.

Chapter 6

Summary and Outlook

This chapter summarizes the achievements of the thesis work beyond the state-of- the-art and presents the impact and prospects of the presented heterogeneous integration technologies.

6.1 Achievements This thesis aims to provide scalable and cost-efficient solutions to address the challenges in different aspects of heterogeneous integration technologies. Specifically, the presented methods deal with issues met in wafer-level vacuum/hermetic packaging, large-area integration of 2D materials, vertical assembly and electrical contacting of microchips, and scalable transfer of nanomaterials and microstructures. In order to maximize the compatibility with standard microfabrication tools and processes, all the presented solutions are based on well-established and high-throughput wafer bonding and wire bonding infrastructure.

Wafer-level vacuum packaging methods Two wafer-level vacuum packaging methods using metal-based wafer bonding are proposed and evaluated. The first method realizes the vacuum sealing by narrow Cu sealing rings of down to 8 µm in width, at a relatively low temperature of 250 °C. The second method demonstrates the combination narrow Al-Au sealing rings (down to 6 µm wide) with ultra-thin Si caps (25 µm thick) for vacuum packaging. The achievements of these two work beyond the state-of-the-art are the successful demonstration of wafer-level vacuum packaging methods that simultaneously combines different beneficial features, including low bonding temperatures (250 °C), narrow footprint sealing rings (< 10 µm), thin caps (25 µm), reliable hermeticity, sufficient mechanical strength, and the use of CMOS-compatible sealing materials (Cu and Al) (especially for Paper II), as indicated by Table 6.1. These features could enable ultra-miniaturization and cost reduction of heterogeneously integrated MEMS and NEMS, such as pressure sensors, accelerometers, and movable structures in photonic MEMS, which require vacuum/hermetic sealing.

53 54 CHAPTER 6 SUMMARY AND OUTLOOK

Table 6.1. Comparison between this thesis work and the state-of-the-art metal-based wafer-level vacuum/hermetic packaging methods.

Sealing ring Bonding Cap Metal Principle width temperature thickness Limitations Ref. used (µm) (°C) (µm) Eutectic Au-Si 100-300 390 > 300 [40] bonding Eutectic Sn-Pb 500 200 > 300 [42] bonding Eutectic Au-Sn 70 280 100 [43] bonding Au-In SLID 300 200 > 300 [39] Ni-Sn bonding 50 / 300 300 Solder / Cracked Pb-Sn-Ni SLID 50 300 5 [79] seals bonding SLID Cu-Sn 50 – 300 400 40 / 500 [105] bonding Au-Au 50 300 TC Not Cu-Cu 20 400 [54] bonding specified Al-Al 20 450 41 TC Au-Au 20 – 200 200 – 300 (etched in [60] bonding 500 µm Si) TC Al-Al 3 / 23 450 105 [53] bonding TC Al-Al 100 / 200 400 – 550 > 300 [52] bonding 40 TC In-In 200 140 (etched in [59] bonding 525 µm Si) Polymer Cold Room underfill is Au-Au > 150 20 [62] welding temperature needed; no cap division 1.5 / 3 µm TC / 30 – 65 Additional Au ring + Au+Ni/Sn Solder 300 (etched in solders are [63] Ø150 µm bonding 300 µm Si) needed solder patch Additional TC Cu-Cu 5 – 50 250 / 300 > 300 bond pads [66] bonding are needed TC Paper Cu-Cu 8 – 21 250 75 – 95 bonding I TC Paper Au-Al 6 – 27 250 25 bonding II

6.1 ACHIEVEMENTS 55

Large-area integration of 2D materials A scalable method for integration of large-area 2D materials from their growth substrates to standard fabrication substrates (Si wafers) using adhesive wafer bonding is presented and evaluated. BCB is used as the adhesive for bonding to enable the dry transfer of 2D materials and formation of 2D heterostructures, thanks to the tunable curing extent of BCB. Successful transfer of graphene, h-BN, MoS2, and formation of graphene/h-BN heterostructure are demonstrated. The achievement of this work is the realization of large-scale, clean, and damage- free dry transfer of 2D materials and formation of 2D heterostructures using standard wafer bonding tools, which has not been reported previously to our knowledge. This method could be used for scalable fabrication of emerging nanoelectronics such as high-speed transistors and photoemitters based on 2D materials and heterostructures.

Vertical integration of microchips A novel scalable method for vertical assembly and electrical contacting of microchips is presented and evaluated. The heterogeneous vertical assembly of microchips from their fabrication substrate to a separate target substrate is realized by magnetic assembly. The subsequent electrical contacting is achieved by wire bonding on the sidewalls of the vertically assembled microchips. The achievement of this work is the creation of a scalable method for heterogeneous out-of-plain assembly and electrical packaging of microchips using well-established and standard microfabrication processes and wire bonding tools, which has not been realized previously to our knowledge. The proposed method could be used for scalable 3D integration of microchips for emerging applications, e.g. biosensors that require vertical integration for minimally invasive diagnosis.

Transfer of carbon nanotubes and silicon microstructures A novel method for versatile and high-throughput transfer of carbon nanotubes and silicon microstructures from their fabrication substrates to new host substrates is demonstrated. The transfer process is realized by using a standard wire bonder as an automated “pick-and-place” tool. Transfer of CNTs to PDMS, parylene, and parylene/Au flexible substrates, transfer of CNTs together with Au FABs into rigid substrates, and transfer of Si microstructures onto adhesive layer are achieved. The achievement of this work is the demonstration of a novel method for versatile and high-throughput material transfer using standard wire bonders, which has not been reported to our knowledge. The presented method could be used for realizing CNT-based flexible electronics, field emission sources, and 3D integration of rigid semiconductor microstructures.

56 6.2 IMPACT AND PROSPECTS

6.2 Impact and prospects The presented methods in this thesis offer potential solutions to various and important issues and challenges existing in different aspects of heterogeneous integration, such as compact integration of MEMS/NEMS with ICs and novel electronic devices based on nanomaterials. They would serve as enabling and supporting technologies for realizing further miniaturized, cost-efficient, and multi-functional integrated micro- and nanosystems for emerging applications, such as intelligent automobiles, health monitoring, and IOT, thereby contributing to the construction of a smarter planet. There are also limitations associated with these methods. For the wafer-level vacuum sealing approach using ultra-thin Si caps, the use of SOI cap wafers and the cap thinning process by Si RIE are not ideal for overall cost reduction. Exploration of other cheaper alternatives for these aspects could be future work. For the integration of 2D materials using adhesive wafer bonding, a different resting substrate other than BCB is sometimes preferable, e.g. silicon oxide. Amelioration of the method for this purpose could be further investigated. In addition, how to realize the front-back orientation control of the microchips during the magnetic assembly and how to minimize the rotational errors in the wire bonder-assisted transfer of Si microstructures could also be useful focuses of future work. On the other hand, the application of the presented methods for realizing practical micro- and nanodevices would be the ultimate goal of this thesis. Fortunately, some of the presented methods have already been partially used in other projects. For example, the wafer-level vacuum sealing method featuring ultra-thin Si caps is being used as the hermetic capping method for packaging photonic MEMS in the EU funded project MORPHIC (Horizon 2020, Grant 780283). In addition, the vertical microchip integration method is being investigated to realize embedded glucose sensors in hollow Si microneedles.

Acknowledgement

First and foremost, I would like to thank Göran Stemme for giving me the opportunity to start my PhD journey in the Department of Micro and Nanosystems. I really appreciate your trust, steering, and patience along the way, regardless of its ups and downs. I would also like to express my sincere gratitude to my co- supervisors, Frank Niklaus and Niclas Roxhed, for your continuous encouragement and support, both spiritually and practically. I would have not made it so far without your help. My special thanks go to Wouter Metsola van der Wijngaart for proof-reading my thesis. Kristinn, thanks a lot for the enjoyable cooperation in the MORPHIC project and funding me during my last year of PhD. Thank you Valentin, Xuge, Bernhard, Carlos, Stephan, Simon, Floria, Federico, Miku, Arne, Torben, and Mikael (Sandell). Seeing you guys at work and on other gather-up occasions after work has been one of the driving forces to keep me moving on. I cherish the meaningful discussions on research and life with Valentin, the genuine Chinese working ethics and wisdom found from Xuge, the soul-crushing yet stimulating daily talks with Bernhard, the humors and innovative thoughts shared by Carlos, the taming skills for the wire bonder taught by Stephan, the helpful suggestions on work and life from Simon especially during my early days at MST, the relaxing and pleasant talks during lunch breaks with Floria, the wonderful time spent together with Federico and Miku on work, climbing, and bubble soccer, the inspiring talks with Arne and your positive mode both at work and during the late dinners in Kista Galleria, the never-ending hours spent together with Torben on ICP, and the excellent Sill Lunch and private events organized by Mikael. I would also like to thank Mikael Bergqvist for your amazing expertise and continuous support in machining all kinds of artworks, and Cecilia Aronsson for your always-online phone support and mastership not only in cleanroom processing but also in making nut cookies. I would have to spend two more years to reach so far without your support. Thank you Anna for organizing the excellent Journal Club course, Joachim for organizing the impressive Hands-on MEMS course, Erika and Ulrika for providing the most efficient administration I have ever seen, Linnea for keeping the MST lab tidy and your help in translating my thesis abstract, Gabriel for introducing me the X-ray project and borrowing me the PVA samples, Mikael (Antelius) for providing the solid basis for my initial PhD work, Staffan for showing me the high-voltage setup, Pierre for your unconditional support in the MORPHIC project, Alessandro for sharing all kinds of useful information and your help in laser machining, Maoxiang for sharing your experience both for work and life, Weijin for your dedicated maintenance to the UV lamp and your help in many private matters, Janosch for your excellent teamwork in Hands-on MEMS course,

57 58 ACKNOWLEDGEMENT

James for your talent in preparing various gifts, Laila for your always-smiling face and help in setting up the high-voltage sources, Ilya for providing me the precious CNT samples, Tommy for your humorous and inspiring speeches, Jonas for your unforgettable performance in many after-defense parties, Fritzi for your amazing organization of MST events, Umer for being always nice and saving the CPD tool many times, Simone for your valuable input regarding magnetic assembly, Reza for your warm greetings every time we met, Xinghai for maintaining the CPD tool, Hithesh for the badminton sessions together, Emre for your active participation in various MST matters, Serguei for sharing your knowledge on CNTs, Isabelle for being an excellent lab coordinator, Dimitrios for managing the lab-related ordering efficiently, Thomas for organizing the MST Poster sessions, Shyam for valuable input on my research during the group meetings, Oleksandr for bringing delicious snacks to MST, Adrian for keeping the ALOES tool running, Mikolaj for letting me know more about Poland, Aleksandr for teaching the Hands-on MEMS course, and the rest of MST group members: Mina, Dmitry, Alexsander, Hans, Andreas, Niklaus S., Gaspard as well as the others that are not named here. It is you folks who contribute to the caring and comfortable atmosphere at MST. It was a great experience to be with you and be a part of MST crew. Furthermore, I would like to thank the Kista cleanroom staff. Magnus, Roger, Per-Erik, Yong-bin, Alex, Arman, Reza, Per, and all the others that are not named here. Thank you for your patient guidance and efficient fix for the cleanroom equipment whenever there was a problem. Thank you Costas, Ganesh, Shuoben and all the other cleanroom buddies for our profound love and hate towards cleanroom processing. In the last year of PhD studies, I was lucky to join the MORPHIC project and worked together with outstanding researchers and experts from different institutions and companies in Europe. Wim, Niels, Peter, Yuji, Hamed, Yu, Moises, How Yuan, Marco, Christina, Iman, Banafsheh, and all the other members that are named here, I really enjoyed collaborating with you folks and I must say that you inspired my interest in photonics. I would like to extend my sincere gratitude to my Master supervisor Prof. Junyong Tao and my previous colleagues Dr. Bin Liu, Dr. Yun-an Zhang at National University Defense Technology. You were my mentors who guided me into academia and provided me valuable opportunities to work on exciting topics in my early career. To date, I still receive your care and support from time to time. I would have not started looking for PhD positions if it were not your encouragement. It was a great honor to know you and work with you. Besides, I deeply appreciate the financial support from China Scholarship Council (CSC) as well as other funding sources. I own special thanks to my Chinese friends who have greatly enriched my life in Sweden. Yansong Ren, Shuai Shi, Meng Jiang, Kun, Jie Fu, Zibo liu, Shuang He, Jie Ren, Sheng Jiang, Jinzhi Lu, Yushan Zhou, Kexin Liu, Jie Hao, Junzhi Wang, Qin Xiong, Chao Zheng, Ke Lu, Yang Zhang, Silun Zhang, Xinlei Yi, Mousong Wu, Yubao Song, Boqian Wang, Xin Zhao, Xikun Hu, Yiheng Tong, Wei Wang, Han Chen, and all the other friends that are not named here. I could not image how to survive the winter in Sweden without you.

ACKNOWLEDGEMENT 59

Finally, I would like to express my deepest gratitude to my family members, my father, my mother, my brother, and of course my beloved Xin. Your consistent love to me is the strongest spiritual support that has driven me through all the ups and downs. There is nothing more fortunate for me to have you in my life!

Xiaojing Wang, Stockholm, Sweden 4th of September, 2019

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