Study and Characetrization of Plastic Encapsulated Packages for MEMS Anjali W
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Flip Chip Based on Connections – Through Hole – Surface Mount PRASANNA S GANDHI [email protected]
Lecture 20: Packaging MEMS ME 645: MEMS: Design, Fabrication and Characterization P.S. Gandhi Mechanical Engineering IIT Bombay Acknowledgements: Mukul Tikekar, Dr Anandroop Bhattacharya PRASANNA S GANDHI [email protected] What is packaging? Service and art of providing a suitable environment to the electronic/ MEMS product as a whole to perform reliably over a period of time To protect delicate components from structural damage and/or malfunctions No addition to functionalityPRASANNA S GANDHI [email protected] 1 Motivation MEMS packaging is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications Packaging is aaveryverylarge percentage of the total cost of MEMS devices MEMS packikaging iiissaaltlmost alllways app licati on specific and greatly affected by its environment and packaging techniques We will first have a look at electronic packaging and then MEMS PRASANNA S GANDHI [email protected] Electronic Packaging Levels of Packaging Edge connector Wafer Chip Printed circuit board Chip Carrier Back panel Chassis PRASANNA S GANDHI [email protected] 2 Level – I Packaging: Chip to Chip Carrier Chip carrier – Housing for the thin and fragile chip Purpose – Protects the chip from environment and abusive handling – Facilitates interconnections from the chip to the pads/holes on the circuit board – Provides pins/pads for that serve as bases for solder joints – Also involved in the heat transfer process as the first step in the heat flow path from source to sink PRASANNA -
Copper Wire Bonding
Copper Wire Bonding Preeti S. Chauhan • Anupam Choubey ZhaoWei Zhong • Michael G. Pecht Copper Wire Bonding Preeti S. Chauhan Anupam Choubey Center for Advanced Life Cycle Industry Consultant Engineering (CALCE) Marlborough, MA, USA University of Maryland College Park, MD, USA Michael G. Pecht Center for Advanced Life Cycle ZhaoWei Zhong Engineering (CALCE) School of Mechanical University of Maryland & Aerospace Engineering College Park, MD, USA Nanyang Technological University Singapore ISBN 978-1-4614-5760-2 ISBN 978-1-4614-5761-9 (eBook) DOI 10.1007/978-1-4614-5761-9 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2013939731 # Springer Science+Business Media New York 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. -
Chapter 9 Chip Bonding At
9 CHIP BONDING AT THE FIRST LEVEL The I/O interface to the die primarily interconnects electrical power, ground and signals. It must provide for low impedance for the power distribution system, so as to keep switching noise within specification, and controlled impedance for the signal leads to allow adequate signal integrity. In addition it must accommodate all the I/O and power and ground leads required, and at the same time, minimize the cost for high volume assembly. The secondary role of chip bonding is to be mechanically robust, not interfere with thermal man- agement and be the geometrical transformer from the die features to the next level of packaging features. There are many options for the next level of interconnect, including: ¥ leadframe in a single chip package ¥ ceramic substrate in a single chip package ¥ laminate substrate in a single chip package ¥ ceramic substrate in a multichip module ¥ laminate substrate in a multichip module ¥ glass substrate, such as an LCD (liquid crystal display) ¥ laminate substrate, such as a circuit board ¥ ceramic substrate, such as a circuit board For all of these first level interfaces, the chip bonding options are the same. Illustrated in Figure 9-1, they are: ¥ wirebond ¥ TAB (tape automated bonding) ¥ flip chip; either with a solder interface, a polymer adhesive or a welded joint Because of the parallel efforts in widely separated applications involving similar, but slightly dif- ferent variations of chip attach techniques, seemingly confusing names have historically evolved to describe some of the attach technologies. COG (chip on glass) refers to assembly of bare die onto LCD panels. -
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems XIAOJING WANG Doctoral Thesis Stockholm, Sweden, 2019 Front cover pictures: Left: SEM image of an array of vertically assembled microchips that are electrically packaged by wire bonding. Right: Optical image of wafer bonded ultra-thin silicon caps of different sizes for wafer-level vacuum sealing. KTH Royal Institute of Technology School of Electrical Engineering TRITA-EECS-AVL-2019:65 and Computer Science ISBN 978-91-7873-280-7 Department of Micro and Nanosystems Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektroteknik och datavetenskap fredagen den 4:e oktober klockan 10:00 i Sal F3, Lindstedtsvägen 64, Stockholm. Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at KTH Royal Institute of Technology, Stockholm, Sweden. © Xiaojing Wang, September 2019 Tryck: Universitetsservice US AB, 2019 iii Abstract Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high- throughput heterogeneous integration challenges for emerging applications. The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding. -
Pdf [70] BE Semiconductor Industries N.V
This is an accepted version of a paper published in Journal of Micromechanics and Microengineering. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination. Citation for the published paper: Fischer, A., Korvink, J., Wallrabe, U., Roxhed, N., Stemme, G. et al. (2013) "Unconventional applications of wire bonding create opportunities for microsystem integration" Journal of Micromechanics and Microengineering, 23(8): 083001 Access to the published version may require subscription. Permanent link to this version: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-124074 http://kth.diva-portal.org UNCONVENTIONAL APPLICATIONS OF WIRE BONDING CREATE OPPORTUNITIES FOR MICROSYSTEM INTEGRATION A. C. Fischer1, J. G. Korvink23, N. Roxhed1, G. Stemme1, U. Wallrabe2 and F. Niklaus1 1 Department of Micro and Nanosystems, KTH Royal Institute of Technology, Stockholm, Sweden 2 Department of Microsystems Engineering - IMTEK, University of Freiburg, Germany 3 Freiburg Institute for Advanced Studies - FRIAS, University of Freiburg, Germany E-mail: [email protected] Abstract. Automatic wire bonding is a highly mature, cost-efficient and broadly available back-end process, intended to create electrical interconnections in semiconductor chip packaging. Modern production wire bonding tools can bond wires with speeds of up to 30 bonds per second with placement accuracies of better than 2 µm, and the ability to form each wire individually into a desired shape. These features render wire bonding a versatile tool also for integrating wires in applications other than electrical interconnections. Wire bonding has been adapted and used to implement a variety of innovative microstructures. This paper reviews unconventional uses and applications of wire bonding that have been reported in the literature. -
A Footprint Study of Bond Initiation in Gold Wire Crescent Bonding Norman Zhou, X
IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES 1 A Footprint Study of Bond Initiation in Gold Wire Crescent Bonding Norman Zhou, X. Li, and N. J. Noolu Abstract—The morphological features of the crescent bond interfacial deformation to remove surface contaminants by sur- footprints on the substrate after peeling the wire off were studied face extension (i.e., to expose clean surfaces for bonding), re- to gain an understanding of the effect of process parameters on the gardless of the application of ultrasonic energy [6], [8]–[10]. crescent bond formation. In the absence of any ultrasonic energy, metallurgical bonding initiated at the peripheral regions of the Typical observations of bonded and nonbonded regions in the crescent bond. The bond strength improved at higher substrate periphery and middle regions of a wire bond is cited by the de- temperatures and higher bonding force which promoted higher formation theory to discount fretting mechanisms caused by in- shear deformation of the substrate. The application of ultrasonic terfacial sliding. According to the deformation theory, ultrasonic energy drastically improved the growth of micro welds along the energy merely acts to reduce the force required to deform the bond interface and produced micro weld patterns on the footprint that are characteristic of the level of ultrasonic energy applied. wire and substrate [6], [9]. The effect of these process parameters on the mechanisms of However, based on studies of Au ball bonding using mi- crescent bonding are discussed. crosensors, Mayer et al. [11] indicated that the sliding and Index Terms—Bonding force, bonding mechanisms, footprint scrubbing at the bump/pad interface plays a significant role in morphology, gold wire crescent bonding, substrate temperature, the bond formation and ultrasonic softening contributes little ultrasonic energy. -
Chapter A: Wire Bonding 2 Level 2. Conclusions and Guideline
Chapter A: Wire Bonding 2 Level 2. Conclusions and guideline 2.1 Wirebonding techniques There are two basic wirebonding techniques that are used in thermocompression (T/C), thermosonic (T/S) or ultrasonic (U/S) bonding process: ball bonding and wedge bonding. Approximately 93% of all semiconductor packages are manufactured using ball bonding method, while wedge bonding is used to produce about 5% of all assembled packages. 2.1.1 Ball bonding In this technique, wire is passed through a hollow capillary, and an electronic-flame-off system (EFO) is used to melt a small portion of the wire extending beneath the capillary. The surface tension of the molten metal from a spherical shape, or ball, as the wire material solidifies. The ball is pressed to the bonding pad on the die with sufficient force to cause plastic deformation and atomic interdiffusion of the wire and the underlying metallization, which ensure the intimate contact between the two metal surfaces and form the first bond (ball bond). The capillary is then raised and repositioned over the second bond site on the substrate, a precisely shaped wire connection called a wire loop is thus created as the wire goes. Deforming the wire against the bonding pad makes the second bond (wedge bond or stitch bond), having a crescent or fishtail shape made by the imprint of the capillary’s outer geometry. Then the wire clamp is closed, and the capillary ascends once again, breaking the wire just above the wedge, an exact wire length is left for EFO to form a new ball to begin bonding the next wire. -
Recent Progress in Transient Liquid Phase and Wire Bonding Technologies for Power Electronics
metals Review Recent Progress in Transient Liquid Phase and Wire Bonding Technologies for Power Electronics Hyejun Kang 1, Ashutosh Sharma 2 and Jae Pil Jung 1,* 1 Department of Materials Science and Engineering, University of Seoul, 163 Seoulsiripdae-ro, Dongdaemun-gu, Seoul 02504, Korea; [email protected] 2 Department of Energy Systems Research and Department of Materials Science and Engineering, Ajou University, Suwon 16499, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-2-6490-2408 Received: 8 June 2020; Accepted: 7 July 2020; Published: 11 July 2020 Abstract: Transient liquid phase (TLP) bonding is a novel bonding process for the joining of metallic and ceramic materials using an interlayer. TLP bonding is particularly crucial for the joining of the semiconductor chips with expensive die-attached materials during low-temperature sintering. Moreover, the transient TLP bonding occurs at a lower temperature, is cost-effective, and causes less joint porosity. Wire bonding is also a common process to interconnect between the power module package to direct bonded copper (DBC). In this context, we propose to review the challenges and advances in TLP and ultrasonic wire bonding technology using Sn-based solders for power electronics packaging. Keywords: power module; TLP bonding; wire bonding; brazing; die-attached materials 1. Introduction Due to rapid progress in power electronics and packaging devices, there is a strong demand for better joining materials and processes. However, conventional silicon power module devices are now being replaced with high power ceramic modules made of SiC or AlN packages, which have better thermal stability at higher temperatures [1]. -
Materials, Processing and Reliability of Low Temperature Bonding in 3D Chip Stacking
Journal of Alloys and Compounds 750 (2018) 980e995 Contents lists available at ScienceDirect Journal of Alloys and Compounds journal homepage: http://www.elsevier.com/locate/jalcom Review Materials, processing and reliability of low temperature bonding in 3D chip stacking * Liang Zhang a, b, , Zhi-quan Liu b, Sinn-Wen Chen c, Yao-dong Wang d, Wei-Min Long e, Yong-huan Guo a, Song-quan Wang a, Guo Ye a, Wen-yi Liu a a School of Mechatronic Engineering, Jiangsu Normal University, Xuzhou 221116, China b Institute of Metal Research, Chinese Academy of Sciences, Shenyang 110016, China c Department of Chemical Engineering, National Tsing Hua University, China d Intel Corp., 5000W. Chandler Blvd, Phoenix AZ85226, USA e State Key Laboratory of Advanced Brazing Filler Metals & Technology, Zhengzhou Research Institute of Mechanical Engineering, Zhengzhou 450001, China article info abstract Article history: Due to the advantages of small form factor, high performance, low power consumption, and high density Received 23 January 2018 integration, three-dimensional integrated circuits (3D ICs) have been generally acknowledged as the next Received in revised form generation semiconductor technology. Low temperature bonding is the key technology to ensure the 21 March 2018 chip (or wafer) stacking in 3D ICs. In this paper, different low temperature bonding methods for chip (or Accepted 3 April 2018 wafer) stacking were reviewed and described systematically. Materials, processing and reliability will be Available online 7 April 2018 extremely important, their effects on the 3D IC structure were addressed in detail, the challenging reliability issues may be considered as the major concern in the future work. -
Polymer Micromachining Packaging of MEMS Sensors Mikrosensorer
Mikrosensorer Polymer Micromachining Packaging of MEMS sensors Project meeting 1 Sensor Time Accelerometer 18/4 , 9.15 Pressure sensor 18/4 , 10.15 Flow sensor 18/4, 11.15 Polymer Micromechanics Polymer Micromachining Cheaper materials Low cost fabrication Allow single use ”thermal recycling” Rapid prototyping Very flexible electronic components (design & state) Polymer Micromechanics • Thin Film Litography • Hot Embossing • Injection Moulding • Laser Fabrication • 3D-printing Polymer classes Plastic: materials that can be formed into shapes. Thermoplastic: materials that can be shaped more than once. Thermosetting plastic: material that can only be shaped once. Elastomer: material that is elastic in some way. If a moderate amount of deforming force is added, the elastomer will return to its original shape. Useful for fibers. Properties of Polymers • Chain length • Structure, orientation of chains • Identity of side groups • Degree of cross‐linking – Cross linking with covalent bonds formed between chains make the polymer stiffer; more crystalline Thermoplastics Melting (Tm) Rubbery flow OSTE(+) Carlborg et al Lab on a chip 2011 Saharil, F., et al µTAS 2012 Particle doped polymers • Magnetic particles • Silver • Carbon / graphene Hot Embossing Nano Imprint Litography (NIL) Thin Films Higher Temperatures Curable Polymers Limit in aspect ratio rather than linewidth Very high resolution Injection Moulding High throughput massfabrication Expensive initial cost Limited resolution (10 µm) 3D printing Stereolitography • Polymerisation