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Flip Chip „ Based on Connections – Through Hole – Surface Mount PRASANNA S GANDHI [email protected]

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Flip Chip „ Based on Connections – Through Hole – Surface Mount PRASANNA S GANDHI Gandhi@Me.Iitb.Ac.In Lecture 20: Packaging MEMS ME 645: MEMS: Design, Fabrication and Characterization P.S. Gandhi Mechanical Engineering IIT Bombay Acknowledgements: Mukul Tikekar, Dr Anandroop Bhattacharya PRASANNA S GANDHI [email protected] What is packaging? Service and art of providing a suitable environment to the electronic/ MEMS product as a whole to perform reliably over a period of time To protect delicate components from structural damage and/or malfunctions No addition to functionalityPRASANNA S GANDHI [email protected] 1 Motivation MEMS packaging is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications Packaging is aaveryverylarge percentage of the total cost of MEMS devices MEMS packikaging iiissaaltlmost alllways app licati on specific and greatly affected by its environment and packaging techniques We will first have a look at electronic packaging and then MEMS PRASANNA S GANDHI [email protected] Electronic Packaging Levels of Packaging Edge connector Wafer Chip Printed circuit board Chip Carrier Back panel Chassis PRASANNA S GANDHI [email protected] 2 Level – I Packaging: Chip to Chip Carrier Chip carrier – Housing for the thin and fragile chip Purpose – Protects the chip from environment and abusive handling – Facilitates interconnections from the chip to the pads/holes on the circuit board – Provides pins/pads for that serve as bases for solder joints – Also involved in the heat transfer process as the first step in the heat flow path from source to sink PRASANNA S GANDHI [email protected] Chip carrier Lid Bond wires Case Leads Chip Pins Bond Lead frame Parts of Chip Carrier – Chip Many different chip carriers exist today ––CaseCase but they all more or less conform to this – Leads and lead frame parent structure – Chip to package bond ––BondingBonding wires ––LidLid PRASANNA S GANDHI [email protected] 3 Key design features of a chip carrier I/O count – Modern VLSI or ULSI chips have thousands of gates thereby requiring large number of I/Os – MEMS may or may not have (ex micromirror device vs pressure sensor device) Hermeticity – Ensures reliable operation – Entry of moisture is avoided - can cause corrosion of pins, wires – Organic materials that outout--gasgas (release volatiles) with time are not used Heat Dissipation – Modern circuitry result in very high heat fluxes Additional MEMS devicePRASANNA S specificGANDHI [email protected] requirements may be there Types of chip carriers Based on materials Based on I/O – Plastic ––PeripheralPeripheral ––CeramicCeramic – Area Array – Flip chip Based on connections – Through hole – Surface Mount PRASANNA S GANDHI [email protected] 4 Types of leads Chip carri er Chip carri er Leads Printed circuit Leads Printed circuit board board Pin-in-hole Gull wing type leads Chip carrier Leads Printed circuit board PRASANNA S GANDHI [email protected] J type leads Plastic vs. Ceramic chip carriers Ceramic cases Plastic cases High Cost Low Cost Usedfd for pro ducts wit h UdfUsed for pro dtducts w ith – Higher I/O count ––LowLow powers ––StringentStringent hermeticity – Moderate I/O count requirements ––LenientLenient hermeticity requirements Bonding material –Eutectic– Eutectic Direct bonding may lead to solder of gold and silicon severe thermothermo--mechanicalmechanical ––InorganicInorganic ––doesdoes not release stresses volatiles – CTE mismatch between Si – Melting point is 390390ººCC (4 ppm/K)ppm/K) and plastic (80 – Thermal conductivity is 296 ppmppm/K)/K) W/mW/m--KK – Problem circumvented by – Aids in heat transfer from introduction of lead frame made of copper chip to case PRASANNA S GANDHI [email protected] 5 Dual Inline Package (DIP) .280 .325 .240 .300 First package (invented in 1 1960s) 1.020 .925 .060 – Both plastic and ceramic .015 .210 MAX – Fully encapsulated .015 MIN 0.1 .022 – Pins inserted in holes .014 .015 Attached to the underside of .006 the board by wave soldering .3 Advantages Disadvantages ¾ Robust pins and connections ¾ Poor area efficiency ¾ Automated assembly – pick ¾ Limited wireability and place machines ¾ Limited I/O count (100 ¾ Width of pins is increased mil pitch) near the body – provides a shoulder PRASANNA S GANDHI [email protected] Other Peripheral Packages -SMT- SMT Small Outline Package (SOP) – WellWell--suitedsuited to 24 – 48 pin memory with space constraints – Similar to DIP with copper lead frames Quad Flat Pack (QFP) – Plastic and ceramic – Lead frames go around the entire periphery – Higher pin counts (up to 300) – Ther e is a p u sh fo r thin QFPs o r TQFP fo r po rtable PCs – Ceramic QFPs are used for higher temperature or humid applications – Handling problems – only connections on one side are made simultaneously PRASANNA S GANDHI [email protected] 6 Peripheral packages Dual in Line Package (DIP) Small Outline Package (SO) PRASANNA S GANDHI [email protected] Quad Flat Pack (QFP) Area Array Packages Utilizes the entire bottom side of the carrier for interconnections instead of only the perimeter. Since area available is higher, it is possible to have – Higher I/O count – Increased lead pitch Ball Grid Array Land Grid Array Pin Grid Array PRASANNA S GANDHI [email protected] (BGA) (LGA) (PGA) 7 Packaging Efficiency Packaging efficiency is defined as Effici Type Area IC size ency Efficiency= 30 mm Package size QFP 900 mm2 11% 20 mm TAB 400 mm2 13% Examples: – DIP: 2% 15 mm ––QFP:QFP: 5% COB 225 mm2 25% ––BGA:BGA: 3030--80%80% CSP 115 mm2 44% – Bare chip: 100% 10 mm Flip chip 100 mm2 100% PRASANNA S GANDHI [email protected] 1st level connections Automated wire bonding – Thermo compression ––UltraUltra sonic – Thermo sonic Tape automated bonding Flip chip bonding PRASANNA S GANDHI [email protected] 8 Scanner Sensor Think Whats inside this Chip Wire Bonding inside chip Lens Wire bonding Wirebonding is an electrical interconnection technique using thin wire and a combination of heat, pressure and/or ultrasonic energy. Wireb ondi ng is a solid ph ase weldi ng process, wh ere th e t wo metallic materials (wire and pad surface) are brought into intimate contact. Once the surfaces are in intimate contact, electron sharing or interdiffusion of atoms takes place, resulting in the formation of wirebondwirebond.. Process Pressure Temperature (C) Ultrasonic Energy Wire Pad Thermo-compression High 300-500 No AuAl, Au Ultrasonic Low 25 Yes Au, Al Al, Au Thermosonic Low 100-150 No Au Al, Au Two basic wirebonding methods: Ball bonding PRASANNA S GANDHI [email protected] Wedge Bonding 9 Ball Bonding Components Connection pad ––WireWire – Capillary Bonding pad – Electronic Flame Off (EFO) Chip system ¾ Temperature range is 100-500°C Clamp ¾ Fine gold wire (75μ) normally used ¾ used where the pad pitch is greater than 100μ PRASANNA S GANDHI [email protected] Flip Chip Technology Bare semiconductor chips are turned upside down and bonded directly into the motherboard or chip carrier First introduced by IBM in 1962. – Path breaking technology invention – Introduced for ceramic substrates – Converted in 1970 to C4 (Controlled Collapse Chip Connection) for ICs – Initially used for peripheral packpackagesages but quickly progressed to area array Why use Flip Chip? – Small size Reduced board area,,g,g less height, lesser weight – Improved performance – high speed Eliminating bond wires reduces the delaying inductance and capacitance Shortens the path by a factor of 25 to 100 – Great I/O flexibility – Rugged With ““underfillunderfill”,”, flip chips behave like small blocks of cured epoxy ––LowLow cost PRASANNA S GANDHI [email protected] 10 Flip Chip: Solder Bumps and Underfill Heat transfer Solder bumps – Electrical connections Underfill ––ThermalThermal path L Chip – Holds chip/die and substrate together Pa y α x Pi Pa h Underfill SubstrateSubstrate – needleneedle--dispenseddispensed along the edges of each chip S – drawn into the underunder--chipchip space by capillary action Solder bump ––heatheat--curedcured to form a permanent bond Why is underfill required? – compensate for any thermal expansion difference between the chip and the substrate - mechanically "locks together" chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps. – protects the bumps from moisture or other environmental hazards – provides additional mechanical strength to the assembly PRASANNA S GANDHI [email protected] UnderfillUnderfill:: Various Ways Underfill L Reservoir Chip Pa y α x Pi Pa h SubstrateSubstrate S Capillary Flow L Chip y injectio n Pi x Pa h Chip Placement Motion Substrate S Solder or Adhesive Bumps Injection Flow Area Array Format Chip Polymer Underfill Flow Front Circuit Traces Substrate Compression Flow PRASANNA S GANDHI [email protected] 11 COMPARISON ––MEMSMEMS & IC Packaging z The goal of IC ppggackaging is to z Provide physical support for the chip z Provide an electrical interface to active chips in the system supply signal, power, and ground interconnections z Provide Heat dissipation z Effectively isolate the chip physically from its environment. z MEMS devices on the other hand are application specific and often are intimately interfaced with their environment for sensing, interconnection, and/or actuation. PRASANNA S GANDHI [email protected] COMPARISON – MEMS & IC Packaging Packaging of MEMS Pressure sensor Lid Bond wires Lead s Chip Bond Lead frame shows a comparison between a typical DIP IC package and a MEMS pressure sensor package, which has an opening to sense pressure variation. PRASANNA S GANDHI [email protected] 12 COMPARISON – MEMS & IC Packaging Items MEMS package IC package Standardization NO YES Process Flow Application Standardization driven Packaging & 20 ~95% 10 ~25% Testing cost Environmental Needed Isolation compatibility Packaging Type Diverse Similar PRASANNA S GANDHI [email protected] Wun-Yan Chen ,Industrial Technology Research Institute CHALLENGES IN MEMS PACKAGING Issues: Release and Stiction:Stiction: when to release devices? Dicing may lead to contamination Dicing Die Handling Stress Outgassing Testing Operation in harsh environments: vibrations, chemicals, salt water etc.
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