Lecture 20: Packaging MEMS
ME 645: MEMS: Design, Fabrication and Characterization
P.S. Gandhi Mechanical Engineering IIT Bombay Acknowledgements: Mukul Tikekar, Dr Anandroop Bhattacharya PRASANNA S GANDHI [email protected]
What is packaging?
Service and art of providing a suitable environment to the electronic/ MEMS product as a whole to perform reliably over a period of time To protect delicate components from structural damage and/or malfunctions
No addition to functionalityPRASANNA S GANDHI [email protected]
1 Motivation
MEMS packaging is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications
Packaging is avery a verylarge percentage of the total cost of MEMS devices
MEMS packikaging iiissaaltlmost alllways app licati on specific and greatly affected by its environment and packaging techniques We will first have a look at electronic packaging and then MEMS PRASANNA S GANDHI [email protected]
Electronic Packaging Levels of Packaging Edge connector Wafer
Chip Printed circuit board
Chip Carrier
Back panel
Chassis
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2 Level –I Packaging: Chip to Chip Carrier
Chip carrier – Housing for the thin and fragile chip
Purpose – Protects the chip from environment and abusive handling – Facilitates interconnections from the chip to the pads/holes on the circuit board – Provides pins/pads for that serve as bases for solder joints – Also involved in the heat transfer process as the first step in the heat flow path from source to sink
PRASANNA S GANDHI [email protected]
Chip carrier Lid Bond wires
Case Leads Chip
Pins Bond Lead frame
Parts of Chip Carrier – Chip Many different chip carriers exist today ––CaseCase but they all more or less conform to this – Leads and lead frame parent structure – Chip to package bond ––BondingBonding wires ––LidLid PRASANNA S GANDHI [email protected]
3 Key design features of a chip carrier
I/O count – Modern VLSI or ULSI chips have thousands of gates thereby requiring large number of I/Os – MEMS may or may not have (ex micromirror device vs pressure sensor device) Hermeticity – Ensures reliable operation – Entry of moisture is avoided - can cause corrosion of pins, wires – Organic materials that outout--gasgas (release volatiles) with time are not used Heat Dissipation – Modern circuitry result in very high heat fluxes
Additional MEMS devicePRASANNA S specificGANDHI [email protected] requirements may be there
Types of chip carriers Based on materials Based on I/O – Plastic ––PeripheralPeripheral ––CeramicCeramic – Area Array – Flip chip Based on connections – Through hole – Surface Mount PRASANNA S GANDHI [email protected]
4 Types of leads
Chip carri er Chip carri er Leads Printed circuit Leads Printed circuit board board
Pin-in-hole Gull wing type leads
Chip carrier Leads Printed circuit board
PRASANNA S GANDHI [email protected] J type leads
Plastic vs. Ceramic chip carriers
Ceramic cases Plastic cases High Cost Low Cost Usedfd for pro ducts with UUdfsed for prod dtucts with – Higher I/O count ––LowLow powers ––StringentStringent hermeticity – Moderate I/O count requirements ––LenientLenient hermeticity requirements Bonding material –Eutectic– Eutectic Direct bonding may lead to solder of gold and silicon severe thermothermo--mechanicalmechanical ––InorganicInorganic ––doesdoes not release stresses volatiles – CTE mismatch between Si – Melting point is 390390ººCC (4 ppm/K)ppm/K) and plastic (80 – Thermal conductivity is 296 ppmppm/K)/K) W/mW/m--KK – Problem circumvented by – Aids in heat transfer from introduction of lead frame made of copper chip to case PRASANNA S GANDHI [email protected]
5 Dual Inline Package (DIP)
.280 .325 .240 .300 First package (invented in 1 1960s) 1.020 .925 .060 – Both plastic and ceramic .015
.210 MAX – Fully encapsulated .015 MIN 0.1 .022 – Pins inserted in holes .014 .015 Attached to the underside of .006 the board by wave soldering .3
Advantages Disadvantages ¾ Robust pins and connections ¾ Poor area efficiency ¾ Automated assembly – pick ¾ Limited wireability and place machines ¾ Limited I/O count (100 ¾ Width of pins is increased mil pitch) near the body –provides a shoulder PRASANNA S GANDHI [email protected]
Other Peripheral Packages -SMT- SMT
Small Outline Package (SOP) – WellWell--suitedsuited to 24 –48 pin memory with space constraints – Similar to DIP with copper lead frames
Quad Flat Pack (QFP) – Plastic and ceramic – Lead frames go around the entire periphery – Higher pin counts (up to 300) – Ther e is a p ush fo r thin QFPs o r TQFP fo r po rtable PCs – Ceramic QFPs are used for higher temperature or humid applications – Handling problems – only connections on one side are made simultaneously
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6 Peripheral packages
Dual in Line Package (DIP) Small Outline Package (SO)
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Area Array Packages
Utilizes the entire bottom side of the carrier for interconnections instead of only the perimeter. Since area available is higher, it is possible to have – Higher I/O count – Increased lead pitch
Ball Grid Array Land Grid Array Pin Grid Array PRASANNA S GANDHI [email protected] (BGA) (LGA) (PGA)
7 Packaging Efficiency
Packaging efficiency is defined as Effici Type Area IC size ency Efficiency= 30 mm Package size QFP 900 mm2 11%
20 mm TAB 400 mm2 13% Examples:
– DIP: 2% 15 mm ––QFP:QFP: 5% COB 225 mm2 25% ––BGA:BGA: 3030--80%80% CSP 115 mm2 44% – Bare chip: 100% 10 mm Flip chip 100 mm2 100%
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1st level connections
Automated wire bonding – Thermo compression ––UltraUltra sonic – Thermo sonic Tape automated bonding Flip chip bonding
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8 Scanner Sensor
Think Whats inside this Chip
Wire Bonding inside chip
Lens
Wire bonding
Wirebonding is an electrical interconnection technique using thin wire and a combination of heat, pressure and/or ultrasonic energy. Wireb ondi ng is a solid ph ase weldi ng process, wh ere th e t wo metallic materials (wire and pad surface) are brought into intimate contact. Once the surfaces are in intimate contact, electron sharing or interdiffusion of atoms takes place, resulting in the formation of wirebondwirebond..
Process Pressure Temperature (C) Ultrasonic Energy Wire Pad
Thermo-compression High 300-500 No AuAl, Au
Ultrasonic Low 25 Yes Au, Al Al, Au
Thermosonic Low 100-150 No Au Al, Au
Two basic wirebonding methods: Ball bonding PRASANNA S GANDHI [email protected] Wedge Bonding
9 Ball Bonding
Components Connection pad ––WireWire – Capillary Bonding pad – Electronic Flame Off (EFO) Chip system
¾ Temperature range is 100-500°C Clamp ¾ Fine gold wire (75μ) normally used ¾ used where the pad pitch is greater than 100μ PRASANNA S GANDHI [email protected]
Flip Chip Technology
Bare semiconductor chips are turned upside down and bonded directly into the motherboard or chip carrier First introduced by IBM in 1962. – Path breaking technology invention – Introduced for ceramic substrates – Converted in 1970 to C4 (Controlled Collapse Chip Connection) for ICs – Initially used for peripheral packpackagesages but quickly progressed to area array Why use Flip Chip? – Small size Reduced board area,,g,g less height, lesser weight – Improved performance –high speed Eliminating bond wires reduces the delaying inductance and capacitance Shortens the path by a factor of 25 to 100 – Great I/O flexibility – Rugged With ““underfillunderfill”,”, flip chips behave like small blocks of cured epoxy ––LowLow cost PRASANNA S GANDHI [email protected]
10 Flip Chip: Solder Bumps and Underfill Heat transfer Solder bumps – Electrical connections Underfill ––ThermalThermal path L Chip – Holds chip/die and substrate together Pa y α
x Pi Pa h Underfill SubstrateSubstrate – needle- needle-dispenseddispensed along the edges of each chip S – drawn into the underunder--chipchip space by capillary action Solder bump ––heatheat--curedcured to form a permanent bond
Why is underfill required? – compensate for any thermal expansion difference between the chip and the substrate - mechanically "locks together" chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps. – protects the bumps from moisture or other environmental hazards – provides additional mechanical strength to the assembly PRASANNA S GANDHI [email protected]
UnderfillUnderfill:: Various Ways
Underfill L Reservoir Chip Pa y α
x Pi Pa h SubstrateSubstrate S Capillary Flow L Chip y injectio n Pi x Pa h Chip Placement Motion Substrate S
Solder or Adhesive Bumps Injection Flow Area Array Format Chip Polymer Underfill Flow Front Circuit Traces Substrate Compression Flow
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11 COMPARISON ––MEMSMEMS & IC Packaging
z The goal of IC ppggackaging is to
z Provide physical support for the chip z Provide an electrical interface to active chips in the system supply signal, power, and ground interconnections z Provide Heat dissipation z Effectively isolate the chip physically from its environment.
z MEMS devices on the other hand are application specific and often are intimately interfaced with their environment for sensing, interconnection, and/or actuation.
PRASANNA S GANDHI [email protected]
COMPARISON – MEMS & IC Packaging
Packaging of MEMS Pressure sensor
Lid Bond wires
Lead s Chip
Bond Lead frame
shows a comparison between a typical DIP IC package and a MEMS pressure sensor package, which has an opening to sense pressure variation.
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12 COMPARISON – MEMS & IC Packaging
Items MEMS package IC package Standardization NO YES Process Flow Application Standardization driven Packaging & 20 ~95% 10 ~25% Testing cost Environmental Needed Isolation compatibility Packaging Type Diverse Similar
PRASANNA S GANDHI [email protected] Wun-Yan Chen ,Industrial Technology Research Institute
CHALLENGES IN MEMS PACKAGING
Issues: Release and Stiction:Stiction: when to release devices? Dicing may lead to contamination Dicing Die Handling Stress Outgassing Testing Operation in harsh environments: vibrations, chemicals, salt water etc.
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13 DICING
Dicing the wafer into individual dice is amajor a major chllhallenge iiin MEMS packikaging. It iiis tilltypically done with adiamond a diamond sawsaw.. ––RequiresRequirescoolant flow along with silicon and diamond particles – Contaminants can get into the crevices of the features, causing the devices to fail
Alternati ve Sol utions : – Wafer cleaving. ––LaserLaser Sawing. – Wafer Level encapsulation before separating devices
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WAFER LEVEL ENCAPSULATION
In wafer level enca pp,sulation, capping wafer is bonded to the top of aadevicedevice wafer which eliminates the need for special die handling fixturesfixtures..
High temperature ((10001000 °CC))requiredrequired for direct bondingbonding..GlassGlassfrit or anodic bonding (500 (500 °CC))isis used more commonly but it may cause stressstress..
However, WLE is unique to semiconductor sensor packaging and adds considerable cost to the sensor die because of the added fabrication steps and increased die areaarea..
PRASANNA S GANDHI [email protected]
14 DIE HANDLING
Die handling is currently not meeting the requirements of MEMS
Because of the delicate surface features, MEMS chips cannot be moved using vacuum pickpick--upup heads
MEMS dice must be picked up and handled by the edges which is more difficult than by the top surface because of greatly reduced surface area and increased dexterity requirements of the pickpick--andand--placeplaceequipment Stringent requirements on vibration levels during handling PRASANNA S GANDHI [email protected]
OUTGASSING
When epoxies or cyanate esters are used for die attach, they out gas as they curecure..
The water and organic vapors may then redeposit on the features, in crevices, and on bond pads. pads.
This leads to device stiction and corrosion. corrosion.
Possible solutions to outgassing challenges include – Very low outgassing die attach materials ––RemovalRemovalof outgassing vapors during die attach curing ––LowLow Young’s Modulus solders
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15 TESTING
The major problem with testing is with applying nonnon--electricelectricstimuli to the devicesdevices..
Currently the only way for testing is to test the packaged chip but this is too expensive and time consumingconsuming..
A feasible solution is to test all that is possible using waferwafer--scalescaleprobing, and finish with cost effective, specially modified test systems
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New Topic: Design and analysis of MEMS Analysis Static analysis: thermal stresses and deflection Dynamic analysis: vibration analysis MDOF Fluid mechanics and heat transfer Correlation measured quantity to electrical signal depending on sensing method Signal conditioning and processing Automatic control Special physics coming at MEMS scale: ex. Electrostatic actuation, squeeze film damping, electrowettingelectrowetting,, optics related, and so on… PRASANNA S GANDHI [email protected]
16 Basic Stress Analysis A lot of use of flexures is carried out for MEMS designs Standard Euler-Euler-BernoulliBernoulli beam theory (thin slender beam) is mostly sufficient; assuming that you are all familiar with the same. Basic equation M E σ d 2 y = = M = EI I R y dx2 PRASANNA S GANDHI [email protected]
Basic Stress Analysis Coupling of stress analysis with actuation forces say electrostatic actuation
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17 Analysis of Pressure Sensor Basis: thin diaphragm formulation . Equations b ⎛ ∂2 ∂2 ⎞⎛ ∂2w ∂2w⎞ p a p x ⎜ + ⎟⎜ + ⎟ = ⎜ 2 2 ⎟⎜ 2 2 ⎟ ⎝ ∂x ∂y ⎠⎝ ∂x ∂y ⎠ D Eh3 D = y 12(1−ν 2 ) z Use fixed-fixed-fixedfixed boundary conditions to get the solution: quite tedious task PRASANNA S GANDHI [email protected] analytically
Analysis of Pressure Sensor Circular diaphragm Max deflection in center 3W(m2 −1)a2 w = − max 16πEm2h3 Max radial stress and max hoop stress at eddge: 3W 3νW (σ ) = (σ ) = rr max 4πh2 θθ max 4πh2 W = (πa2 )p m =1/ν
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18 Analysis of Pressure Sensor Rectangular diaphragm a Max deflection in center pb4 x w = −α b max Eh3 Max stress pb2 y (σ ) = β yy max h2
a/b 1 1.2 1.4 1.6 1.8 2.0 ∞ α 0.0138 0.0188 0.0226 0.0251 0.0267 0.0277 0.0284
β 0.3078 0.3834PRASANNA 0.4356 S GANDHI 0. [email protected] 0.4872 0.4974 0.5
Pressure Sensor: Example
ExampleExample:: Rectangular diaphragm has dimensions a = 752micron and b = 376 microns. Thickness of diaphragm is 13.9 micron and pressure applied is 20MPa. Material is Si with yield strength = 7000MPa and E = 190,000MPa v=0.25. Determine maximum stress and deflection. Will the diaphragm be safe under this loading? If the circular diaphragm of the same area is used with same thickness, will it be safe?
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19 Thank You
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