Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic Metal Bonding of Wafers Is Used in Advanced MEMS Packaging and 3D Integration Technologies

2008 . Issue July

Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic metal bonding of wafers is used in advanced MEMS packaging and 3D integration technologies. A unique feature of eutectic metals is the melting of the solder like alloys that facilitate surface planarization and provide a tolerance to surface topography and particles. Advanced wafer level bonding using 2-3um thick metal layers allows precision alignment preventing the aberrant viscous flow of the metal and wafer slippage.

Also in this issue: • C4NP Next Generation Wafer Bumping Page 2 index

3 The Age of 3D Integration 12 Application Notes Wilfried Bair Tips to Get The Most Out Vice President Strategic Business Development, of Data Viewer SUSS MicroTec Sumant Sood, SUSS MicroTec

4 C4NP Next Generation Wafer 13 New Office in USA Bumping Anton Wolejnik, Managing Director, SUSS MicroTec Changing bumping requirements driven by 3D Packaging Klaus Ruhmer and Emmett Hughlett, 14 Clif´s Notes SUSS MicroTec You Can Define That Exposure Dose In One Wafer! 6 Precision Wafer to Wafer Clifford J. Hamel, Packaging Using Eutectic SUSS MicroTec Metal Bonding Shari Farrens, Ph.D. and Sumant Sood, SUSS MicroTec 18 SUSS in the News

20 Tradeshows/Conferences

SUSS Scores First Place for 10th Year as Material Handling Supplier Page 3 Full View

The Age of Integration 3D When commercial wafer bonders processes. A commonly used com- were first introduced to the industry parison of 3D integration with real in the early 90’s the main driver for estate illustrates that when silicon this new equipment type was the space is at a premium or cannot be then emerging MEMS technology. made larger the only logical conclu- Pressure sensors and accelerome- sion is to expand constructions into ters for automotive applications set the third dimension. off on its booming track providing the first volume market opportunity Thus 3D integration technologies for wafer bonding in large quantities. allow for an alternate path to Moore’s Since the early 60’s and until then the law. This is now commonly referred mechanical use of silicon was mainly to as “More than Moore” and shows limited to high performance, but low that the continuous scaling of tran- Wilfried Bair volume applications in aerospace. sistors by doubling approximately Vice President every two years can be pursued by Strategic Business Development, The second phase in wafer bon- stacking devices. SUSS MicroTec ding is hallmarked by the growing demand for MEMS devices in con- To address this new market op- sumer electronics providing new and portunity novel equipment approa- unique product features to a vast ches are required to provide submi- mass of insatiable consumers. From cron alignment accuracy for 300mm MEMS microphones to accelerome- wafers for the full product range of ters being used in game consoles like lithography and wafer bonding tools. the Nintendo Wii MEMS continued to The product and process develop- penetrate and influence the appetite ment teams within SUSS MicroTec of the consumer world. The latest have worked on a new and unique “MEMS publicity stunt” was Apple’s set of tools to address this upcoming announcement of the 2nd generation challenge. Millions of connections iPhone. Describing the latest unique per stacked device will be dedicated features of the iPhone the use of to the use of metal bond processes (MEMS) accelerometers and smart with alignment accuracies in order sensors was prominently shown on to match the roadmaps of the con- the supplier’s website. tinuously shrinking Through Silicon Via (TSV) sizes down to interconnect Now we are looking at the third pitches of 3 microns and less. and - what we expect to be - the largest surge in demand for wafer We are approaching the age of 3D bonding applications: We are ap- integration – in fact, we are already proaching the age of 3D integration there. And SUSS is right ahead to of semiconductor devices. The en- help our customers maximize their visioned plan for the 3D integration wafer’s real estate. And maximize includes logic, memory, mixed signal, their profit. As their success is our image sensor and almost all other success. commercially viable semiconductor Page 4 - C4NP – Next Generation Wafer Bumping -

Klaus Ruhmer, Sales & Marketing C4NP, and Emmet Hughlett, VP and Business Unit Manager C4NP, SUSS MicroTec

Solder bumps were invented almost or in-situ reflow, the solder volume materials has shown to be the primary half a century ago – an eternity in to- transforms into a solder sphere due driver for cost, reliability and electrical day’s world of micro electronics. The to surface tension. That solder sphere performance. technology has not stood still and many is then used to connect to the outside One key advantage of IBM’s C4NP advances have been made in the ar- world. Depending on the type of pack- is it’s capability to put bumps on es- eas of solder and UBM (Under Bump age, that may either be to an interme- sentially any UBM material as long as Metallurgy) materials, solder deposition diate substrate (Flip Chip in Package it wets to solder. As previously reported techniques and equipment technology. FCiP) or to the board itself (Wafer Level in this publication, C4NP also tackles The basic principle however remained Chip Scale Package WLCSP). other classical bumping challenges and unchanged: A UBM feature is created enables environmentally friendly, low- on open pads of a semiconductor chip. SUSS MicroTec has played a key cost, fine pitch bumping using a variety 50um pitch, lead- A specific volume of solder is deposited role in Wafer Bumping since its infancy. of lead-free solder alloys. With C4NP, free solder bumps (Courtesy of IBM) on top of the UBM. During subsequent SUSS Mask Aligners and coat/develop pure bulk solder is molten and injected cluster systems are ideally suited for the into prefabricated glass molds. These specific requirements related to pattern- molds contain etched cavities mirror- ing the UBM and the resist and polymer ing the bump pattern of the wafer. Once layers for subsequent metal deposition. the molds are filled, all solder bumps are transferred in one step onto the wafer. Advanced packaging techniques in- The process is quite simple and doesn’t cluding 3D packaging utilizing solder use any liquid flux. That makes it a low bumps as the primary interconnect- cost, high yield and fast cycle time so- technology have been growing at an lution for bumping with a wide variety impressive pace since the mid 1990’s. of high performance lead free solders. Ever higher interconnect density needs In addition, this process also eliminates combined with increasing performance the need for toxic chemicals needed for requirements are no longer a match for alternative bumping techniques – C4NP existing interconnect technologies such is truly a “Green Technology”. as wire bonding. Besides the solder bump itself how- Unlike other solder deposition pro- ever, the selection of the appropriate cesses, C4NP is independent of the UBM or BLM (Ball Limiting Metallurgy) UBM materials used. It offers full flex- Page 5 - C4NP – Next Generation Wafer Bumping -

Klaus Ruhmer Klaus Ruhmer has global Sales & Marketing responsibility for C4NP wafer bumping technology at SUSS MicroTec. He has been with SUSS since 1998 starting out as an Applications Engineer for wafer bonding and lithography products. Over the years, he has held various technical and sales related positions within SUSS. Prior to his current position, Klaus was responsible for Strategic Accounts in North America. Klaus is a native Austrian and holds a BS in Electronics and Telecommunica- tions Technology. He worked in software development before he moved to the 3D - Stacked chips using C4NP micro-bumps US and joined the semiconductor indus- (Courtesy of IBM) try in 1996. ibility to combine the proper UBM with the right solder alloy Emmett Hughlett to not only fit the application but also meet cost and perfor- is Vice President and C4NP Business mance requirements of the final package. Unit Manager with SUSS MicroTec. Emmett holds a Ph.D. in electrical en- Besides the need for lead-free, future solder bumps are gineering. Emmett‘s career includes also driven by 3D packaging and integration requirements. 24 years of engineering, sales and 3D requires fine pitch bumping capability to accommodate management in the semiconductor very high interconnect density. equipment industry, with both Kulicke & Soffa Industries and SUSS MicroTec More information about SUSS MicroTec’s Inc. wafer bumping and advanced packaging solutions can be found on www.suss.com. Page 6 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

Abstract PRECISION Eutectic metal bonding of wafers is used in advanced MEMS packaging and 3D integration technologies. A unique feature of eutectic metals is the melting of the solder WAFER TO WAFER like alloys that facilitate surface planarization and provide a tolerance to surface topography and particles. Often it is assumed that the alignment in eutectic metal bonding is PACKAGING compromised from the liquid phase transition and precision alignment is not possible. This is not true in advanced wafer level bonding using 2-3um thick metal layers. Precision control of bonding force and temperature prevent the aberrant USING EUTECTIC viscous flow of the metal and prevent wafer slippage. Keywords: Eutectic bonding, wafer bonding, MEMS packaging, Au-Sn, Au-Si, Cu-Sn. METAL BONDING

Shari Farrens, Ph.D., Chief Scientist, and Co-Author Sumant Sood, Sr Application Engineer, SUSS MicroTec

INTRODUCTION Hermetic packaging of sensors has historically been achieved with glass frit and anodic bonding techniques. However, these techniques are pres- ently limiting scaling of devices and are not appropriate for integration plans for CMOS compatible MEMS. The widespread use of glass frit bonding can be attributed to its tolerance to particles and surface topography, hermetic quality of the seals, and inexpensive processing costs. In com- parison, eutectic alloys provide better hermeticity levels, are equally tolerate to roughness and particles and enable device scaling and integration.

EUTECTIC REACTIONS A eutectic reaction is a triple point Figure 1: in a binary phase diagram in which the Au-Si Binary Phase Diagram liquid metal solidifies into a solid alloy without going through a two phase, sol- of phases in the alloy is not fully alloys of Au and Si will consist of a two id + liquid equilibrium region. Because achieved. The morphology of the grains phase mixture of α and β. When an al- the solidification is immediately realized within the eutectic solid are very small loy of 2.85wt Si is heated the solid will Table 1: Eutectic Alloys used the atomic rearrangements necessary and best described as “feather-like”. immediately turn to liquid above 363C in MEMS Packaging to establish the equilibrium distribution This fine grained interdigitated structure avoiding both the α+liquid and β+liquid is extremely rigid and strong. The fine two phase regions. Alloy Eutectic Eutectic grain size limits interdiffusion and cor- Temperature Composition rosion. MATERIALS SYSTEMS Al-Ge 419 C 49/51 wt% Figure 1 is the phase diagram for There are several alloys choices Au-Ge 361 C 28/72 wt% Au-Si. This phase diagram is a classic based on Cu or Au eutectic metallur- Au-In 156 C 1/99 wt% eutectic example in which the pure gies. Table 1 shows the commonly used fcc Au phase is denoted as and alloys along with the eutectic composi- Au-Si 363 C 97/3 wt% α the pure silicon diamond cubic phase tions and the eutectic temperature. Au-Sn 280 C 20/80 wt% is β. The diagram shows that there is All of these alloys have been used in Cu-Sn 231 C 1/99 wt% very little miscibility in either Au or Si and MEMS packaging, or optical MEMS. Page 7 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

The Al-Ge system is also applicable to Figure 2: Formic acid vapor ternary eutectic reactions between Al cleaned Cu surface and SiGe layers because Al forms a bi- before and after nary eutectic reaction with both Si and heating to 400 C. Ge. This system is particularly CMOS friendly.

DEPOSITION TECHNIQUES There are two fundamental methods for creating a eutectic seal. The first method involves deposition of pure materials which then are diffused together until the eutectic composition is reached. Then the eutectic alloy can be melted and reflowed to achieve the seal. By contrast the binary alloy can be SURFACE PREPARATION spun dry. Then the wafer was heated deposited as a single layer already at The diffusion of metals as well as to 400 C to see if reoxidation would the composition necessary to achieve the solidification of eutectic phases is occur. It does not and this method is a eutectic reaction. inhibited by contamination and oxide used for Cu-Cu bonding in 3D integra- Figure 3: layers. In most fabrication facilities the tion technology. Position of optics for Eutectic alloys can be plated, sput- timing of the device wafer and cap wa- wafer to wafer bond tered or evaporated onto the sub- fer process are such that one or the alignment. strates. There are several sources other set of substrates may be queued for alloy sputter targets that are ide- up for bonding before the other. This ally suited to thin layer deposition and delay time between deposition of metal many of the alloys can be electroplated layers and actual bonding can lead at eutectic compositions. Because the to surface oxidation. To achieve high quality of the electrical connections, yields and reproducible lots, point of Bottom Side Alignment as well as the reaction kinetics, are use surface preparation is advised to with Transparent Wafer adversely affected by impurities the make sure that metal layers are clean deposition should be done as clean just prior to bonding. as possible. Incorporation of oxygen Based on experience in die-to-die and other gases in the thin films during and C4NP advanced bumping tools it deposition can lower the diffusion rates has been established that formic acid dramatically as will impurities from the vapor cleaning is very effective for most electroplating bath. eutectic alloys, low temperature solders, and aluminum as well as copper Bottom Side Alignment It is necessary to use adhesion layers in the removal of surface oxides. [2,3] with Digitized Image when using metal seal technologies. Vapor phase cleaning can be accom- The semiconductor surfaces or glass plished in batch processing or as a one surfaces should be properly cleaned to wafer at a time, point of use, cleaning. remove any previous photoresist layers In both cases the wafer(s) are placed in or other materials remaining from ear- a closed chamber or cleaning station. lier etching or patterning steps. Stan- The formic acid vapors are intro- dard substrate cleaning methods be- duced and the surfaces oxides are re- fore metal deposition include standard moved. The wafers are then rinsed in DI RCA1 and RCA2 or Piranha (sulfuric water and spun dry in the cleaning sta- acid, water and hydrogen peroxide). tion. In automated bond cluster tools IR Alignment To remove organics or to clean metal such as the SUSS MicroTec ABC200 surfaces dry plasma treatments have this is done with one or two wafers si- been effective. multaneously for increased throughput. The formic acid treatment passivates Typical adhesion layers include TiW, the surface of the metals and prevents TiN, W, Cr, Ni and vary with the sub- reoxidation during the rinse, dry and strate used. The adhesion layer is very alignment process that follows. Inter-Substrate important to ensure that the strength of Figure 2 shows a copper surface that Alignment the interface is not limited by thin film was cleaned with the formic acid vapor, delamination. rinsed with DI megasonic water and Page 8 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

ALIGNMENT TARGETS Alignment targets play an important role in achieving good quality bond alignment. In addition some target de- signs also facilitate process control and monitoring, For example, the alignment key shown in figure 4 contains both a standard cross and box style alignment key as well as graduated scales along the x- and y-axes. During process development the scales can be used to accurately determine systematic shifts Figure 4: and rotation that may occur during Male and female alignment keys with graduate the alignment or bonding steps. Note xand y- axis scales. that the graduated scales are used for analysis and not used for alignment. ALIGNMENT TECHNIQUES The standard male and female keys are Alignment techniques are separated used by the operator or the image rec- in to methods which align to live target ognition system for overlay alignment. images and those that use stored image Figure 5 shows an image of one of alignment. During live image alignment the keys after bonding. In this exam- the image of both the device and the ple the x-axis is perfectly aligned and cap wafer alignment keys are viewed the center of the graduated scales is simultaneously. This has the advantage aligned. On the y-axis verniers the pat- that throughout the alignment process tern is shifted slightly upwards and the any shifts that might occur because of first hash mark is aligned. If this were a vibration, clamping or other mechanical 0.5 μm vernier then the measurement motions can be observed and correct- would imply that at most the misalign- ed. With stored images once the posi- Figure 5: ment in this example is +/-0 μm in x and Post bond IR image of male and female tion of the initial fiducial is found and alignment keys in bonded silicon wafers. +0.5 μm in y. Verniers can be scaled to captured (digitally stored to memory) give 0.1, 0.2 or 0.5μm resolution de- the wafer is clamped into position and to live images. ISA also aligns to a live pending upon the desired precision presumed to be stationary during all image however, after bonding the mi- needed. remaining teps. However, this can not croscopes can not access the interface be verified since the target image is no again and are not useful for post bond BONDING TECHNIQUES AND longer in the field of view. analysis. The BSA method can be used KNOW-HOW The options for alignment techniques to verify the post bond alignment ac- Bonding of eutectic alloys requires include BSA (backside alignment) curacy because it is possible to “look good control over the temperature and with transparent substrates, BSA with through” the transparent substrate at pressure profiles in the bonder. This is opaque substrates, IR (infrared) align- any time during the align and bond pro- directly related to the melting of the alloy. ment, and ISA (intersubstrate) align- cess. This is also true for the IR method The viscosity of the alloy is related to ment. Figure 3 is a schematic of the whenever the metal layers do not ob- the temperature. As the melt becomes objective and substrate locations for scure the field of view of the target and hotter the molten metal is more fluid. each technique. The BAS w/ transpar- the wafers have a resistivity greater than With increased fluidity come the pro- ent substrates and the IR method align 0.01 Ohm-cm (for silicon). pensity of the wafers to slide relative to one another and loose alignment accuracy. Another reason that temperature control is essential involves ensuring that all the locations on the wafer are melted. Many MEMS structures are fragile and care must be taken that when the applied force is used the interface is soft Figure 6: and fluid. If any areas contain solid met- Recipe al this will not be flattened by the ap- for Au-Sn eutectic plied force and the stress may damage bonding. underlying or surrounding structures. Page 9 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

The reaction time is generally short for eutectic bonds when the reaction is driven from melting an alloy layer. When the diffusion reaction is used the recipe may be lengthened by several minutes. Once the material is in the liquid state only a few minutes are required to equilibrate the composition and reflow the interface. Cooling can be done as rapidly as stress conditions in the device or sample will allow.

Figure 7: Hermeticity results from 14 Au-Si eutec- time from the wafer edge. Later genera- tic sealed devices from reference 5 and 6. tion equipment enabled the flags to be Equally important is the uniformity of pulled one at a time, however a funda- the applied force and the parallelism of mental problem still existed; if the wafer the bond chucks to the surface of the stack is pinned only in the center it is wafers. If the force is not applied di- still free to rotate about the z-axis. rectly perpendicular to the interface the In addition many times the center molten alloy will squeeze into unwanted pin causes harm to delicate dice in the areas and distortion of the bond lines center of the wafer. The solution is new will result. In extreme cases the molten control software that allows for only one alloy can be extruded in to the cavity or clamp to be lifted leaving the other two die structure and prevent device func- clamps available to confine the wafers tionality. in two locations along the edge of the In many applications the parts that wafer stack. After the first clamp is lifted are being bonded have cavities. To en- the spacer is removed and the clamp sure that the cavities are filled with the is put back down on the stack. Then proper atmosphere, separation flags the next clamp location is released still or spacers are used to maintain a gap leaving two locations pinned in position. between upper and lower substrates. This improved flag retraction method Spacers are thin shims of metal that are has been shown to reduce shifting by APPLICATIONS AND Figure 8: Sonoscan image of 6” placed between the wafers at three lo- seven times.[4] This method, called se- ReSULTs wafers bonded using cations. quential clamp removal is only possible Eutectic bonds are used for a variety Au-Si diffusion based The spacers range from 50-100 μm when there are at least three clamp of inertia devices such as accelerom- Eutectic bonds. in thickness and only penetrate the out- mechanisms on the bond fixture. eters, gyroscopes, and applications er most 2-3mm of the wafer perimeters. The bond recipe itself will resemble such as RF switches and resonators. A The spacers allow gases to be purged the example shown in figure 6. There recent publication presented a lengthy to and from the cavities throughout the may be some pump and purge cycles study of Au-Si eutectic bonded pres- interface via the vacuum pump system in the initial stages of the recipe to ex- sure sensors.[5,6] It is rare to find pub- in the bonder. Once the proper atmo- change the atmosphere inside the bond lished hermeticity data and these tests sphere is established within the cavities, chamber with one that is typically inert used encapsulated pirani gauges within the spacers must be removed prior to or reducing. Forming gas, hydrogen the device to monitor the leak rates of bringing the wafers in contact for final mixed with either nitrogen, argon or the seals over more than one year. The annealing. Removal of spacers has helium has been shown to dramatically study included several eutectic alloys been identified as a source of mechani- improve yield by suppressing oxidation and data in Figure 7 is for a diffused cal motion that can lead to shifting of and metal film contamination. The at- Au-Si eutectic bond showing excellent the substrates. mosphere also aids in heat transfer and results. Early generation bonders used an all is preferred to vacuum annealing unless Several examples of successfully at once removal methodology to retract the device requires vacuum sealing. bonded wafers are shown in figure the spacers. This was accomplished by The temperature as well as the force 8-11. Figure 8 shows an example of a using a center pin to come down from should be ramped in a controlled fash- Au-Si eutectic bond on 6” MEMS wa- the upper pressure plate and press ion. Force is used to establish physi- fers. This particular example was driven the wafers together in the center. This cal contract between the surfaces. By from a diffusion reaction and Sonoscan fixed the position of wafers together in gradually applying the force the metal acoustic imaging found no voids within the center only. Then the clamps were will flow between the wafers and remain the seal ring area. The blue in this figure lifted and the flags pulled out one at a confined to the pattern seal ring area. indicates a void free bond line. Page 10 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

Figure 9: The IR and acoustic image of 200mm wafers bonded using Au-Sn eutectic solder.

Another feature to point out is that requested alloy system in the demo fa- of the ceramic substrate the conformal the edge of the wafer is sealed. This cilities of Suss MicroTec. Shown in figure nature of a eutectic sealing technol- is very important if acoustic imaging is 9 is an example of the IR and Sonoscan ogy was a desired benefit of this bond used for void detection because when acoustic image of the bonded 200mm method. the edges of the wafer are not sealed, wafers. The dice were uniformly bonded The last example is a Au to SiGe capillary action will draw fluid into the at all locations within the wafer. eutectic bond. Whenever a eutectic areas between the die and complicated The gold tin system has also been forms between two binary phases it will post bond process flows. used on ceramic packages as shown in be possible to form a ternary eutectic Gold tin eutectics have been the most Figure 11. Due to the surface waviness phase as well if the remaining binary

Figure 10: system also has complete solubility Au to SiGe eutectic bond or exhibits a eutectic reaction. In the on 200mm silicon wafer. case of Au a simple eutectic exists be- Acoustic image shows no voids or unbonded tween Au-Si at 363C and 2.65wt% Si areas. and between Au-Ge at 419C and 28 at%Ge. Meanwhile, Si and Ge are completely miscible. In figure 11 we show a 200mm wafer bonded by eutectic alloy formation between Au and a SiGe alloy layer on silicon substrates. This process was completed at 420C. Because eutectic alloys melt and are therefore, self planarizing there is no need to CMP (chemical mechanical polishing) the metal layers. The wetting behavior of the alloy to its adhesion layer will assist with confinement of the molten flow as long as the force is applied gradually. This eliminates one of the costly processes normally associ- ated with metal bonds. Page 11 - Precision Wafer To Wafer Packaging Using Eutectic Metal Bonding -

CONCLUSIONS Eutectic alloy bonding is widely used in advanced packaging and MEMS device fabrication for hermetic seals. The processing temperatures of the various alloy choices are below 400C (except the Au-Ge system) and the selfpla- narization of the molten metal make this type of bond a very surface topography tolerant method. Alignment methods can include IR, intersubstrate alignment, or backside alignment. The accuracy of the aligned features depends on the choice of alignment method, quality of the targets and thickness of the alloy layer. However, for metal layers 1μm thick or less alignment accuracies of ~2 μm can be expected. It is expected that eutectic alloys will gradually replace some of the glass frit sealing technologies in applications that require device scaling to smaller packages and for integrated devices. The methods and materials systems described here should give some insight into what the possibilities can include. Figure 11: Ceramic packaging using Au-Sn eutectic bonds

References

1. Thaddeus B. Massalski, Binary Alloy Phase Diagrams, 2nd Edition, ASM International, Materials Park, Ohio, Vol. 1, 1990, p. 434.

2. Eric Laine, et.al., “C4NP – Reliability and Yield Data for Lead Free Wafer Bumping”, IMAPS Device Packaging Confe- rence, Doubletree Hotel, Scottsdale, March 17, 2007.

3. K. Ruhmer et al., “C4NP: Lead-Free and Low Cost Solder Bumping Technology for Flip Chip and WLCSP”, IWLPC Pan Pacific Conference Oct. 2006, Wyndham Hotel, San Jose, CA.

4. S. Farrens, “Processing Solutions for Reproducible Submi- cron 3D Integration”, 3D Architectures for Semiconductor Integration and Packaging Accessing Technological Deve- Dr. Shari Farrens Sumant Sood lopments, Applications, and Key Enablers, Oct 22-24, 2007, is the inventor of plasma activated is the Senior Applications Engi- Hyatt Regency San Francisco Airport Hotel, Burlingame, substrate bonding and holds sev- neer for Wafer Bonders at SUSS California. Proceedings to be published. eral patents for this enabling tech- Microtec Inc.. His recent experi- nology. Dr. Farrens has authored ence includes development of 5. Mei Y, Lahiji G R, Najafi K 2002” A Robust gold-silicon and co-authored over 100 pub- plasma enhanced wafer bonding eutectic wafer bonding technology for vacuum packaging”, lications on SOI, wafer bonding processes for SOI and strained Solid-State Sensor, Actuator and Microsystem Workshop, and nano-technology. With over silicon on Insulator (sSOI) applica- Hilton Head, SC, USA, pp. 772-4. 15 years of hands-on, worldwide tions. Sumant has authored and 6. Mitchell J S, Lahiji G R, Najafi K., “Reliability and characte- experience in academia and in- co-authored more than 15 papers rization of micropackages in a wafer level Au-Si eutectic dustry she is considered an ex- in wafer bonding, SOI, strained vacuum bonding process”, Proc., ASME/Pacific Rim Tech. pert on MEMS and wafer to wafer silicon and related areas. He re- Conf. Exhibit Integration and Packaging of MEMS, NEMS, bonding technologies. ceived his B.Tech in Electrical and Electronic Systems, InterPack05, San Francisco, CA, Engineering from Punjab Techni- July 2005 cal University, India and MS in Mi- croelectronics from University of Central Florida. Page 12 - Tips To Get The Most Out Of Data Viewer -

Application Notes Tips To Get The Most Out Of Data Viewer

When the data viewer is first opened, all buttons are disabled (grayed out) with the exception of ‘Open Datafile’ and ‘Exit’. Importing a data file to the viewer enables the remaining buttons.

Configuring Data View The Chart configuration window (Figure 1) is accessed by clicking the ‘Configure Chart’ button. This window enables the user to plot the ‘actual’ and ‘target’ values of selected process data items vs. the bond recipe time. In addition to common bonding process parameters (top and bottom tool temp, chamber pressure and tool force), the user can also plot other data items such as Recipe Steps (RcpStep) and Recipe Action (RcpAction). RcpStep provides an easy way to view the actual process time spent at each step of the bond process and can be used to refine the The graphical user interface for all Data Viewer graphically displays the bond recipe and improve overall pro- Figure 1: SUSS bonder products is called the contents of selected process data files cess throughput. The actual value (X, Y Data Viewer Plot and Process Control Program (PCP) Navi- and allows customization and export value) of any plotted parameter can be Chart Configuration Window gator. One of the lesser used compo- of process data. This note will discuss viewed on the chart by directly clicking nents available in this navigator is the the common and not-so-common but the line on the plot for that parameter. “Data Viewer”. It is accessed by click- helpful functions available in the Data ing the Navigator Data button. The Viewer. Editing Chart PropertieS The ‘Editing DataChart’ (Figure 2) window is accessed by clicking on the chart properties button in the ‘Chart configuration’ window (Figure 1) and enables easy customization of chart data. All general chart edit functions such as data formats, axis titles and scales, and all plotted parameters can be ed- ited by accessing the Chart and Series tabs in ‘Editing DataChart’ window. The axis for any plotted data items can be changed by first selecting the relevant data series in the ‘Series’ tab and then selecting the horizontal and vertical axis in the ‘General’ subtab. In addition, the user has an option to plot the chart in 3D by accessing the ‘3D’ Figure 2: subtab under the ‘chart’ tab. Data Export Page 13 - Tips To Get The Most Out Of Data Viewer -

‘tools’ tab (Figure 3). These tools allow the user to add extra legends, lines and text to the plotted chart without the need to export and customize the chart in an external application.

Exporting and Printing DatA Data export functionality is available from the Export tab on the ‘Editing Da- Sumant Sood taChart’ window as shown in Figure 2. is the Senior Applications En- Data Viewer allows export of process gineer for Wafer Bonders at data in the following formats: SUSS Microtec Inc.. His recent (a) Common data types (XML, experience includes devel- HTML, Excel or delimited text). opment of plasma enhanced wafer bonding processes for (b) as an image (windows metafile SOI and strained silicon on Insulator (sSOI) applications. or bitmap) Sumant has authored and co-authored more than 15 pa- Figure 3: pers in wafer bonding, SOI, strained silicon and related Chart Tools Gallery (c) native format Using the functions of the Data Viewer areas. He received his B.Tech in Electrical Engineering from Punjab Technical University, India and MS in Micro- The ‘Editing DataChart’ window also discussed above will enable the SUSS electronics from University of Central Florida. has extra chart customization tools that bonder users to get the most out of can be accessed by clicking on the their Data Viewer.

Though spare parts for remanufactured and older tools will be provided New by the German site, North American customers will be working with the new office in Waterbury to get a quo- tation for the parts they need. The of- fices will also support each other in Office tool location and sales worldwide. North American customers interested in purchasing SUSS Remanufactured and Certified Equipment should contact their local Sales Account Manager. in USA If you are not sure who that is, please visit www.suss.com or email info@suss. miles from the SUSS Wafer Bonder com. Customers who need technical Anton Wolejnik, Managing Director, SUSS MicroTec Reman GmbH production facility in Waterbury, Ver- support on older SUSS equipment mont. The new site and staff will fo- should contact our Technical Support Introducing the Certified cus primarily on the remanufactured Hotline at 1-800-TOP-SUSS Remanufactured line of equipment business, such as locat- (867-7877), please give the SUSS quality products ing and repurchasing SUSS tools and attendant the model and se- now in the United States. supporting North American sales of rial number of your tool and remanufactured SUSS equipment. you will be directed to the SUSS Remanufactured and Certi- Technical support will also play an im- specialist for that piece of fied tools are completely reconditioned portant role for this office enabling the equipment. Customers by expert technicians who use genuine SUSS service teams to focus on cur- wishing to trade-in spare parts and state-of-the-art test- rent models of equipment platforms. or sell a piece of ing methods to assure 100% confor- The Reman division will provide the full older equipment mity to original specifications. Tools spectrum of support on all remanufac- can either contact their are fully upgraded to meet today’s tured and older models of SUSS tools. local Sales Account Man- safety standards, include current and The site will be managed by Glenn ager or Glenn Walker at licensed system software, warranty Walker in his function as Business [email protected]. and may offer technology not available Manager Remanufactured Equip- when the original equipment was sold. ment North America. Glenn works SUSS MicroTec opened its North closely with the SUSS ReMan head- American Remanufacturing division quarter in Oberschleissheim, Ger- Remanufactured on May 5 in a location only a few many and SUSS MicroTec Inc. in MABA 6 Waterbury, Vermont. Page 14 - Clif‘s Notes - You Can Define That Exposure Dose In One Wafer! -

You Can Define That Exposure Dose In One Wafer!

This second method also makes short mode a wafer is brought to exposure work of those thick film exposures ta- gap and will remain there for as many king sixty or more seconds. Each of the- exposure cycles as you wish. Thus you se methods will be discussed in detail. simple place the exposure dial at one wedge position and cycle the shutter SUSS Exposure Dial for the desired time. Rotate the wedge This unit is comprised of two pieces to the next position, change the expo- of metal held together in the center sure time and cycle the shutter again. slightly larger than the wafer to be ex- This is repeated for each wedge until posed. The lower piece has six cut outs you have obtained your six exposures in the shape of a wedge while the top and unloaded the wafer. Develop the piece has one wedge shaped cut out. images and you now have six exposure The top piece may be rotated about the conditions on one wafer. center to allow light to pass thru each For thin films this procedure works individual wedge, Figure 1 for example, very nicely and takes a very short time, shows a test dial with top piece rota- however, with thicker films requiring six- ted between two wedges. The beauty ty or more seconds each this could be of this method is that you can do all a very time consuming operation. The- of your testing with the mask of your re is no doubt that it will work, it is just choice, no special mask is required. that it will take such a very long time. You may do up to six exposures on one There must be a faster way to do this Figure 1: Introduction SUSS Exposure Test wafer with each exposure at a different and there is! Dial View There are many ways to determine time or condition. For example, suppo- the best exposure dose for a SUSS 1X se you wish to evaluate the changes in The Step Wedge full field aligner. Many times it seems ea- sidewall profile under different exposure When time is of the essence and you siest to just run a group of wafers each conditions such as proximity gap of say can do only one exposure cycle then at a different exposure time. This me- 0, 15, 20, 40, 80, 160 μm. You simply you need to use a step tablet which has thod however takes time and resources place the dial on top of the mask of your been used in the printing industry for which adds cost to process. There are choice, set the wedge position, cycle many years. It is basically a strip of pla- some very simple and easy methods the wafer thru the tool then rotate the stic with different levels of transmission to reduce the cost of an evaluation yet dial and repeat until all six conditions similar to that shown in Figure 2 where still provide the most information at the are completed. You now have one wa- amount of light passing thru the tablet least cost. fer which has been exposed with your will be reduced in steps from zero to One method which may be used for mask pattern at six different conditions! one-hundred percent. thin resist films involves the use of the If only the exposure time is to be chan- In normal use the tablet is placed on SUSS exposure test dial while the se- ged SUSS has a special feature on its the object to be exposed i.e. your mask cond method uses a simple low cost aligner called ‘exposure test mode’. then the shutter is turned on for a given step wedge. Using the mask of your choice with this time thus producing as many exposu- Page 15 - Clif‘s Notes - You Can Define That Exposure Dose In One Wafer! -

Figure 2: Transmission Step Tablet Figure 3: SUSS Step Tablet re levels on the substrate as there are require you to use at most two wafers steps on the tablet. Thus if you need to find the correct range. First, most to evaluate your mask pattern with say thin resists of say one to five microns three exposure modes, proximity, soft thickness will require about 75 mj/cm² and hard contact, as a function of ex- dose per micron of resist. Thus, simply posure dose you only need three sub- multiply this value times the film thick- strates to complete the test! ness and divide by the light intensity to For semiconductor use ten exposure obtain the nominal exposure time. The steps is far too many to be practical so light intensity will be measured as the SUSS has modified the step tablet1 to broad band ultraviolet light covering a have at most four to six steps similar to range between 330 to 450 microns, those shown in Figure 3. The four step typically the SUSS 405nm probe. This tablet has been defined in the shape of nominal exposure time will be midway a pie chart similar to the exposure test between the lowest and highest expo- dial. These step tablets will allow for an sure times to be used with the test dial investigation of exposures from about or step tablets. A sample calculation for fifty to one-hundred percent of the inci- a typical thin and thick film is shown in Step Wedge, % Trans dent exposure intensity. Table 2 below using the percent trans- Pie Steps Typical changes in exposure intensi- mission values from Table 1. The goal is None 100 % 100 % ty for each step tablet type that SUSS to insure that the steps used will cover uses are shown Table 1. a range of about fifty percent of the total 1 81 % 81 % exposure time. The steps will typically 2 66 % 68 % What Exposure Time? be about twenty percent of the nominal A most important question is how to exposure. Smaller steps have not pro- 3 54 % 63 % define the proper exposure steps to be ven to be any more useful while larger 4 - 53 % used with the test dial or the step tablet. steps may be used if the characteristics 5 - 46 % In most cases it is quite easy and may of the resist are not well known. Table 1: Typical Light Intensity By Tablet Type Page 16 - Clif‘s Notes - You Can Define That Exposure Dose In One Wafer! -

Summary Cliff Hamel In summary, using one of two pos- is the principle applications engineer at SUSS MicroTec, sible methods on the SUSS 1x field Inc. for lithography processes involving full field mask alig- aligner it is possible to evaluate the exposure dose on your mask using only ners and automated cluster coating equipment. Over the one wafer, for an example see Figure 4. last ten years at SUSS he has co-authored several papers Using the SUSS exposure test dial also in the field of thick resist processes and process optimi- allows you to evaluate up to six exposu- zation. He has over 26 years of BEOL process and mask re modes on a single wafer. fabrication experience at IBM where he was the principle engineer and inventor for lift off process development. He received his BS in chemical engineering at Trinity College of Vermont.

Figure 4: Step Tablet Image Size Evaluation AZ50XT, 50µm Thickness, Copper Plate, Design to Substrate Image is approx +13µm.

Table 2: Resist Film Calculating the Steps Thin Thick Units Film Thickness 1.2 20 µm Dose per Micron of Resist 75 55 mj/cm²/µm Nominal Dose 90 1100 mj/cm² UV Light Intensity 70 mw/cm² Nominal Exposure Time 1.3 15.7 seconds Using Percent Transmission from Table 1 No Step 1.9 24.9 seconds 1 1.6 20.2 seconds 2 1.3 17.0 seconds 3 1.1 15.7 seconds 4 - 13.2 seconds 5 - 11.5 seconds Page 17 Scaling in 3 Dimensions

Maximize Your Wafer’s Real Estate

Your success in the third dimension relies on innovative technology. SUSS technology is leading the way in the advancement of 3D applications with innovative equipment solutions enabling the development of production-ready 3D processes. Our commitment to superior performance will prepare your business for the next dimension.

+ 3D Lithography + Wafer-to-Wafer-Bonding + Micro-Bumping + Thin Wafer Handling

www.suss.com E-Mail: [email protected]

suss_semi08_7.875x10.5.indd 1 6/9/2008 5:15:00 PM Page 18 SUSS in the News

Here’s a summary of our recent press releases. To read the entire press release, please visit www.suss.com/about_suss/latest_news

Jan 14, 2008 . SUSS MicroTec litho- March 3, 2008 . SUSS MicroTec Boosts Eindhoven/The Netherlands, for a new resulting from precision mechanics, graphy Quality Management Now Cer- Nanotechnology with New Toolset for enabling technology called Substrate uniform force capability and leading tified According to ISO 9001 : 2000 Mask Aligners Conformal Imprint Lithography (SCIL). edge temperature control. SUSS Mi- SUSS MicroTec Lithography GmbH SUSS MicroTec has launched an The aim of this cooperation is to bring croTec offers advanced wafer bondi- now holds the globally recognized advanced nanotechnology toolset an existing equipment platform with ng solutions for the MEMS, SOI, Op- ISO 9001 certification for having es- for its Mask Aligners. The new Nano this additional Nanoimprinting (NIL) toelectronics, and 3D Interconnect tablished a high level process- and Imprint Lithography (NIL) tool enables feature to the market, enabling new markets. system-oriented quality management SUSS Aligners to print resist thick- approaches to large-area imprint ap- June 26, 2008 . SVTC Technologies (QM) based on ISO 9001 quality stan- nesses from less than 100 nanome- plications along with excellent printing Selects Processing Tools from SUSS dards. The certificate is evidence of ters to a few hundred microns with resolution and repeatability. MicroTec SUSS MicroTec Lithography’s com- a printing resolution down to a few This new imprint technology for sub- SUSS MicroTec, Inc. announced that mitment to provide consistent high- nanometers. UV-NIL is a low-cost 50nm patterning is bridging the gap a suite of processing tools that enable quality development, production and production technology that is based between small rigid stamp application new generations of micro-electrome- service processes at both German on UV-curing. It has been develo- for best resolution and large-area soft chanical systems (MEMS) has been manufacturing sites in Garching (near ped as a cost-effective alternative to stamp usage with the usual limited selected for SVTC Technologies’ fa- Munich) and Vaihingen/Enz (near high-resolution e-beam lithography to printing resolution below 200nm. SCIL cility in Austin, Texas. Stuttgart). print sub-20 nanometer geometries. is an enabling technology offering the As a key supplier to SVTC, SUSS UV-NIL applications with promising best of two worlds – large-area soft Jan 16, 2008 . Freescale Selects 200mm MicroTec also will provide joint de- perspectives include semiconductor, stamps with repeatable sub-50nm SUSS Tool Set for MEMS Facility velopment and support for process MOEMS, NEMS and optoelectronic printing capability, avoiding stamp de- SUSS MicroTec announced it has and tooling. The SUSS toolsets at technologies. formation as no contact force is ap- shipped and successfully installed SVTC include manual and automated plied, non-UV based curing at room several microelectromechanical sys- April 8, 2008 . SUSS MicroTec Installs platforms to perform lithography and temperature and allowing high aspect tems (MEMS) production tools at First 300 mm WLR Test System in Ja- bonding - two of the critical process ratios even up to 1:5 and more. Freescale Semiconductor. The equip- pan steps in the creation of MEMS de- ment included a new DSM200 Series SUSS MicroTec announced the instal- May 29, 2008 – SUSS Automated Bond vices. SVTC, a leading independent Front-to-Back Alignment Verification lation of its PM300WLR, the world’s Cluster Selected for MEMS Foundry in semiconductor process-development System, the latest generation SUSS most advanced 300 mm wafer-level Korea foundry, will use these tools to provi- MA200Compact Mask Aligner as reliability (WLR) test system, at a lea- SUSS MicroTec,announced that de process solutions and a prototy- well as a SUSS ABC200 series Wa- ding Japanese manufacturer of se- u-ITC, Korea, has selected the ad- ping foundry for emerging MEMS and fer Bond Cluster system for use in miconductor devices. It will be used vanced wafer bonding equipment of other devices. MEMS sensor applications. for testing the reliability of current and SUSS for its MEMS foundry. “The SUSS toolset represents the With shrinking design rules, MEMS next-generation devices. u-ITC is a world class MEMS foundry latest technology - giving our custo- devices must be produced with hig- As the technology and design of se- specializing in MEMS sensors. The mers the opportunity to lead the way her precision and accuracy to en- miconductor devices advance, the Incheon facility will incorporate de- for emerging MEMS devices,” said sure reliability and the required per- need to test their reliability and gauge sign, manufacture, assembly and test Dave Bergeron, chief executive offi- formance. With an accuracy of 0.2 their lifetime becomes acuter. Com- within one location for the growing cer of SVTC. micron at 3 sigma, the DSM system mon reliability tests, such as electro- fabless MEMS market. MEMS devices have been instrumen- demonstrates excellent measure- migration (EM) and time-dependent “The SUSS ABC200 Automated tal in creating many state-of-the-art ment results in automated mode. dielectric breakdown (TDDB), require Bond Cluster is a key acquisition for products for the consumer, health- Working in concert with the SUSS the device under test (DUT) to be put our foundry operations,” said Suh, care, automotive and entertainment Compact series mask aligner, these under thermal and electrical stress Dong-Ryang Ph.D, Director at u-ITC, industries. Expected to increase at a two machines represent the perfect over long periods of time to accele- “we can easily meet our customers’ 13 percent compound annual growth package for double-sided alignment rate failure mechanisms. Before the needs by using a cluster tool that can rate through 2010, MEMS are the and exposure applications frequently PM300WLR, these measurements be quickly reconfigured for changing enabling technology behind many used in the manufacturing of MEMS, were carried out after the DUT had process conditions.” well-known applications such as in- power semiconductors and optoelec- been packaged, a costly process that “The flexibility of the SUSS bond kjet printing, automobile air bags, tronic devices. delays time to data and lengthens cluster to quickly reconfigure pro- global positioning systems and mo- the device design cycle. By moving cess parameters from small runs to tion sensing game controllers. Futu- Feb 12, 2008 . SUSS MicroTec AG ap- these tests to wafer level with the full production is a big advantage of re markets to be opened by MEMS points new VP Sales PM300WLR, reliability data is ob- the toolset, especially in the case of technology include fuel cells, com- SUSS MicroTec has appointed Tho- tained sooner, and the device design a foundry serving new markets,” said bustion optimization, drug discovery mas Breser to the position of Vice cycle and thus time to market can be Daniel T. Hurley, International Product and delivery systems, as well as next- President Sales. Thomas Breser co- improved significantly. Manager, Wafer Bonder Division, generation navigation and gaming mes to SUSS with almost 20 years SUSS MicroTec. “We are pleased to systems. international experience within the April 29, 2008 . SUSS MicroTec Signs support u-ITC as they establish them- “We are very pleased to be chosen semiconductor industry. He has held License Agreement with Philips Re- selves as the primary best in class by a high-quality organization such as positions in general management, search to develop a New Nano Imprin- MEMS foundry in Korea.” SVTC and are excited about the pos- sales management, business deve- ting Technology: Substrate Conformal The ABC200 is a 200mm Automa- sibilities that this partnership brings to lopment, product planning and stra- Imprint Lithography (SCIL) ted Bond Cluster. It delivers supe- SUSS MicroTec and our customers”, tegic marketing. SUSS MicroTec has entered a licen- rior post-bond alignment accuracy said Dr. Stefan Schneidewind, CEO se agreement with Philips Research, Page 19

of SUSS MicroTec. “The MEMS in- mer Satisfaction Awards. Customers of customer satisfaction. Customers “Our continuous success shows that dustry has long been a focus for our rated SUSS Micro Tec first among the selected SUSS as best in Cost of our customers highly value the quality company. The opportunity to partner Material Handling Suppliers and fifth Ownership, Uptime, Build Quality, and customer support from SUSS.” with such highly respected forward- among Small Suppliers of Wafer Pro- Usable Throughput, Quality of Result, said Dr. Stefan Schneidewind, CEO looking organization as SVTC will only cessing as well as eighth among the Product Performance and Commit- of SUSS MicroTec AG.” Clearly, our strengthen our ability to service our overall category Focused Supplier of ment thus making SUSS first in seven customers appreciate our high-level growing customer base and our po- Chip Making Equipment. The survey’s of the thirteen categories. application expertise and superior sition as a leading equipment supplier respondents represent 95% of the In the category Small Suppliers of performance they have come to ex- to the MEMS market.” world’s semiconductor market. Wafer Processing Equipment SUSS pect from us. We are dedicated to By securing a number one ranking MicroTec was awarded fifth. Again, further proving ourselves as reliable July 1, 2008 . SUSS MicroTec leads for the tenth year in the category customers rated SUSS best for Build partner and returning their trust with Ranking of 10 Best Material Handling Material Handling Suppliers in which Quality and ranked SUSS among the on-going commitment.” Suppliers for the 10th Year the company’s probe systems are first three within the categories Qua- SUSS MicroTec has been ranked featured SUSS MicroTec has signi- lity of Results, Uptime and Product again among the best suppliers in the ficantly extended its lead in the field Performance. 2008 VLSI Research 10 BEST Custo-

wire-bonded stacked die solutions Are TSVs the Future for future generations of DRAM. Kyle Kirby, senior process integration engineer at Micron, showed a of Advanced Packaging? roadmap of TSV trends for memory with via sizes decreasing below 5 by Julia Goldstein, Ph.D. μm and density increasing to 1000 May 22, 2008 San Jose, CA via etching process. He focused I/O per device. Challenges in mov- The “3D Integration North Ameri- on methods to improve etch rates ing toward this goal include rout- can Tour” came to San Jose on May without producing rough sidewalls ing between die on different levels 15 after stops in Durham, NC and that negatively impact via fill. De- (design tools are not really ready Dallas, TX. The event, hosted by signs with a variety of via sizes are for 3D integration) and overcoming SUSS MicroTec, Surface Tech- still a major challenge. thermo-mechanical stresses as via nology Systems (STS) and NEXX The via fill process is the most ex- spacing decreases. Bob Patti, CTO Systems outlined the current state pensive step in the TSV process of Tezzaron, proposed a solution of the art in through silicon vias and the most time-consuming. Ad- that de-couples the controller from (TSVs) and related technology. An vances in Cu plating chemistry, as the memory functions in separate overview by consultant Phil Garrou, presented by Dr. Yun Zhang, R&D layers, decreasing the number of Ph.D. of MCNC describing various and technical marketing director TSVs required. He also discussed process steps involved in 3D TSV at Enthone, improve throughput increased use of built-in self test Julia Goldstein, Ph.D. has been technology led naturally into de- for a wide range of via sizes while and stacking using a template, technical editor of Advanced tailed presentations on processes producing void-free vias. Arthur achieving a hybrid between wafer- Packaging magazine since 2001. 3D Integration Tour and materials. Keigler, VP of technology at NEXX wafer and die-wafer bonding that She received a B.S. in engineer- The primary application for this Systems, explained how agitating allows the use of KGD with reason- ing from Harvey Mudd College, technology today is CMOS im- the plating fluid near the wafer pro- ably high throughput. Both of these and M.S. in materials science age sensors, with DRAM stacked moted bottom-up filling, eliminating approaches improve overall yield of from Stanford, and a Ph.D. in memory as the next high volume voids at the bottom of vias. He also a wafer stack. materials science from U.C. application. Garrou showed a road- advised using electrochemical de- The current state of the art in wafer Berkeley. Julia has worked as a map that predicted completely het- position to deposit the seed layer, aligning, bonding and thinning, also process development engineer erogeneous stacks with via sizes reducing overall cost. For very large discussed at the seminar, seem at nCHIP, where she developed around 2 μm by 2014. As Garrou vias, Bob Forman of Rohm and sufficient to enable further devel- a flip chip process for multichip noted, many industry leaders, rang- Hass discussed a combination of opment of 3D processes. Kirby modules. Since 1996, she has ing from image sensor and memory Cu-plated liner and polymer plug to stated that, “TSVs are the future of been a technical consultant in ar- manufacturers to IDMs, foundries reduce total fill time. Forman also advanced packaging.” That may eas ranging from flip chip bump- and SATS companies, are involved mentioned indium plating as an be true, but it remains to be seen ing to thin film coatings. Julia has in or have included roadmaps for option for applications that require whether 3D IC integration will bring authored 11 technical publica- 3D activity. lower temperature processing. about the death of wire bonding, as tions, and is a member of IMAPS Stephen Vargo, Ph.D., applications Memory manufacturers empha- flip chip promised to do years ago. and MEPTEC. manager at STS, discussed the sized performance limitations of This column is reprinted with permission from Advanced Packaging Magazine. Some of the opportunities to meet with SUSS MicroTec in the upcoming months:

July IPFA . July 07 - 11, 2008 Semicon West . San Francisco, CA, USA . July 15 - 17, 2008 MIG (MEMS Industry Group) Education Series . San Francisco, CA, USA . July 18, 2008 Micromachine . MEMS . Tokyo, Japan . July 30 - August 01, 2008 August Nano Korea . Nano . Seoul, Korea . August 27 - 29, 2008 September ESTC . Greenwich, UK . Sept 1 to 4, 2008 Semicon Taiwan . Taipei, Taiwan . Sep 09-11, 2008 LED Seminar Semicon Taiwan . Taipei, Taiwan . Sep 11, 2008 MNE08 . Athens, Greece . Sep 15 to 18, 2008 Micronora . Besancon, France . Sept 23 to 26, 2008 MME . Aachen, Germany . Sep 28 to 30, 2008 ESREF . Maastricht, Netherlands . Sep 29 - Oct 02, 2008 October Semicon Europa . Stuttgart, Germany . Oct 07-09, 2008 ABMS Seminar . Kitakyushu, Japan . Oct 8-10, 2008 ECS Fall Meeting/PRIME . Honolulu, Hawaii . Oct 12-16, 2008 European Microwave Week . Amsterdam, Netherlands . Oct 27-31, 2008 SUSS Seminar . Tokyo, Japan . Oct 29, 2008 SUSS Seminar . Shanghai, China . Oct 31, 2008 November ISTFA . Portland, OR, USA . Nov 2-6, 2008 SUSS Seminar . Seoul, Korea . Nov 3, 2008 SUSS Seminar . Taipei, Taiwan . Nov 5, 2008 MEMS Executive Congress . Monterey, CA, USA . Nov 5-11, 2008 SUSS Seminar . Singapore . Nov 7, 2008 RTI-3D . Burlingame, CA, USA . Nov 17-19, 2008 Microwave . Yokohama, Japan . Nov 26-28, 2008 December Semicon Japan . Chiba, Japan . Dec 03-05, 2008 ARFTG . Portland, OR, USA . Dec 9-12, 2008 Sponsor MRS . Boston, MA . Dec 12, 2008 APMC . Hong Kong . Dec 17-19, 2008

Please check our website for any updates: www.suss.com/events

We hope you found this edition of the SUSS Report interesting and informative. For more information about SUSS and our products, please visit www.suss.com or write to [email protected] with your comments and suggestions.

SUSS MicroTec AG Schleissheimer Strasse 90 85748 Garching near Munich Germany

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