Characterization of Al-Ge Bonding for MEMS Packaging
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Wafer Bonding Methods
Wafer Bonding Methods ADVANCED TECHNOLOGY FOR KNOWLEDGE BASE FACT RESEARCH & INDUSTRY SHEET • SCOPE: This document provides an overview of the different wafer bonding methods used in semiconductor manufacturing. Wafer bonding refers to the attachment of two or more substrates or wafers to one another through a range of physical and chemical processes. Wafer bonding is used in a variety of technologies such as MEMS device fabrication, where sensor components are encapsulated within the application. Other areas of application are in three-dimensional integration, advanced packaging technologies and CIS manufacturing. Within wafer bonding there are two main groupings, temporary bonding and permanent bonding, both of which play a key part in the technologies that facilitate three-dimensional integration. The main techniques used in wafer bonding are: • Adhesive • Anodic • Eutectic • Fusion • Glass Frit • Metal Diffusion • Hybrid • Solid liquid inter-diffusion (SLID) Adhesive bonding Adhesive bonding utilises a range of polymers and adhesives to attach the wafers to one another. These polymers include epoxies, dry films, BCB, polyimides and UV curable compounds. Adhesive bonding is widely utilised throughout the microelectronic and MEMS manufacture industry as it is a simple robust and often low cost solution. A major advantage for their use is the comparatively low temperature for protecting sensitive components allowing compatibility with standard integrated circuit materials and processes. Other advantages include the ability to join different types and materials of substrate together and insensitivity to surface topography. Additionally adhesive bonding can be used for both permanent and temporary wafer bonding. In an adhesive bond it is the polymer adhesive that bears the force needed to hold the two surfaces together and also distributes this force evenly across the substrate surfaces to avoid localised any stresses across the join. -
Copper Thermocompression for Mems Encapsulation
Henri Ailas COPPER THERMOCOMPRESSION FOR MEMS ENCAPSULATION Master’s Programme in Chemical, Biochemical and Materials Engineering Major in Chemistry Master’s thesis for the degree of Master of Science in Technology submitted for inspection, Espoo, 5th of April, 2019 Supervisor Prof. Kari Laasonen Advisors D.Sc. Jaakko Saarilahti D.Sc. Jyrki Kiihamäki Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Henri Ailas Title Copper thermocompression for MEMS encapsulation Degree programme Chemical, Biochemical and Materials Engineering Major Chemistry Code of major CHEM3023 Thesis supervisor Prof. Kari Laasonen Thesis advisors D.Sc. Jaakko Saarilahti, D.Sc. Jyrki Kiihamäki Date 5.4.2019 Number of pages 92+5 Language English Abstract Copper thermocompression is a promising wafer-level packaging technique, as it al- lows the bonding of electric contacts simultaneously to hermetic encapsulation. In thermocompression bonding the bond is formed by diffusion of atoms from one bond interface to another. The diffusion is inhibited by barrier forming surface oxide, high surface roughness and low temperature. Aim of this study was to establish a wafer-level packaging process for MEMS (Micro- ElectroMechanical System) mirror and MEMS gyroscope. The cap wafer of the MEMS mirror has an antireflective coating that limits the thermal budget of the bonding process to 250°C. This temperature is below the eutectic temperature of most com- mon eutectic bonding materials, such as Au-Sn (278°C), Au-Ge (361°C) and Au-Si (370°C). Thus a thermocompression bonding method needed to be developed. Cop- per was used as a bonding material due to its low cost, high self-diffusivity and re- sistance to oxidation in ambient air. -
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon
Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Degree project in Microsystem Technology Second level Stockholm, Sweden 2011 XR-EE-MST 2011:005 Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon SOBIA BUSHRA Master’s Degree Project in Microsystem Technology (MST) KTH Royal Institute of Technology Stockholm, Sweden Supervisor: Henrik Gradin Examine: Wouter van der Wijngaart September 2011 Abstract The objective of this research work was to investigate the low temperature gold silicon eutectic bonding of SMA with silicon wafers. The research work was carried out to optimize a bond process with better yield and higher bond strength. The gold layer thickness, processing temperature, diffusion barrier, adhesive layer, and the removal of silicon oxide are the important parameters in determining a reliable and uniform bond. Based on the previous work on Au-Si eutectic bonding, 7 different Si substrates were prepared to investigate the effect of above mentioned parameters. Cantilevers with different bond sizes were prepared from SMA and steel sheets. Afterwards, these cantilevers were bonded to the prepared substrates. The bond yield and bond strength are the two parameters which establish the bond quality. Quantitative analysis was carried out by shear tests. Scanning Electron Microscopy (SEM) and Mapping were used for the analysis of the bond interface and diffusion of elements across the bond. The research has resulted in bonding of SMA cantilevers onto silicon wafers with high yield and bond strength. Steel cantilever can also be bonded by Au-Si eutectic alloy but the processing of the steel sheet is critical. -
Wafer-To-Wafer Permanent Bonding
REVERSE COSTING® – STRUCTURAL, PROCESS & COST REPORT Wafer Bonding Comparison Permanent Bonding – Physical analysis and Cost Overview MEMS, Imaging, LED, Packaging report by Audrey LAHRACH November 2018 – Sample 22 bd Benoni Goullin 44200 NANTES - FRANCE +33 2 40 18 09 16 [email protected] www.systemplus.fr ©2018 by System Plus Consulting | Wafer to Wafer Permanent Bonding Comparison 2018 1 Table of Contents Overview / Introduction 5 o Thermo-compression Bonding o Executive Summary o MEMS RF o Reverse Costing Methodology o MEMS Inertial Sensor Permanent Wafer Bonding Technology 9 Physical Comparison 140 Permanent Wafer Bonding Definition and Process Description 13 o Without intermediate layer Cost Comparison 164 o Fusion Bonding o CMOS Image Sensor Feedbacks 168 o MEMS Inertial Sensor SystemPlus Consulting services 170 o Cu-Cu/Oxide Hybrid Bonding o CMOS Image Sensor o Anodic Bonding o MEMS Pressure Sensor o With intermediate layer o Glass Frit o MEMS Pressure Sensor o MEMS Inertial Sensor o Adhesive Bonding o MEMS Micro-mirror o Eutectic Bonding o MEMS Inertial Sensor o Microbolometer o LED ©2018 by System Plus Consulting | Wafer to Wafer Permanent Bonding Comparison 2018 2 Executive Summary Overview / Introduction o Executive Summary This comparative review has been conducted to provide insights into the structures, processes and costs of the main o Reverse Costing Methodology permanent wafer bonding technologies. o Glossary Wafer Bonding Technology Among these technologies, we have identified two main groups. One, bonding wafers without intermediate layers, includes Wafer Bonding Definition and fusion, copper-copper hybrid and anodic bonding approaches. The second group involves bonding wafers with intermediate Process Description layers using an insulator like a glass frit, or a metal in eutectic and thermocompression approaches. -
Mechanical Characterization of Glass Frit Bonded Wafers
IMEKO TC15 - Experimental Mechanics - Proceedings of the 11th Youth Symposium on Experimental Solid Mechanics Brasov, ROMANIA, 2012, May 30-June 2 MECHANICAL CHARACTERIZATION OF GLASS FRIT BONDED WAFERS K. VOGEL1, 2 D. WUENSCH2 S. UHLIG 2 J. FROEMEL1 F. NAUMANN3 M. WIEMER1 T. GESSNER1, 2 Abstract: Wafer bonding is a key technology in the manufacturing of microelectronic and micromechanical systems on industrial scale. Especially glass frit bonding is often used for the encapsulation of MEMS devices on wafer level. To ensure the reliability of these bonds and to prevent critical failure of the systems, characteristic mechanical properties of the bonded interface are required. The fracture toughness and the shear strength are suitable values to characterize the bonding strength and can be determined by micro chevron and shear testing. They depend on the bonding parameters as well as the test speed. Due to the correlation between measured bonding strength and test speed a maximum test speed has to be identified to obtain reliable failure criteria regarding the fracture toughness and the shear strength. Key words: glass frit bonding, stress intensity coefficient, fracture toughness, shear strength, influence of test speed. 1. Introduction the bonding strength. They enable an estimation of lifetime for the whole MEMS Wafer bonding is a key technology in the device as well as the comparison of manufacturing of micro electro mechanical different bonding technologies and process systems (MEMS) on industrial scale. It parameters during bonding. describes various techniques of joining two wafers with or without thin intermediate 2. Technology and Methods layers. Thereby, glass frit bonding is used in a wide range of industrial applications, 2.1. -
Copyrighted Material
1 Part One Technologies COPYRIGHTED MATERIAL A. Adhesive and Anodic Bonding 3 1 Glass Frit Wafer Bonding Roy Knechtel Glass frit wafer bonding is widely used in industrial microsystems applications where fully processed wafers have to be bonded. This end - of - process - line bonding must fulfi ll some very specifi c requirements, such as: process temperature limited to 450 ° C to prevent any temperature - related damage to wafers, no aggressive cleaning to avoid metal corrosion, high process yield since wafer processing to this stage is expensive, bonding of wafers with certain surface roughness or even surface steps resulting from metal lines electrically running at the bonding inter- face to enable electrical connections into the cavity sealed by the wafer bonding, as well as a mechanically strong, hermetically sealed, reliable bond. All of these requirements are fulfi lled by the glass frit wafer bonding process, which addition- ally can be very universally applied since it can be used to bond almost all surfaces common in microelectronics and microsystem technologies. 1.1 Principle of Glass Frit Bonding The basic principle of glass frit bonding is the use of glass as a special intermedi- ate bonding layer. This glass must have a low - temperature melting point. In the bonding process, the glass between the wafers to be bonded is heated, so that its viscosity continually decreases until the so - called wetting temperature is reached, at which point the glass is soft enough and liquid enough to fl ow and wet the wafer surface. In this fl owing process, the glass comes into contact with the surface to be bonded at the atomic level, and fl ows into surface roughnesses and around surface steps. -
Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding
Transactions of The Japan Institute of Electronics Packaging Vol. 8, No. 1, 2015 [Technical Paper] Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding Kazuya Nomura*, Akiko Okada*, Shuichi Shoji*, Toshinori Ogashiwa**, and Jun Mizuno* *Waseda University, 3-4-1 Okubo, Shinjyuku, Tokyo 169-8555, Japan **Tanaka Kikinzoku Kogyo K.K., 2-73 Shinmachi, Hiratsuka, Kanagawa 254-0076, Japan (Received July 30, 2015; accepted November 4, 2015) Abstract We propose a novel fabrication methodology for a hermetic sealing device using an O2 plasma-assisted low temperature Intrinsic-Silicon (I-Si) and glass bonding technique. Glass substrates were used as the cap and base wafers, while I-Si was applied selectively to the contact surface of the cap wafer as an interlayer. A 180-μm-deep cavity was formed in the cap glass by wet etching using a double-layer (photoresist/I-Si) etching mask. I-Si/glass bonding was conducted at 200°C using an I-Si layer-covered glass wafer and a bare glass wafer. Water contact angle measurements and tensile test results showed that the bonding strength increased with promoting surface hydrophilicity through O2 plasma pretreatment. Moreover, scanning acoustic microscope observations revealed that I-Si/glass bonding was achieved successfully without significant voids. Our results indicate that the proposed method could become an indispensable technique for future functional hermetic sealing devices. Keywords: Glass-to-glass Structure, Hermetic Sealing, HF Wet Etching, Intrinsic-silicon/glass -
Wafer Bonding — a Powerful Tool for MEMS
Indian Journal of Pure & Applied Physics Vol. 45, April 2007, pp. 311-316 Wafer bonding — A powerful tool for MEMS K N Bhat +, A Das Gupta, P R S Rao, N Das Gupta, E Bhattacharya, K Sivakumar, V Vinoth Kumar, L Helen Anitha, J D Joseph, S P Madhavi & K Natarajan* Electrical Engineering Department, Indian Institute of Technology Madras, Chennai 600 036 +Present address: ECE Department, Indian Institute of Science Bangalore 560 012 *Bharat Electronics Ltd, Jalahalli, Bangalore 560 013 Received 7 June 2006; accepted 16 October 2006 Wafer bonding techniques play a key role in the present day silicon bulk micromachining for MEMS based sensors and actuators. Various silicon wafer bonding techniques and their role on MEMS devices such as pressure sensors, accelerometers and micropump have been discussed. The results on the piezoresistive pressure sensors monolithically integrated with a MOSFET differential amplifier circuit have been presented to demonstrate the important role played by the Silicon Fusion Bonding technique for integration of sensors with electronics on a single chip. Keywords : Silicon fusion bonding, Silicon on insulator, Piezoresitive pressure sensor, MOSFET amplifier integration with sensor IPC Code : B81B7/02 1 Introduction 2 Wafer Bonding Techniques for MEMS Wafer- level bonding of a silicon wafer to another Silicon wafer 1 bonding for MEMS is achieved by silicon substrate or to a glass wafer plays a key role in several different approaches such as (1) anodic all the leading-edge Micro-Electro-Mechanical bonding, (2) direct bonding and (3) intermediate layer Systems (MEMS). When used along with the wet or bonding which includes eutectic and glass-frit bonds. -
Wafer Bonding Enables New Technologies and Applications Teikoku Taping Systems
Wafer Bonding Enables New Technologies and Applications Teikoku Taping Systems TTS Confidential Document Prepared by: Mark Franklin At a Glance Forecasts for the demise of Moore’s Law are fairly common. There is a limit to making smaller features where cost and complexity issues become prohibitive. The semiconductor industry has established, rather quickly, a new path forward focused around 3D stacking of integrated circuits. Adding a third dimension to an integrated circuit packs more transistors into the same small footprint without the need to shrink the features of the circuit. The layers are stacked like floors in a skyscraper effectively allowing Moore’s law to continue, albeit, down a slightly different path. 3D integration or vertically stacked chips or wafers requires new technology and new equipment. Just as chemical mechanical polishing (CMP) became the enabling technology for the industry years ago; wafer bonding has been identified as its next enabling technology. Changing Landscape Cost of Future Scaling The Governing Paradigm: More than Moore Source: Samsung & Micron Images Temporary Bonding/Debonding Temporary wafer bonding and debonding has emerged as challenging processes necessary for most 3D integration schemes. The selection of a suitable temporary bond process is the key to success. Through silicon via (TSV) processing places significantly higher technical demands on the bond process compared to MEMS or GaAs processing on smaller wafers. The bond process must be able to withstand temperatures of up to 300C or more while at the same time be easily removed at room temperature, opposing objectives. It must be resistant to a wide range of semiconductor chemicals that it will contact, from solvents and acids to plating solutions and cleaning agents. -
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems XIAOJING WANG Doctoral Thesis Stockholm, Sweden, 2019 Front cover pictures: Left: SEM image of an array of vertically assembled microchips that are electrically packaged by wire bonding. Right: Optical image of wafer bonded ultra-thin silicon caps of different sizes for wafer-level vacuum sealing. KTH Royal Institute of Technology School of Electrical Engineering TRITA-EECS-AVL-2019:65 and Computer Science ISBN 978-91-7873-280-7 Department of Micro and Nanosystems Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektroteknik och datavetenskap fredagen den 4:e oktober klockan 10:00 i Sal F3, Lindstedtsvägen 64, Stockholm. Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at KTH Royal Institute of Technology, Stockholm, Sweden. © Xiaojing Wang, September 2019 Tryck: Universitetsservice US AB, 2019 iii Abstract Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high- throughput heterogeneous integration challenges for emerging applications. The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding. -
Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic Metal Bonding of Wafers Is Used in Advanced MEMS Packaging and 3D Integration Technologies
2008 . July Issue Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding Eutectic metal bonding of wafers is used in advanced MEMS packaging and 3D integration technologies. A unique feature of eutectic metals is the melting of the solder like alloys that facilitate surface planarization and provide a tolerance to surface topography and particles. Advanced wafer level bonding using 2-3um thick metal layers allows precision alignment preventing the aberrant viscous flow of the metal and wafer slippage. Also in this issue: • C4NP Next Generation Wafer Bumping Page 2 index 3 The Age of 3D Integration 12 Application Notes Wilfried Bair Tips to Get The Most Out Vice President Strategic Business Development, of Data Viewer SUSS MicroTec Sumant Sood, SUSS MicroTec 4 C4NP Next Generation Wafer 13 New Office in USA Bumping Anton Wolejnik, Managing Director, SUSS MicroTec Changing bumping requirements driven by 3D Packaging Klaus Ruhmer and Emmett Hughlett, 14 Clif´s Notes SUSS MicroTec You Can Define That Exposure Dose In One Wafer! 6 Precision Wafer to Wafer Clifford J. Hamel, Packaging Using Eutectic SUSS MicroTec Metal Bonding Shari Farrens, Ph.D. and Sumant Sood, SUSS MicroTec 18 SUSS in the News 20 Tradeshows/Conferences SUSS Scores First Place for 10th Year as Material Handling Supplier Page 3 Full View The Age of Integration 3D When commercial wafer bonders processes. A commonly used com- were first introduced to the industry parison of 3D integration with real in the early 90’s the main driver for estate illustrates that when silicon this new equipment type was the space is at a premium or cannot be then emerging MEMS technology. -
Customized Glass Sealant for Ceramic Substrates for High Temperature Electronic Application
This document is downloaded from DR‑NTU (https://dr.ntu.edu.sg) Nanyang Technological University, Singapore. Customized glass sealant for ceramic substrates for high temperature electronic application Sharif, Ahmed; Gan, Chee Lip; Chen, Zhong 2014 Sharif, A., Gan, C. L., & Chen, Z. (2014). Customized glass sealant for ceramic substrates for high temperature electronic application. Microelectronics reliability, 54(12), 2905‑2910. https://hdl.handle.net/10356/102501 https://doi.org/10.1016/j.microrel.2014.07.005 © 2014 Elsevier Ltd. This is the author created version of a work that has been peer reviewed and accepted for publication by Microelectronics reliability, Elsevier Ltd. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [http://dx.doi.org/10.1016/j.microrel.2014.07.005]. Downloaded on 07 Oct 2021 04:50:29 SGT Customized Glass Sealant for Ceramic Substrates for High Temperature Electronic Application Ahmed Sharif1, Chee Lip Gan2 and Zhong Chen2 1. Department of Materials & Metallurgical Engineering, Bangladesh University of Engineering and Technology, Dhaka 1000, Bangladesh 2. School of Materials Science & Engineering, Nanyang Technological University, Singapore 639798 Corresponding Author: Dr. Ahmed Sharif, Tel: (+88)-01912802486, Fax: (+88)-029665618, E-mail: "Dr. Ahmed Sharif" [email protected] Abstract This study investigates the ceramic to ceramic bonding, using composite glass frit as the binding layer that is able to tolerate a high temperature environment for ruggedized microelectronic applications. Shear strength measurements were carried out at both ambient room and high temperature (i.e.