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Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding

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Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding Transactions of The Japan Institute of Electronics Packaging Vol. 8, No. 1, 2015 [Technical Paper] Fabrication Methodology for a Hermetic Sealing Device Using Low Temperature Intrinsic-Silicon/Glass Bonding Kazuya Nomura*, Akiko Okada*, Shuichi Shoji*, Toshinori Ogashiwa**, and Jun Mizuno* *Waseda University, 3-4-1 Okubo, Shinjyuku, Tokyo 169-8555, Japan **Tanaka Kikinzoku Kogyo K.K., 2-73 Shinmachi, Hiratsuka, Kanagawa 254-0076, Japan (Received July 30, 2015; accepted November 4, 2015) Abstract We propose a novel fabrication methodology for a hermetic sealing device using an O2 plasma-assisted low temperature Intrinsic-Silicon (I-Si) and glass bonding technique. Glass substrates were used as the cap and base wafers, while I-Si was applied selectively to the contact surface of the cap wafer as an interlayer. A 180-μm-deep cavity was formed in the cap glass by wet etching using a double-layer (photoresist/I-Si) etching mask. I-Si/glass bonding was conducted at 200°C using an I-Si layer-covered glass wafer and a bare glass wafer. Water contact angle measurements and tensile test results showed that the bonding strength increased with promoting surface hydrophilicity through O2 plasma pretreatment. Moreover, scanning acoustic microscope observations revealed that I-Si/glass bonding was achieved successfully without significant voids. Our results indicate that the proposed method could become an indispensable technique for future functional hermetic sealing devices. Keywords: Glass-to-glass Structure, Hermetic Sealing, HF Wet Etching, Intrinsic-silicon/glass Bonding, Low Temperature Bonding 1. Introduction roscopes, accelerometers, and pressure sensors.[16] To In recent years, hermetic sealing devices for encap- achieve the interconnection, several bonding methods sulating integrated circuits (IC) and microelectrome- using insulating interlayers have been reported, including chanical systems (MEMS) have attracted significant glass frit bonding and adhesive bonding.[17, 18] These research attention.[1–4] In most cases, the hermetic seal- methods can provide a very strong bonding strength ing device comprises a cap wafer, a base wafer, and an exceeding 10 MPa while maintaining insulation, but their encapsulated device. A cavity is formed in either of the practical usage is still challenging. Glass frit bonding is wafers and the device is placed onto the cavity area. The generally performed at high temperatures (400–500°C), wafers are bonded under vacuum or in a N2 atmosphere. which may degrade or damage the encapsulating Hence, the encapsulated device has a longer operating devices.[17] In the case of adhesive bonding, the influence life and more improved characteristics than what is in the of outgas from the adhesive or the invasion of moisture atmosphere.[5] should be considered.[18] Therefore, in order to over- In many hermetic packaging technologies, glass has come these limitations, a novel bonding method with an been widely used as the cap wafer owing to its mechanical appropriate insulating material is required for functional sturdiness, chemical stability, and permeability to light and hermetic sealing devices. radio frequency (RF) power.[6–10] Moreover, glass is also In this study, we propose the use of intrinsic-silicon (I-Si) employed as the base wafer because it has high electrical as an interlayer for hermetic sealing devices because I-Si resistance and a low loss tangent even at high-frequency has the following three unique features. (1) I-Si exhibits ranges.[11–15] insulation property because no significant impurities such Recently, there has also been an interest in side-direc- as phosphorus or boron are doped into it. (2) I-Si has a tional interconnection, which allows signal transmissions possibility of low temperature bonding by activating its or a power supply for MEMS devices, such as microgy- surface.[19–21] (3) The deposition of I-Si is relatively sim- 74 Copyright © The Japan Institute of Electronics Packaging Nomura et al.: Fabrication Methodology for a Hermetic Sealing Device (2/7) Fig. 1 Schematic image of a hermetic sealing device. Fig. 2 Measuring circuit of four-probe method. Fig. 3 Fabrication process of cap wafer. ple compared to other interlayers that need electroplating respectively. The sample temperature was controlled from or multilayer deposition,[3, 22, 23] because it doesn’t 25°C to 300°C based on considerations of the possible require the wet etching process and the adhesive layer. temperature at the time of I-Si/glass bonding. The concept of the hermetic sealing device is illustrated 2.2 Fabrication of the cap wafer in Fig. 1. The I-Si interlayer is formed on the ring-shaped Figure 3 shows the fabrication process of the cap wafer area of the cap wafer, and I-Si/glass bonding is conducted with an I-Si interlayer. We employed HF wet etching using with the base glass wafer. In the following, we describe a double-layer etching mask to prevent the HF solution three processes involved in the fabrication of the proposed from forming pinholes on the glass substrate.[24] First, 1 device: evaluating the insulating property of the sputtered μm I-Si was sputtered onto both sides of the 50 × 50 mm2 I-Si, fabrication of the cap wafer with an I-Si interlayer, and non-alkali glass (EN-A1, Asahi Glass Co., Ltd.) and the evaluating I-Si/glass bonding. glass was then annealed for 60 min at 450°C in a N2 atmo- sphere (RHL-P610CP, CANON ANELVA Corp.). Next, a 2. Experimental Procedure positive photoresist (LA-900, Tokyo Ohka Kogyo Co., Ltd.) 2.1 Insulating property of sputtered I-Si was applied to both sides of the glass, whereas the I-Si and To evaluate the insulation property of I-Si, resistance resist were patterned only on the front side. Wet etching measurements were obtained using a four-probe method was then carried out with agitation for 2 h to form a cavity (Grail 10-5-LV-HTV, Nagase Techno-Engineering Co., using the double-layer (resist/I-Si) as an etching mask. A Ltd.), as shown in Fig. 2. First, 300 nm I-Si was sputtered 12.5 wt% HF solution was used as the etchant. After wet onto a 20 × 20 mm2 glass substrate (SPC350, CANON etching, the resist and I-Si were removed with acetone and ANELVA Corp.). Next, surface silicon dioxide was dry etching (RIE-10NR, SAMCO Inc.) because the HF removed by dry etching using Ar ion and Au electrodes solution would have degraded the surface condition of the were then arrayed onto the I-Si surface in the same vac- I-Si. The conditions for dry etching are listed in Table 1. uum chamber (M820, Hakuto Co., Ltd.). The diameter and Next, masking tape was cut to the size of the cavity and pitch of the Au electrodes were 250 μm and 470 μm, pasted onto the cavity area. This simple patterning method 75 Transactions of The Japan Institute of Electronics Packaging Vol. 8, No. 1, 2015 Table 1 Condition of dry etching. Table 3 Condition of O2 plasma pretreatment. Gas Species SF6 RF Power 150 W Flow Rate 30 sccm Vacuum 5.13 mPa RF Power 100 W Time 1 min Vacuum 3.0 Pa Time 3 min Table 4 Condition of I-Si/glass bonding. Temperature 200°C Applied Pressure 5.0 MPa Vacuum 0.50 Pa Time 30 min Fig. 4 Measurement points of substrate thickness. Table 2 Condition of AFM measurement. Observation Mode Dynamic Mode SSS-NCH Probe (Nanoworld Co., Ltd.) Scanning Area 1 μm × 1 μm Scanning Speed 1 Hz Fig. 5 Resistance vs temperature of I-Si. has limitations in terms of the tape size and accurate align- 2.4 I-Si/glass bonding ment, but we considered that they would not affect the After pretreatment with O2 plasma, I-Si/glass bonding subsequent processes. Contamination that remained after was conducted (SB6e, SUSS MicroTec AG.). Untreated removing the tape would be removed easily by ultrasonic wafers were also bonded for comparison. These bonding cleaning. Finally, the aluminum tape was removed manu- experiments were performed simply to demonstrate the ally. The thicknesses of the cavity and ring-shaped area superior performance of the O2 plasma; therefore, only were measured by a digital micrometer (MH-15M, Nikon one sample was prepared for each plasma condition. The Corp.) at 25 and 24 points, respectively, as shown in Fig. 4. bonding conditions are listed in Table 4. Next, the inter- In addition, the surface roughness of the ring-shaped area face between the I-Si and glass was observed using scan- was observed using atomic force microscopy (AFM) ning acoustic microscopy (SAM) (SAM300, PVA Tepla (SPM-9600, SHIMADZU Corp.). Table 2 lists the measure- Analytical Systems GmbH) with a 210-MHz transducer. ment conditions for AFM. Furthermore, a tensile test was performed using a 2.3 O2 plasma pretreatment MODEL-1307R (AIKOH ENGINEERING Co., Ltd.) at To clarify whether I-Si/glass bonding was applicable for crosshead speeds of 50 mm/min to determine the strength a hermetic sealing, a bonding evaluation was performed of I-Si/glass bonding. with a non-patterned I-Si layer-covered glass wafer and bare glass wafer. First, we investigated the effect of the O2 3. Results and Discussion plasma pretreatment on the bonding performance. Table 3 3.1 Insulating property of sputtered I-Si lists the O2 plasma conditions (PL8, SUSS MicroTec AG.). Figure 5 shows the relationship between temperature Untreated wafers and 1 min O2 plasma treated ones were and the resistance per unit length. The resistance of I-Si prepared. Second, the water contact angles were measured decreased as the temperature increased up to a specific using a contact angle meter LCD-400S (Kyowa Interface temperature range (200–300°C in this study).
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