Indian Journal of Pure & Applied Physics Vol. 45, April 2007, pp. 311-316

Wafer bonding — A powerful tool for MEMS

K N Bhat +, A Das Gupta, P R S Rao, N Das Gupta, E Bhattacharya, K Sivakumar, V Vinoth Kumar, L Helen Anitha, J D Joseph, S P Madhavi & K Natarajan* Electrical Engineering Department, Indian Institute of Technology Madras, Chennai 600 036 +Present address: ECE Department, Indian Institute of Science Bangalore 560 012 *Bharat Electronics Ltd, Jalahalli, Bangalore 560 013 Received 7 June 2006; accepted 16 October 2006

Wafer bonding techniques play a key role in the present day bulk micromachining for MEMS based sensors and actuators. Various silicon wafer bonding techniques and their role on MEMS devices such as pressure sensors, accelerometers and micropump have been discussed. The results on the piezoresistive pressure sensors monolithically integrated with a MOSFET differential amplifier circuit have been presented to demonstrate the important role played by the Silicon Fusion Bonding technique for integration of sensors with electronics on a single chip. Keywords : Silicon fusion bonding, Silicon on insulator, Piezoresitive pressure sensor, MOSFET amplifier integration with sensor IPC Code : B81B7/02

1 Introduction 2 Wafer Bonding Techniques for MEMS Wafer- level bonding of a silicon wafer to another Silicon wafer 1 bonding for MEMS is achieved by silicon substrate or to a wafer plays a key role in several different approaches such as (1) anodic all the leading-edge Micro-Electro-Mechanical bonding, (2) and (3) intermediate layer Systems (MEMS). When used along with the wet or bonding which includes eutectic and glass- bonds. dry etching techniques, the wafer bonding technique Even though, the process conditions used for all the can be used to realize (1) membranes of thickness three bonding techniques vary, the general process of varying from couple of microns to several microns, the wafer bonding follows a three step sequence suitable for pressure sensors over a wide range of consisting of surface preparation, contacting and pressures, (2) complicated three dimensional annealing. structures for accelerometers for sensing acceleration involves bonding a silicon wafer and (3) multilayered device structures such as and a glass wafer with a high content of sodium. Fig.1 micropump suitable for biomedical and microfluidic shows the schematic of the anodic bonding applications, and (4) high aspect ratio structures arrangement. The anodic bonding is carried out at which can compete with the LIGA process. The 450 °C by applying a high voltage in the range manufacturers of MEMS require wafer-level bonding 500 -1000 V as shown in Fig. 1 to attract NA + ions to of one silicon wafer to another silicon substrate or a the negative electrode where they are neutralized. glass wafer. This provides a first level packaging This to the formation of a space charge at the solution that makes these processes economically viable. In this paper we first discuss the various silicon wafer bonding techniques and illustrate their role on MEMS devices such as pressure sensors, accelerometers and micropump. The results obtained in our laboratory on the piezoresistive pressure sensors monolithically integrated with a MOSFET differential amplifier circuit are presented to demonstrate the important role played by the Silicon

Fusion Bonding technique for the integration of sensors with electronics on a single chip. Fig. 1 — Silicon –glass anodic bonding arrangement 312 INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

glass silicon interface, thus creating a strong multiple bonding waves to warpage and gases electrostatic attraction between glass and silicon can be trapped in pockets formed by multiple waves, wafer, enabling the transport of oxygen from the glass and result in areas of poor bonding. After this pre- to the glass-silicon interface and converts silicon to bonding step, subsequent annealing is carried out at SiO 2 creating a permanent bond. Processes for anodic temperatures in excess of 1000 °C. During this bonding of silicon to bulk glass and silicon to annealing step, the hydroxyl groups from water 2 silicon using thin glass layer have been reported. molecules create Si-O-Si bond as diffuses Typically Pyrex 7740 or Schott 8330 glass are away. Oxygen also diffuses into the crystal lattice to used. The Coefficient (TEC) of create a bond interface that is not distinguishable from these match closely matches with the the rest of the silicon structure. Although the high TEC of silicon, resulting in low stress in the bonded annealing temperature involved in this process is a devices. drawback for some applications, the silicon fusion Silicon Direct Bonding (SDB) which is usually bonding technique permits the formation of cavities, referred to as Silicon Fusion Bonding (SFB) is used as well as all- silicon, stress free bonded structures. It for bonding two or more silicon wafers and is based has been reported 4 that surface activation methods on the initial bonding by hydroxyl radicals present on such as argon beam etching to create a clean surface the silicon wafer surfaces prepared by standard RCA 3 prior to bonding result in excellent bond strengths of clean prior to bonding . Mechanical spacers are 10-12 MPa even when the Si-Si bonding is carried out placed at the edges of the wafers as in Fig.2 (a) to at room temperature. maintain physical separation, so that pressing the Intermediate-layer bonding techniques involve middle of the wafers creates an initial point contact deposition of either metallic or glass intermediate that originates the bond . Removing the mechanical films prior to bonding and they are referred to as spacers as in Fig.2 (b) allows a single bonding wave glass-frit bonding and the . The to propagate from the center of the wafers. The eutectic bonding makes use of the existence of a mechanical spacers are important in establishing a eutectic melting temperature which is considerably single bond front that propagates outward because lower than the melting point of individual constituent elements. For gold and silicon system, the eutectic melting point is 363 °C and corresponds to a eutectic composition of 3.16% silicon and 96.84% gold by weight (19 % silicon and 81% gold by atomic per cent). The eutectic bond is performed by evaporating and plating gold on to one of the silicon wafers and then exposing the gold to UV light just before bonding to remove organic contaminants that preclude gold surface contact with the second silicon

wafer into which it is bonded. To accomplish good bond, the second silicon wafer surface preparation must remove any oxide film that can hamper diffusion of gold into silicon. The eutectic bonding method uses pressure applied with the wafers held at a temperature slightly higher than the eutectic temperature. A detailed optimization study 5 has revealed that maximum bond strength of 18 MPa can be achieved with the bonding temperature of 400 °C and the gold layer thickness of 1.0 µm. In the glass-frit bonding process a thin glass layer such as lead borate is deposited on the silicon substrate. The wafers are then brought into contact under pressure at the Fig. 2 — Silicon fusion bonding (a) Wafers placed in position with spacers (b) Wafers are bonded by removing the mechanical melting temperature of the glass, which is generally spacers and pressurizing < 600 °C. BHAT et al .: WAFER BONDING 313

3 MEMS Devices using Silicon Fusion Bonding actuation as follows. When an attractive potential is and Etching applied to the counter electrode, the membrane Among the various wafer bonding methods, Silicon deflects upwards, decreasing chamber pressure, thus Fusion Bonding (SFB) approach results in stress free opening the inlet check valve and drawing fluid into bonds with bond strength as high as that of silicon the chamber through the inlet port. When the voltage itself. This approach has attracted wide interest for is removed, the membrane relaxes, increasing the MEMS as well as for microelectronics and has chamber pressure, and forcing the fluid out of the opened up new avenues to realize complicated chamber through the outlet port. structures with multiple wafer bonding along with In the above structure, the reliability of operation is Deep Reactive Ion Etching (DRIE) and wet chemical limited due to the clogging of the mechanical check etching of silicon . We illustrate the impact of this valve and due to the fatigue and failure of the moving powerful technology for microstructures with part in this valve. In order to overcome this problem, examples drawn from literature as well as from the valve less micropumps have been designed and structures realized in our laboratory. reported in the literature 8. However the actuation Figure 3 shows a generalized process flow reported voltages required for the operation of the micropumps in the literature 6 for building very tall suspended reported in the literature were rather high in the range structures made entirely from single crystal silicon of 50 to 60 V. Actuation voltages need to be low for using SFB and DRIE. Figure 3(a) shows a spacer applications in drug delivery and drug dosage control cavity etched into a bottom wafer. A second silicon for biomedical applications. Figure 5 shows a wafer is bonded on to the cavity wafer by SFB and it schematic structure of the micropump we have is then thinned down to the desired thickness designed for operation below 10 V. In this structure, Fig. 3(b). This is followed by patterning as shown in the inlet and outlet to the pump chamber are realized Fig. 3(c) for DRIE. The micromechanical structure by nozzle and diffuser type dynamic valves prepared shown in Fig. 3(d) is released by etching through the by etching the silicon substrate which is bonded to the top silicon wafer by DRIE into the buried cavity. silicon membrane having the chamber cavity as Silicon Fusion Bonding enables increased shown in the Fig. 5. When the membrane deflects complexity in device design by allowing multiple downwards due to electrostatic actuation, the ‘outlet’ silicon wafers to be stacked on top of each other and marked in the figure acts as a nozzle and allows more bonded .to each other. The complexity that can be fluid flow out of the chamber as compared to the fluid achieved using SFB is illustrated by a micropump 7 as flow outward through the duct marked ‘inlet’ which shown in Fig. 4. This device is realized using four acts as a diffuser to this direction of flow. When the silicon wafers, three of which have been voltage is brought down to zero, the chamber volume micromachined by wet chemical anisotropic etching increases causing a drop in its pressure, causing the prior to bonding. This device operates by electrostatic flow through the inlet (which now acts as the nozzle) into the chamber to be more than the fluid flow out of the chamber through the ‘outlet’ (which is now behaving like a diffuser). Thus during one stroke

Fig. 3 — Process flow for realizing a suspended mass using SFB Fig. 4 — Schematic structure of the micropump with valves and DRIE (Ref.6) (Ref.7) 314 INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

Fig. 5 — Schematic of a valve less Micropump fabricated using Fig. 6 — Schematic cross sectional view of MOSFET integrated SFB and wet etching pressure sensor cycle, the pump delivers a net fluid corresponding to the stroke volume. The pump - chamber height in our design is reduced to a small value of 0.2 µm choosing the lateral dimensions of the chamber to be 5 mm ×5 mm. This gives rise to a stroke volume of 0.5 nano-liters and a flow rate of 1.5 micro-liters/minutes when actuated by a 50 Hz, 6V pulse voltage. The structure has been designed and fabricated in our laboratory to show the proof of concept. Further study is in progress to fully demonstrate the working of the Micropump with fluid flow.

4 MOS Integrated Pressure Sensors on a Fig. 7 — Circuit diagram of the pressure sensor integrated with Monolithic Chip using Silicon Fusion Bonding MOSFET amplifier on an SOI wafer and SOI Approach One of the many important applications of silicon made compatible with the process steps of the fusion bonding is the realization of Silicon on pressure sensor. (c) Once the processes (a) and (b) Insulator (SOI) wafers which have received were stabilized with reasonably good results, the considerable attention for microelectronics integrated sensor was designed with optimized applications. In this section we show that the SOI minimum number of process steps, fabricated on SOI approach is very attractive to integrate MEMS devices wafers, packaged and tested. and electronics on the same SOI wafer. In this The schematic cross-section of the polycrystalline approach, the thickness of the SOI layer is chosen silicon piezoresitive pressure sensor integrated with from the requirements of the mechanical MOSFET differential amplifier fabricated in our considerations such as the pressure sensor membrane, laboratory on SOI wafer is shown in Fig.6. It may be and the doping concentration of the SOI layer is noted that the piezoresistors are laid out on the oxide decided as per the requirements of the MOSFET grown on the SOI membrane, realized by KOH threshold voltage for the electronics portion of the etching from the backside of the SOI wafer. The integrated sensor. We have designed and processed buried oxide of the SOI wafer serves as an etch stop this integrated pressure sensor in three stages as during the anisotropic etching process. The follows: (a) First the polysilicon piezoresistive electronics portion of the integrated sensor is laid out pressure sensors were designed for operation up to a on the SOI layer outside the membrane region. The maximum pressure of 15 bar, and fabricated on SOI circuit diagram of the integrated pressure sensor is wafers prepared in-house in our laboratory by SFB shown in the Fig. 7. The sensor portion consists of and back etching the top wafer to the required four polysilicon piezoresistors arranged in the form of thickness (b) Next the common source MOSFET a Wheatstone bridge on the oxide grown on the differential amplifier has been designed for a membrane and the output of the Wheatstone bridge is differential gain of 5 and fabricated on bulk silicon connected to the input of the common source wafers to standardize the process so that it can be MOSFET differential amplifier. BHAT et al .: WAFER BONDING 315

Fig. 8 — Layout of four piezoresistors for polysilicon pressure sensor

Polysilicon piezoresistors are used for the pressure sensor because, as the polysilicon piezoresistors are laid out on the oxide, excellent isolation between the Fig.9 Composite mask layout of MOSFET integrated pressure resistors is achieved. The doping concentration of the sensor polysilicon resistors is adjusted by ion implantation of appropriate boron dose to minimize the temperature coefficient of resistance of these resistors. The aspect ratio of the membrane is designed to be 500 ×1000 µm and the polysilicon piezoresistors are laid out as shown in Fig. 8 to achieve the best sensitivity for the membrane thickness of 11 µm which is same as the thickness of the SOI layer. When a pressure is applied over the membrane the resistors R1 and R3 located at the edges of the membrane Fig. 10 — Photograph of the integrated pressures sensor chip experience longitudinal tensile stress and the resistors mounted on a header. (a) Without the cap and (b) With the cap R2 and R4 located near the center of the membrane having a pressure port hole welded on to the header experience longitudinal compressive stress. This will result in an increase in the resistance of the resistors steps of the piezoresistors so as to minimize the R1 and R3 and decrease in resistance of the resistors number of photolithography and process steps. After R2 and R4. This imbalances the Wheatstone bridge realizing the polysilicon piezoresistors and the and hence the output voltage changes with applied amplifier resistors, the MOSFET amplifier portion is pressure. The offset voltage (output voltage when the processed. During these process steps of source drain differential pressure is zero) of the pressure sensor diffusion etc, the resistor regions are protected with fabricated using these masks are small since the PECVD . After completing all the contact resistance between the resistor and the metal process steps, contact windows are opened in the is equal for all the four resistors. regions shown in Fig. 9. This is followed by The composite mask layout of the integrated metal evaporation and patterning as in pressure sensor designed and fabricated in our Fig. 9. The wafer is diced and then packaged in a laboratory is shown in Fig. 9. The differential TO39 header. amplifier has been designed using SPICE simulation A photograph of the integrated pressure sensor by considering 500 mV threshold voltages for the mounted on the header and wire bonded to the posts is MOSFET with 10 V supply to the drain. The drain shown in Fig.10(a) and the same device with a cap and source resistance values have been designed by welded in position is shown in Fig.10(b). The simulation and found to be 10 k Ω and 4 k Ω packaged MOS integrated pressure sensor is mounted respectively for achieving a differential voltage gain in a specially fabricated jig for the purpose of testing of 5. The polysilicon resistors of the amplifier circuit and characterizing the device and pressure is applied are processed simultaneously along with the process from a nitrogen cylinder. The applied pressure is 316 INDIAN J PURE & APPL PHYS, VOL 45, APRIL 2007

that complicated 3-D structures such as micropump with micromachined multilayer silicon wafers and very tall suspended structures made entirely from single crystal silicon can be realized with this approach. It is also shown from our own experiments that Integration of Piezoresistive pressure sensors with electronics circuits can be easily achieved on a monolithic chip using Silicon on Insulator (SOI) wafers which are realized with Silicon Fusion Bonding and Etch Back technique . The pressure sensors thus integrated with MOSFET differential amplifier have been packaged, tested and characterized. Excellent linearity with a maximum nonlinearity of 1% has been seen in these devices. It Fig. 11 — Pressure versus output voltage of the MOSFET is concluded that the SOI approach using silicon integrated pressure sensor wafer bonding holds tremendous promise for measured using a digital pressure gauge. An input of integration of mechanical sensor s and actuators with 10 V is given to both the sensor and the drain supply electronics circuits. of the differential amplifier. The measured voltages at the sensor output and differential amplifier output up References Solid State Technology to 7 bar pressure are shown in Fig. 11. The offset 1 Mirza A R & Aydon A A, , (1999) 72. 2 Weichel Steen, Reus Roger de & Lindahl Michael, Sensors & voltage (output voltage when the differential pressure Actuators, A 70 (1998) 179. is zero) at the integrated sensor output is nullified by 3 Takao Abe, Tokio Takeia, Uchiyama Tsuo, Yoshizawa Katsuo connecting an external resistor across one of the drain & N Yasuaki, Japanese Journal; of Applied Physics, 29 (1990) resistors of the differential amplifier. Sensitivity of 2311. 316 mV per bar with the on chip amplifier gain of 4.5 4 Takagi Hideki, Maeda Ryutaro, Ryong Chang Teak & Suga Tadatomo, Sensors & Actuators, A70 (1998) 164. has been achieved in these devices. The output at the 5 Nai S M L, Wei J, Lim P C & Wong C K, Proceedings of the sensor and amplifier are linear up to 7 bar pressure Electronics Packaging Technology Conference , (2003) 119. with a maximum non linearity of 1%. 6 Klaasen E H, Petersen K, Noworolski J M, Logan J, Maluf N I, Brown J, Storment C, McCulley W and Kovacs G T A, 5 Summary and Conclusions Sensors & Actuators , A52 (1996) 132. In this paper we have shown that the silicon Fusion 7 Zengerle R, Richter A & Sandmair H, Proc. IEEE Micro Electro Mechanical System Workshop , , Travemunde, Bonding is a powerful technique when used along Germany, (1992) 19. with either DRIE or wet chemical etching methods. 8 Gerlach Torsten & Wurmus Helmut, Sensors & Actuators , From the results available in the literature it is shown A50 (1995) 135.