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SET Technical Bulletin DIE BONDING APPLICATIONS SET Technical Bulletin DIE BONDING APPLICATIONS An Innovative Die to Wafer 3D Integration Scheme: Die to Wafer Oxide or Copper Direct Bonding with Planarised Oxide Inter-Die Filling RF MEMS and Flip-Chip for Space Flight Demonstrator Electrically Yielding Collective Hybrid Bonding for 3D Stacking of ICs A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package High Density Cu-Sn TLP Bonding for 3D Integration Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps High Density Cu-Cu Interconnect Bonding for 3-D Integration Manufacturing & Stacking of Ultra-Thin Film Packages New Reflow Soldering and Tip in Buried Box (TB2) Techniques for Ultrafine Pitch Megapixels Imaging Array Electrical Characterization of High Count, 10 µm Pitch, Room-Temperature Vertical Interconnections 3D Stacked Chip Technology Using Bottom-up Electroplated TSVs Study of 15µm Pitch Solder Microbumps for 3D-IC Integration 3D Stacked IC Demonstration using a Through Silicon Via First Approach Contents www.set-sas.fwww.set-sas.fr r 1 / 80 ACKNOWLEDGMENTS A number of people who use SET Die / Flip-Chip Bonders helped develop and prepare the SET Technical Bulletin: Die Bonding Applications. We would like to express our deep appreciation to all the contributing authors, all experts in their respective fields, for their many helpful suggestions and their cooperation in respon- ding to requests for revisions. We would like to thank them all, with specific mention to dedicated people at IMEC: Anne Jourdain, Rahul Agarwal, Bart Swinnen and Eric Beyne. Our special thanks also go to Léa Di Ciocco, Claude Massit, Marion Volpert and François Marion from CEA-LETI, Claude Drevon from Thalès Alenia Space, Aibin Yu from the Institute of Microelectronics, as well as John M. Lannon from RTI International and Jimmy Ying-Ching Shih from ITRI. We are also pleased to include an introduction penned by Jean-Marc Yannou from Yole Développement as well as a conclusion written by George A. Riley from Flipchips.com. The material in the SET Technical Bulletin has clearly been derived from many sources including individuals, companies and organizations. We have attempted to acknowledge in the appropriate parts of the bulletin the assistance that has been given. We would like to extend a special thank you to several professional societies for permitting us to reproduce some of their illustrations and information in this SET Technical Bulletin. These include the Electronic Components and Techno- logy Conference (ECTC), the IEEE International Conference on 3D System Integration (3D IC) and the Institute of Electrical and Electronic Engineers (IEEE). www.set-sas.fr 2 / 80 Contents TABLE OF CONTENTS SET is well Positioned and Prepared to address the Challenges of the fast growing 3D System Integration Market 4 An Innovative Die to Wafer 3D Integration Scheme: Die to Wafer Oxide or Copper Direct Bonding with Planarised Oxide Inter-Die Filling 6 RF MEMS and Flip-Chip for Space Flight Demonstrator 10 Electrically Yielding Collective Hybrid Bonding for 3D Stacking of ICs 14 A Fluxless Bonding Process using AuSn or Indium for a Miniaturized Hermetic Package 17 High Density Cu-Sn TLP Bonding for 3D Integration 26 Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps 32 High Density Cu-Cu Interconnect Bonding for 3-D Integration 38 Manufacturing & Stacking of Ultra-Thin Film Packages 43 New Reflow Soldering and Tip in Buried Box (TB2) Techniques for Ultrafine Pitch Megapixels Imaging Array 50 Electrical Characterization of High Count, 10 µm Pitch, Room-Temperature Vertical Interconnections 58 3D Stacked Chip Technology Using Bottom-up Electroplated TSVs 64 Study of 15µm Pitch Solder Microbumps for 3D-IC Integration 71 3D Stacked IC Demonstration using a Through Silicon Via First Approach 76 High Density 3D Interconnection 80 www.set-sas.fr 3 / 80 Contents SET is well Positioned and Prepared to address the Challenges of the fast growing 3D System Integration Market Jean-Marc Yannou, Project Manager, Advanced Packaging, WLP, 3D System Integration. Yole Développement www.yole.fr - [email protected] Since the advent of photolithography in electronics in the ting personal devices and appliances. You do not only want a early sixties, and for decades, most new technology develo- game console with bright and fast high resolution graphics. pments for the semiconductor industry have aimed at down- You now want to interact with it: it can feel and sense you in sizing the transistors so as to make more integrated, more every possible way, by means of motion and video sensors. powerful, faster and even cheaper Integrated Circuits (ICs). Patients with cardiac rhythm malfunctions want to enjoy their Since a few years, this industry has changed and this in turn lives as they did before being equipped with a pacemaker: shifted the paradigm of technology innovation for semicon- continuous monitoring is now made possible as the pacema- ductors: a consensus is rising within the community of pro- ker device measures the heart beats and directly sends rele- cess experts and scientists that further downsizing of the vant information via the patients cell phone to his physician transistors will not only become more difficult because new without requiring any formal examination at the doctor’s. As geometries tend to the physical limit of atom sizes, but it will a consequence, there is rising awareness that integrated cir- also come along with lower performance side-effects such as cuits are increasingly interacting with the real world by recei- higher parasitic coupling, higher current leakage and thermal ving, processing and transmitting more information than ever issues. From an investors’ perspective, the math is simple: before. The focus is shifting from the transistors constituting in order to reach the next CMOS technology node, huge in- the integrated circuits to their external interfaces, from pro- vestments are needed, and the expected benefits are still cessors to sensors and actuators, from circuits to systems: unclear. the value of semiconductors is shifting from ICs to IC and system packaging. In parallel, electronic applications are being thought diffe- rently and processing power is now less seen as an end than But the challenges remain the same ones as 50 years ago: as a means to develop and build user-friendly communica- how to make high performance, fast, low consumption and 3D TSV Packaging Market Value Forecast Breakdown per application (in M$) Figure 1 - 3D TSV Packaging Market Value Forecast: Breakdown per application (in M$). www.set-sas.fr 4 / 80 Contents Figure 2 - Cost effectiveness of bonding scenarii function of die size and needed placement accuracy. cheap highly integrated electronic systems? What is chan- Moreover, SET is well-positioned on the die to die (or chip to ging is how this is now increasingly being addressed. And chip) and especially on the die to wafer (or chip to wafer) the answer stands in a few keywords: mid-end, wafer-level bonders which represent the favorite solution for a vast ma- packaging, 3D integration. The whole idea is to pack more jority of industrials. Indeed, the chip to wafer bonding tech- electronic function per volume unit (instead of surface area) nique already allows better costs than “chip to chip” as it and to extend the photolithography techniques beyond the enables batch processing at the wafer level. On the other making of ICs to their packaging and their integration in a hand, it offers more integration flexibility than wafer to wafer system. And this is a heavy trend: Yole forecasts that from as different size ICs using heterogeneous wafer processes slightly less than M$ 500 in 2010, the market of 3D integra- can be stacked using chip to wafer. It is also clear that by tion using through silicon vias (TSV) will grow to more than choosing the chip to wafer bonding option, the bonded chips B$ 4 in 2015 (figure 1), addressing a wide variety of advan- can be pre-tested, and only good ICs are reported on the host ced systems! Packaging of MEMS and sensors using wafer- wafer allowing for much higher stack yields than when using level techniques will become mainstream in just a few years wafer to wafer. This accounts for the cost competitiveness of as we forecast a compound annual growth rate of 85% over the chip to wafer bonding technique served by SET versus the 2009-2013 time period! the wafer to wafer bonding technique for many given confi- gurations of die sizes and required placement accuracies as Ahead of time of the other players in the value chain of the illustrated in figure 2. semiconductor industry, equipment manufacturers are bound to play an important role so as to tackle the technology chal- SET clearly appears to be well positioned and prepared and lenges and seize the opportunities offered by this paradigm with the right focus to address any new opportunity offered shift. SET demonstrated throughout this technical bulletin by the high growth mid-end semiconductor market of 3D sys- their active involvement in each and every area of technology tem integration. innovation resulting from this industry trend. All the techni- cal articles in this bulletin either deal with 3D integration of integrated circuits or packaging of MEMS and sensors using wafer level techniques, and all of them demonstrate how the SET bonders can be adequately used with varying process parameters: die to die bonding or die to wafer bonding, cop- per tin or gold tin or solder alloys, with flux or flux-less, with a wide range of die and wafer thicknesses, within front-end or back-end factory environments. Thanks to the equipment flexibility, recipes combining the right placement accuracy, compression duration, force and temperature can be defined to meet the requirements of bon- ding strength and reliability with high industrial throughput.
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