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Reversible Computing: the Design of an Adiabatic REVERSIBLE COMPUTING: THE DESIGN OF AN ADIABATIC MICROPROCESSOR A Thesis Submitted to the Graduate School of the University of Notre Dame in Partial Fulfillment of the Requirements for the Degree of Master of Science in Electrical Engineering by Rene Celis Cordova Gregory L. Snider, Co-Director Alexei O. Orlov, Co-Director Graduate Program in Electrical Engineering Notre Dame, Indiana November 2019 © Copyright 2019 Rene Celis Cordova REVERSIBLE COMPUTING: THE DESIGN OF AN ADIABATIC MICROPROCESSOR Abstract by Rene Celis Cordova Despite the exponential progress over the past fifty years the increase of performance of microprocessors has recently come to a rather abrupt end. Modern microprocessors are limited by heat dissipation. Speeds have been capped around 4 GHz since 2004 to limit heat generation. Such speeds are well below the RC time constant limit of the circuits, sacrificing speed to prevent the chips from melting. Reversible computing is a viable alternative to traditional circuit implementations since it reduces heat generation by avoiding unnecessary dissipation. Traditional CMOS circuits dissipate power on every switching in the form of heat. Adiabatic reversible computing uses reversible logic and quasi-adiabatic transitions to reduce heat generation by introducing a trade-off between speed and power. By using reversible logic and switching the circuits slowly, relative to their RC time constants, power can be dramatically reduced. In this thesis, I will present the design of a 16-bit adiabatic microprocessor that operates at 0.5 GHz dissipating an energy one order of magnitude lower than its CMOS counterpart. Rene Celis Cordova The adiabatic microprocessor is a multicycle RISC processor with a 16-bit datapath and it follows the MIPS architecture. Only a subset of instructions is implemented but they are sufficient for universal computation. Adiabatic reversible logic is achieved using split-rail charge recovery logic (SCRL) with Bennett clocking, which consists of clocks that only ramp up once the previous stage has a valid steady state. An adiabatic SCRL implementation allows a circuit to operate both in adiabatic and in standard CMOS mode. The adiabatic microprocessor design includes on-chip temperature sensors that directly measure heat dissipation and provide a direct comparison of the power between the two modes of operation. The 16-bit adiabatic microprocessor is successfully implemented in 90 nm technology with an operating frequency of 0.5 GHz, which demonstrates the design of a real-life circuit using adiabatic reversible logic and shows a promising future for energy- efficient computing. This is for my family, who encouraged me to pursue my dreams. ii CONTENTS Figures..................................................................................................................................v Tables ................................................................................................................................ vii Acknowledgments............................................................................................................ viii Chapter 1: Introduction ........................................................................................................1 1.1 Reversible Computing .......................................................................................1 1.1.1 Heat Production in Modern Computing ..............................................1 1.1.2 Landauer’s Principle ...........................................................................3 1.1.3 Quasi-adiabatic Clocking ....................................................................5 1.2 Adiabatic Reversible Computing .......................................................................7 1.2.1 Split-level Charge Recovery Logic (SCRL) .......................................7 1.2.2 Bennett Clocking ................................................................................9 Chapter 2: Adiabatic Reversible Computing Implementation ...........................................10 2.1 Reversible Energy Production Compared to CMOS .......................................10 2.1.1 Shift Register Using SCRL ...............................................................10 2.2 Choice of Technology Node ............................................................................13 2.3 Implementing Adiabatic Digital Circuits .........................................................14 2.3.1 Adiabatic Standard Cell Library .......................................................16 2.4 SCRL Quasi-adiabatic Analysis ......................................................................18 Chapter 3: Reversible 16-bit Microprocessor Design ........................................................22 3.1 Architecture......................................................................................................22 3.1.1 Multi-cycle Operation .......................................................................23 3.1.2 MIPS and Bennett Clocking .............................................................24 3.1.3 Optimizations for Adiabatic Computing ...........................................26 3.2 Novel Memory Elements for Adiabatic Computing ........................................29 3.2.1 Adiabatic Flip-Flops .........................................................................29 3.2.2 Adiabatic SRAM Cells .....................................................................30 3.3 Microprocessor Physical Implementation........................................................32 3.3.1 ALU and Critical Path ......................................................................32 3.3.2 Register File ......................................................................................33 3.3.3 Instruction and Data Fetch ................................................................35 3.3.4 Control Unit ......................................................................................36 3.4 Microprocessor Verification ............................................................................40 iii Chapter 4: Reversible CMOS Heat Dissipation Measurements ........................................41 4.1 On-chip Thermocouples...................................................................................43 4.1.1 Metallic Thermocouples ...................................................................44 4.1.2 Silicon Thermocouples .....................................................................47 4.2 On-chip Diode Temperature Sensors ...............................................................48 Chapter 5: Conclusion and Future Work ...........................................................................51 5.1 Future Work .....................................................................................................52 5.1.1 Fabrication and Testing.....................................................................52 5.2 Microprocessor Scalability ..............................................................................53 Bibliography ......................................................................................................................56 iv FIGURES Figure 1.1: Number of transistors per chip and their clock speeds compared to the year of introduction. Reproduced from [1]. .........................................................................2 Figure 1.2: Block diagram of reversible computing system. Reproduced from [8]. ..........4 Figure 1.3: (a) Adiabatic inverter implemented with SCRL. (b) Timing diagram ..............8 Figure 1.4: Timing diagram of three-level Bennett clocking ..............................................9 Figure 2.1: (a) CMOS shift register. (b) Adiabatic shift register. (c) Energy lost per cycle SPICE simulation comparing both modes of operation using the 90nm technology ................................................................................................................................12 Figure 2.2: Comparison of energy dissipated by an adiabatic shift register implemented in 90nm and 28nm......................................................................................................13 Figure 2.3: (a) Standard CMOS digital logic circuit. (b) Conversion to adiabatic logic of the circuit ...............................................................................................................15 Figure 2.4: (a) Adiabatic two input NAND circuit schematic. (b) NAND physical implementation using 90nm technology ................................................................17 Figure 2.5: (a) Ordinary SCRL logic NAND gate. (b) SPICE simulation shows voltage drop across nodes Output and Vx which leads to undesired dissipation. ..............18 Figure 2.6: (a) Fixed SCRL logic NAND gate. (b) SPICE simulation shows node Vx follows the Output, therefore preventing undesired dissipation. ...........................19 Figure 2.7: Energy losses of ordinary SCRL NAND gate, and fixed-SCRL gate. ............21 Figure 3.1: Multi-cycle MIPS microprocessor main components. Adapted from [36]. ....23 Figure 3.2: MIPS multi-cycle operation state machine, and corresponding states. ...........24 Figure 3.3: Adiabatic microprocessor main components showing three separate Bennett blocks to implement adiabatic logic with Bennett clocking ..................................25 v Figure 3.4: Kogge-Stone adder using propagate-generate logic. Adapted from [36]. .......27 Figure 3.5: Adiabatic 16-bit Kogge-Stone adder layout implemented in 90nm
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