Lecture 26 Structure of a computer

◆ Logistics ◆ Block diagram view ■ Ant extra credit problem due today address ■ Extra lab check-off times read/write Memory µ Monday 12:30-4:20 System µ Tuesday 12:00-2:00 central processing data unit (CPU) ■ All labs must be done by Tuesday 2:00pm ■ Review session Monday 4:30 pm here ■ Final Exam Wednesday 2:30 pm here

◆ Today control signals ■ Computer Organization Overview Control Data Path µ Where some of the things we’ve learned fit in data conditions ■ Review ■ Evaluation: leave last 10-15 min for this – instruction fetch and interpretation FSM – functional units and registers CSE370, Lecture 26 1 CSE370, Lecture 26 2

Registers Instruction sequencing

◆ Selectively loaded – EN or LD input ◆ Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz) ◆ Output enable – OE input ◆ Step 1: get the ADD instruction from memory into an instruction ◆ Multiple registers – group 4 or 8 in parallel register (IR) ◆ Step 2: decode instruction ■ instruction in IR has the code of an ADD instruction ■ register indices used to generate output enables for registers Rx and LD OE OE asserted causes FF state to be Ry D7 Q7 ■ D6 Q6 connected to output pins; otherwise they register index used to generate load signal for register Rz D5 Q5 are left unconnected (high impedance) D4 Q4 ◆ Step 3: execute instruction D3 Q3 D2 Q2 LD asserted during a lo-to-hi clock ■ enable Rx and Ry output and direct to ALU D1 Q1 transition loads new data into FFs ■ setup ALU to perform ADD operation D0 CLK Q0 ■ direct result to Rz so that it can be loaded into register

CSE370, Lecture 26 3 CSE370, Lecture 26 4

Elements of the (aka instruction Instruction types unit)

◆ Data manipulation ◆ Standard FSM elements ■ add, subtract ■ state register ■ next-state logic ■ increment, decrement ■ output logic (/control signalling) ■ multiply ■ Moore or synchronous Mealy machine to avoid loops unbroken by FF ■ shift, rotate ■ immediate operands ◆ Plus additional "control" registers ■ instruction register (IR) ◆ Data staging ■ program (PC) ■ load/store data to/from memory ◆ Inputs/outputs ■ register-to-register move ■ outputs control elements of data path ■ ◆ Control inputs from data path used to alter flow of program (test if zero) ■ conditional/unconditional branches in program flow ■ subroutine call and return

CSE370, Lecture 26 5 CSE370, Lecture 26 6 Instruction execution Data path (hierarchy)

◆ Control state diagram (for each diagram) ◆ Arithmetic circuits constructed in hierarchical and iterative fashion ■ reset Reset ■ each bit in datapath is functionally identical Cin ■ fetch instruction ■ 4-bit, 8-bit, 16-bit, 32-bit , 64-bit ■ decode Init ■ execute Initialize Ain Machine FA Sum ◆ Instructions partitioned into three classes Bin ■ branch ■ load/store Fetch Cout ■ register-to-register Instr. Ain Sum ◆ Different sequence through HA Bin Cout diagram for each HA Load/ Execute Cin instruction type Branch Store Instr. Register- to-Register Branch Branch Taken Not Taken Incr. PC

CSE370, Lecture 26 7 CSE370, Lecture 26 8

Data path (ALU) Data path (ALU + registers)

◆ ALU block diagram ◆ Accumulator ■ input: data and operation to perform ■ special register ■ ■ output: result of operation and status information one of the inputs to ALU ■ output of ALU stored back in accumulator ◆ One-address instructions ■ operation and address of one operand AB ■ other operand and destination 16 16 16 is accumulator register ■ AC ← AC op Mem[addr] REG AC ■ Operation "single address instructions” 16 16 (AC implicit operand) OP 16 ◆ Multiple registers ■ part of instruction used N SZ N to choose register operands 16 Z

CSE370, Lecture 26 9 CSE370, Lecture 26 10

Data path (bit-slice) Instruction path

◆ Bit-slice concept – iterate to build n-bit wide datapaths ◆ ■ keeps track of program execution ■ address of next instruction to read from memory CO ALU CI ■ CO ALU ALU CI may have auto-increment feature or use ALU

AC AC AC ◆ Instruction register ■ current instruction R0 R0 R0 ■ includes ALU operation and address of operand rs rs rs ■ also holds target of jump instruction rt rt rt ■ immediate operands rd rd rd ◆ Relationship to data path from from from memory memory memory ■ PC may be incremented through ALU ■ 1 bit wide 2 bits wide contents of IR may also be required as input to ALU

CSE370, Lecture 26 11 CSE370, Lecture 26 12 Data path (memory interface) Block diagram of processor

◆ Memory ◆ Register transfer view of Princeton architecture ■ separate data and instruction memory () ■ which register outputs are connected to which register inputs µ two address busses, two data busses ■ arrows represent data-flow, other are control signals from control FSM ■ single combined memory (Princeton architecture) ■ MAR may be a simple rather than separate register µ single address , single data bus ■ MBR is split in two (REG and IR) load 16 path ◆ ■ load control for each register Separate memory REG AC ■ ALU output goes to data memory input rd wr 16 16 store data ■ path register input from data memory output OP Data Memory ■ data memory address from instruction register (16-bit words) addr ■ instruction register from instruction memory output N 8 ■ Z instruction memory address from program counter Control MAR FSM 16 ◆ Single memory ■ address from PC or IR IR PC 16 16 ■ memory output to instruction and data registers ■ memory input from ALU output OP 16 CSE370, Lecture 26 13 CSE370, Lecture 26 14

Block diagram of processor “Why” take CSE 370

◆ Required (okay, but let’s talk about why it is required and will be ◆ Register transfer view of Harvard architecture useful for your future) ■ which register outputs are connected to which register inputs ■ arrows represent data-flow, other are control signals from control FSM ◆ Most basic building blocks of computer science (0’s and 1’s) ■ two MARs (PC and IR) load ◆ path It is important to understand how they are used as baseline for ■ two MBRs (REG and IR) 16 more complex operations (adding, storing, other logic like ■ load control for each register REG AC rd wr if/while) 16 16 store path data ◆ It is good to understand what can be implemented in hardware, OP Data Memory (16-bit words) and why it is sometimes good to implement certain things in addr N 16 hardware instead of software Z ◆ Control Understand how some of the technology you interact with on FSM 16 daily basis (memory stick, vending machine, etc) at the hardware IR PC data logic level. 16 16 Inst Memory (8-bit words) ◆ Knowledge gained in this course is used directly in OP addr industry/research 16 CSE370, Lecture 26 15 CSE370, Lecture 26 16

What you should know What you should know

◆ basics ◆ Combinational logic applications ■ Binary/hex/decimal numbers ■ Combinational design ■ Ones and twos complement arithmetic µ Input/output encoding ■ Truth tables µ Truth table ■ Boolean algebra µ K-map µ Boolean equation 4529 ■ Basic logic gates I like Pink and Blue but not Yellow … + 34532 µ Schematics ------■ Schematic diagrams ???? ■ /demultiplexers ■ Timing diagrams ■ PLAs/PALs ■ de Morgan's theorem ■ ROMs ■ AND/OR to NAND/NOR logic conversion ■ Adders ■ K-maps (up to 4 variables), logic minimization, don't cares ■ SOP, POS ■ Minterm and maxterm expansions (canonical, minimized)

CSE370, Lecture 26 17 CSE370, Lecture 26 18 What you should know What you should know

◆ building blocks ◆ Counters ■ Latches (R-S and D) ■ Timing diagrams ■ Flip- (D and T) ■ Shift registers ■ Latch and flip-flop timing (setup/hold time, prop delay) ■ Ring counters ■ Timing diagrams ■ State diagrams and state-transition tables ■ Asynchronous inputs and metastability ■ Counter design procedure ■ Registers 1. Draw a state diagram 2. Draw a state-transition table Remember that 1, 2, 3, 4, … the last number was 1 3. Encode the next-state functions 4. Implement the design ■ Self-starting counters

CSE370, Lecture 26 19 CSE370, Lecture 26 20

What you should know (Final exam focus is What you should know (Final exam focus is here though exam is cumulative) here though exam is cumulative)

◆ Finite state machines ◆ Finite state machines and Verilog ■ Timing diagrams (synchronous FSMs) ■ Understanding simple Verilog ■ Moore versus Mealy versus synchronized/registered Mealy ■ Expressing Moore and Mealy machines in sequential Verilog ■ ■ FSM design procedure The last coin was 5cents and Understanding Verilog descriptions of finite state machines 1. State diagram already had 10cents deposited expressed in standard stylized formats so let’s pop out a coffee 2. state-transition table 3. State minimization

4. State encoding Food! ◆ Other 5. Next-state logic minimization ■ start Pipelining and Retiming 6. Implement the design ■ State minimization ■ One-hot / output-oriented encoding ■ State partitioning ■ FSM design guidelines µ Separate datapath and control

CSE370, Lecture 26 21 CSE370, Lecture 26 22

Final exam logistics Thank you

◆ 2:30 – 4:20 (1 hour and 45 minutes long) ◆ Materials: cumulative but more focus on later material Thank you for making teaching this course fun HW7, HW8. I hope you enjoyed the course ◆ Closed book/notes, no calculator Send me an email or drop in for questions about CSE, etc. ◆ Scratch papers provided ◆ Just have your pencil/pen and eraser Good luck on your final exams! ◆ Raise hand for questions (don’t walk to get help)

CSE370, Lecture 26 23 CSE370, Lecture 26 24