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UG018 Powerpc 405 Processor Block Reference Guide

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UG018 Powerpc 405 Processor Block Reference Guide PowerPC 405 Processor Block Reference Guide Embedded Development Kit UG018 (v2.1) July 20, 2005 R R Xilinx is disclosing this Specification to you solely for use in the development of designs to operate on Xilinx FPGAs. Except as stated herein, none of the Specification may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of this Specification may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Specification; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Specification. Xilinx reserves the right to make changes, at any time, to the Specification as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Specification. THE SPECIFICATION IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE SPECIFICATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD- PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE SPECIFICATION, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE SPECIFICATION, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE SPECIFICATION. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE SPECIFICATION TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Specification is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Specification in such High-Risk Applications is fully at your risk. © 2002-2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 09/16/02 1.0 Initial Embedded Development Kit (EDK) release. 09/02/03 1.1 Updated for EDK 6.1 release PowerPC 405 Processor Block Reference Guide www.xilinx.com UG018 (v2.1) July 20, 2005 Date Version Revision 08/20/04 2.0 Updated to include Virtex-4 functionality. 07/20/05 2.1 • Updated Table 2-24, JTAG Instruction Register length for Virtex-4 devices: FX12, FX40, FX60. • Added (Virtex-4 only) DCREMACENABLER output port to Figure 2-29 and Table B-1. Added (Virtex-4 only) parity error detection sections for instruction cache, data cache and unified translation lookaside buffer. Introduced new privileged registers (Virtex-4 only) Core Configuration Register 1 (CCR1) and Machine Check Syndrome Register (MCSR). • Completely revised “PowerPC 405 APU Controller” in Chapter 4 including adding descriptions to figures and an entirely new section: “Flushed FCM Instructions”. UG018 (v2.1) July 20, 2005 www.xilinx.com PowerPC 405 Processor Block Reference Guide PowerPC 405 Processor Block Reference Guide www.xilinx.com UG018 (v2.1) July 20, 2005 Table of Contents Revision History . 2 Preface: About This Guide Guide Contents . 9 Additional Resources . 10 Conventions . 10 Typographical. 10 Online Document . 11 General Conventions . 12 Registers . 12 Terms. 13 Chapter 1: Introduction to the PowerPC 405 Processor PowerPC Architecture . 17 PowerPC Embedded-Environment Architecture . 18 PowerPC 405 Software Features . 21 Privilege Modes . 22 Address Translation Modes . 23 Addressing Modes . 23 Data Types . 23 Register Set Summary . 24 PowerPC 405 Hardware Organization. 26 Central-Processing Unit . 27 Exception Handling Logic . 27 Memory Management Unit . 27 Instruction and Data Caches . 29 Timer Resources . 30 Debug. 30 PowerPC 405 Interfaces. 31 PowerPC 405 Performance. 32 Chapter 2: Input/Output Interfaces Signal Naming Conventions. 34 Clock and Power Management Interface . 35 CPM Interface I/O Signal Summary . 36 CPM Interface I/O Signal Descriptions . 37 System Design Considerations for Clock Domains . 39 CPU Control Interface. 41 CPU Control Interface I/O Signal Summary . 41 CPU Control Interface I/O Signal Descriptions . 42 Reset Interface . 43 Reset Requirements . 43 Reset Interface I/O Signal Summary . 44 PowerPC 405 Processor Block Reference Guide www.xilinx.com 5 UG018 (v2.1) July 20, 2005 R Reset Interface I/O Signal Descriptions . 45 Instruction-Side Processor Local Bus Interface . 47 Instruction-Side PLB Operation . 47 Instruction-Side PLB I/O Signal Table . 50 Instruction-Side PLB Interface I/O Signal Descriptions . 51 Instruction-Side PLB Interface Timing Diagrams . 59 Data-Side Processor Local Bus Interface . 69 Data-Side PLB Operation . 69 Data-Side PLB Interface I/O Signal Table . 72 Data-Side PLB Interface I/O Signal Descriptions . 74 Data-Side PLB Interface Timing Diagrams . 86 Device-Control Register Interfaces . 99 Internal Device Control Register (DCR) Interface . 100 Virtex-II Pro and Virtex-II ProX Processor Blocks . 100 Virtex-4-FX Processor Blocks . 101 External DCR Bus Interface . 102 External DCR Bus Interface I/O Signal Summary . 105 External DCR Bus Interface I/O Signal Descriptions . 106 External DCR Bus Interface Timing Diagrams . 107 External DCR Timing Consideration (Virtex-II Pro/ProX Only) . 110 External Interrupt Controller Interface. ..
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