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MIPS Architecture with Tomasulo Algorithm [12] CALIFORNIA STATE UNIVERSITY NORTHRIDGE TOMASULO ARCHITECTURE BASED MIPS PROCESSOR A graduate project submitted in partial fulfilment for the requirement Of the degree of Master of Science In Electrical Engineering By Sameer S Pandit May 2014 The graduate project of Sameer Pandit is approved by: ______________________________________ ____________ Dr. Ali Amini, Ph.D. Date _______________________________________ ____________ Dr. Shahnam Mirzaei, Ph.D. Date _______________________________________ ____________ Dr. Ramin Roosta, Ph.D., Chair Date California State University Northridge ii ACKNOWLEDGEMENT I would like to express my gratitude towards all the members of the project committee and would like to thank them for their continuous support and mentoring me for every step that I have taken towards the completion of this project. Dr. Roosta, for his guidance, Dr. Shahnam for his ideas, and Dr. Ali Amini for his utmost support. I would also like to thank my family and friends for their love, care and support through all the tough times during my graduation. iii Table of Contents SIGNATURE PAGE .......................................................................................................... ii ACKNOWLEDGEMENT ................................................................................................. iii LIST OF FIGURES .......................................................................................................... vii ABSTRACT ........................................................................................................................ x Chapter 1: Introduction ....................................................................................................... 1 1.1 Introduction to RISC and CISC ........................................................................... 1 1.1.1 RISC versus CISC .............................................................................................. 2 1.1.2 CISC Architecture .............................................................................................. 3 1.1.3 RISC Architecture .............................................................................................. 4 1.1.4 Performance Equation ........................................................................................ 6 Chapter 2: Types of CPU .................................................................................................... 7 2.1 Single-Cycle CPU Method ........................................................................................ 7 2.2 Instruction Formats ................................................................................................... 8 R-Type Instruction Format .......................................................................................... 9 I-Type Instruction Format ......................................................................................... 11 Branch Instruction ..................................................................................................... 12 J-Type Instruction Format ......................................................................................... 12 2.3 Multi Cycle CPU ..................................................................................................... 13 iv Chapter 3: Pipelining and MIPS ....................................................................................... 16 3.1 Pipelining ................................................................................................................ 16 3.2 The Classic 5 Stage Pipelined Processor................................................................. 17 3.3 Pipeline Hazards ...................................................................................................... 18 3.4 Data Forwarding ...................................................................................................... 19 3.5 MIPS Implementation ............................................................................................. 21 3.5.1 Instruction Fetch ............................................................................................... 23 3.5.2 Instruction Decode ............................................................................................ 24 3.5.3 Execute Stage ................................................................................................... 25 3.5.4 Memory stage ................................................................................................... 26 3.5.5 Write Back Stage .............................................................................................. 27 3.5.6 ALU and Control to Complete MIPS ............................................................... 27 Chapter 4: Dynamic Scheduling ....................................................................................... 31 4.1 Types of scheduling ................................................................................................ 31 4.2 Types of Data Hazards ............................................................................................ 32 4.3 The Tomasulo Approach ......................................................................................... 33 4.3.1 Register Renaming ........................................................................................... 37 4.4 Working Example of Tomasulo .............................................................................. 39 Chapter 5: Simulation and Synthesis ................................................................................ 47 5.1 Simulation using ModelSim .................................................................................... 47 v 5.2 Simulation using Synopsys VCS............................................................................. 55 5.3 Synthesis Results ..................................................................................................... 60 Chapter 6: Conclusion and Modifications ........................................................................ 63 6.1 Conclusion ............................................................................................................... 63 6.2 Modifications .......................................................................................................... 63 References ......................................................................................................................... 65 Appendix A: Code Listing and Synthesis Scripts ............................................................. 67 Appendix B: Simulation waveforms showing all Operations........................................... 72 vi LIST OF FIGURES Figure 1: Storage scheme of a generic Computer ............................................................... 2 Figure 2: Single-Cycle Method [5] ..................................................................................... 7 Figure 3: R-Type Register Format [6] ................................................................................ 9 Figure 4: Data Path for R-Type format [7] ....................................................................... 10 Figure 5: I-Type Instruction Format [8]............................................................................ 11 Figure 6: I-Type Data Path [9] .......................................................................................... 11 Figure 7: J-Type Instruction Format ................................................................................. 12 Figure 8: Data Path for Jump Instruction Format [9] ....................................................... 13 Figure 9: Multi Cycle CPU Data Path [5] ......................................................................... 14 Figure 10: A Pipelined RISC Data Path ........................................................................... 18 Figure 11: Forwarding Path for the above example. [10] ................................................. 21 Figure 12: 5 Stage Pipelined MIPS [11] ........................................................................... 22 Figure 13: IF Data Path ..................................................................................................... 23 Figure 14: ID Data Path .................................................................................................... 24 Figure 15: EX Data Path ................................................................................................... 25 Figure 16: MEM Data Path ............................................................................................... 26 Figure 17: MIPS after appending ALU Control [12]........................................................ 28 Figure 18: Controller in MIPS .......................................................................................... 29 Figure 19: 5 Stage Pipelined MIPS Processor [12] .......................................................... 30 Figure 20: MIPS architecture with Tomasulo Algorithm [12] ......................................... 36 Figure 21: Tomasulo Example - Clock Cycle 0 ................................................................ 39 Figure 22: Tomasulo Example - Clock Cycle 1 ................................................................ 40 vii Figure 23: Tomasulo Example - Clock Cycle 2 ................................................................ 41 Figure 24: Tomasulo Example - Clock Cycle 3 ................................................................ 41 Figure 25: Tomasulo Example - Clock Cycle 4 ...............................................................
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