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United States Patent (19) 11 Patent Number: 5,680,565 Glew Et Al

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United States Patent (19) 11 Patent Number: 5,680,565 Glew Et Al USOO568.0565A United States Patent (19) 11 Patent Number: 5,680,565 Glew et al. 45 Date of Patent: Oct. 21, 1997 (54) METHOD AND APPARATUS FOR Diefendorff, "Organization of the Motorola 88110 Super PERFORMING PAGE TABLE WALKS INA scalar RISC Microprocessor.” IEEE Micro, Apr. 1996, pp. MCROPROCESSOR CAPABLE OF 40-63. PROCESSING SPECULATIVE Yeager, Kenneth C. "The MIPS R10000 Superscalar Micro INSTRUCTIONS processor.” IEEE Micro, Apr. 1996, pp. 28-40 Apr. 1996. 75 Inventors: Andy Glew, Hillsboro; Glenn Hinton; Smotherman et al. "Instruction Scheduling for the Motorola Haitham Akkary, both of Portland, all 88.110" Microarchitecture 1993 International Symposium, of Oreg. pp. 257-262. Circello et al., “The Motorola 68060 Microprocessor.” 73) Assignee: Intel Corporation, Santa Clara, Calif. COMPCON IEEE Comp. Soc. Int'l Conf., Spring 1993, pp. 73-78. 21 Appl. No.: 176,363 "Superscalar Microprocessor Design" by Mike Johnson, Advanced Micro Devices, Prentice Hall, 1991. 22 Filed: Dec. 30, 1993 Popescu, et al., "The Metaflow Architecture.” IEEE Micro, (51) Int. C. G06F 12/12 pp. 10-13 and 63–73, Jun. 1991. 52 U.S. Cl. ........................... 395/415: 395/800; 395/383 Primary Examiner-David K. Moore 58) Field of Search .................................. 395/400, 375, Assistant Examiner-Kevin Verbrugge 395/800, 414, 415, 421.03 Attorney, Agent, or Firm-Blakely, Sokoloff, Taylor & 56 References Cited Zafiman U.S. PATENT DOCUMENTS 57 ABSTRACT 5,136,697 8/1992 Johnson .................................. 395/586 A page table walk is performed in response to a data 5,226,126 7/1993 McFarland et al. 395/.394 translation lookaside buffer miss based on a speculative 5,230,068 7/1993 Van Dyke et al. .. 395/464 memory instruction. In the event of a data translation 5,313,634 5/1994 Eickemeyer ........ ... 395/587 lookaside buffer miss, a page miss handler determines 5,327547 7/1994 Stiles et al. ........ ... 395/464 whether the memory micro-instruction causing the miss is a 5,377,336 12/1994 Eickemeyer et al. - 395/383 speculative or non-speculative micro-instruction. If non 5,381,533 1/1995 Peleg et al. ......... ... 395,391 5,394,529 2/1995 Brown, III et al. 395/587 speculative, the page miss handler performs a non 5,404,467 4/1995 Saba et al. .......... 395/383 speculative page table walk. If the memory micro 5,421,022 5/1995 McKeen et al. ... 395/800 instruction causing the miss is a speculative micro 5,442,766 8/1995 Chu et al. ....... ... 395/414 instruction, the page miss handler initiates a speculative 5,553,255 9/1996 Jain et al. ... 395/582 page table walk. While performing the speculative page table walk, the page miss handler determines whether page OTHER PUBLICATIONS table memory accessed during the page table walkis specu Asprey et al. "Performance Features of the PAT100 Micro lateable or non-speculateable memory. If non-speculateable, processor" IEEE Micro, Jun. 1993, pp.22-35. the speculative page table walk is aborted. A micro Knebel et al. "HP's PA7100LC: A Low-Cost SuperScalar instruction assisted page table walk is performed whenever PA-RISC Processor.” COMPCON IEEE Comp. Soc. Int'l access or dirty bits must be set for the pages accessed in the Conf., 1993, pp. 441-447. page table walk. Moore, "The PowerPC 601 Microprocessor.” COMPCON IEEE Comp. Soc. Int’l Conf. 1993, pp. 109-116. 27 Claims, 9 Drawing Sheets O3R8first ifesparent No Perry Non-speciate Yelagisting peries er LPridPEld 2 218 sPagetateers Corporcing to the Paisrt Psi PNon-specital of is Pencrgetirement Fetid 22 22. Perfor Spellabye pagitable Walk langsued and TEids(Figure5 28 U.S. Patent Oct. 21, 1997 Sheet 1 of 9 5,680,565 JOSS000Ido10|WOJOSS000Ido10||NGOJOSS300/d010|W snguJe?SÁS WJOSS000Id010|W ÕÕI U.S. Patent Oct. 21, 1997 Sheet 2 of 9 5,680,565 Extemal Memory 10 130 Data Cache Unit 124 I/O Device Page Miss Handler 128 MTRR'S 129 Data Translation Lookaside Buffer 126 Memory | Ordering Buffer Memory System 122 !----------------------------- System Bus 108 Address Generation Unit 116 ------------------------------- Reang ReservationStation 120 1181 : i instruction Fetch CP, Bus }| and issue Unit 114 Out-of-Order Engine 113 : U.S. Patent Oct. 21, 1997 Sheet 3 of 9 5,680,565 FIG. 3 Memory OpCOde Type Linearr" Address | PraguePhysical Address asPost ATRETIREMENT N-134 141 U.S. Patent Oct. 21, 1997 Sheet 4 of 9 5,680,565 nstruction FetC and DeCode Unit SSues a Parent uOP 200 FIG. 4 RSAIOCates Parent UOP 202 RS Dispatches ROB ReOrders and Parent UOP Retires Parent uOP With Walid PdSt 214 204 AGU Generates DCU. Executes Linear Address Parent UOP 206 212 Return Physical D. YeS Address from DTLB 210 NO Store Physical PHM Address G Determined from Redispatches Parent Stuffed PDE and PTE L0ads Page Table Memory Load 218 Walkin DTLB 222 20 Corresponding to the Parent HOld Parent UOP uOP, Non-speculatable or is Pending Retirement a Fault Detected? 226 224 Perform Speculative Page Table Walk by issuing Stuffed PDE and PTE Loads (Figure 5) 228 U.S. Patent Oct. 21, 1997 Sheet 5 of 9 5,680,565 PMH Successively Dispatches Stuffed F G 5 PDE and PTE LOads 230 PMH Redispatches Ordering Conflict Parent uOP With Detected by MOB or Y PMH Squashes Non-speculatable Access Or Dirty Bit S. Stuffed load Designation Thus Assist Required? 234 Causing MOB to 232 Block Redispatched UOP Until Retirement 236 DCU Squashes PMH Re-Dispatches Stuffed Load? Squashed Stuffed Load 238 Yes 240 NO Access or Dirty Bit DCUPrOCesses Assist Required? Stuffed LOad and 237 Returns Data for Stuffed LOad to PMH TO Block 218 Yes Either From Internal of Figure 4 Perform MicroaSSist Cache Or From Page Table Walk External Memory (Figure 6) 242 239 Page Table Walk Complete? NO 244 Yes PMHDetermines Physical Address Based On PTE and PDE Data 246 To Block 220 of Figure 4 U.S. Patent Oct. 21, 1997 Sheet 6 of 9 5,680,565 MicroCOde Generates Micro-aSSist PDE UOPS for Steering PMHinto Performing a Page Table Walk and Set an ACCess F G 6 Or Dirty Bit with the PDE 248 AllOCate Micro-assist UOPS in RS 250 RS Dispatches On a DTLB Miss, PMH Microassist UOP Computes Physical Address Micro-COce (AGUBypassed) for the Micro-assist uOP's Generates 252 and Redispatches uOP Micro-assist With Walid PDST PTE UOP's 253 for Steering DCU Squashes? re PMH to 254 PMH Re-dispatches E. Micro-assist UOP W aOeand able Set DCUPrOCeSSeS 256 an ACCeSS Or Micro-assist Load Dirty Bit and Returns Data Within the for Micro-assist Load to PMH, RS and ROB PTE 258 Fault Detected? Yes Bros.ault To Block 208 260 268 of Figure 4 No Set Access or Dirty Bit 264 PMHDetermines TableMicro-assist Walk Compete? Page Yes-BasedPhysical on Address PTE TO BOCK 220 266 and PDE Data of Figure 4 268 U.S. Patent Oct. 21, 1997 Sheet 8 of 9 5,680,565 [100] pl|pueEldUp??dsp U.S. Patent Oct. 21, 1997 Sheet 9 of 9 5,680,565 5,680,565 1 2 METHOD AND APPARATUS FOR tively executed instructions are merely committed to PERFORMING PAGE TABLE WALKS INA memory, i.e., the speculative instructions are "retired”. If the MCROPROCESSOR CAPABLE OF branch prediction is found to be incorrect, then the specu PROCESSING SPECULATIVE latively executed instructions must be flushed from the NSTRUCTIONS system. As can be appreciated, the capability of performing opera tions speculatively can result in a great windfall in process BACKGROUND OF THE INVENTON ing speed. Since the microprocessor need not wait for a 1. Field of the Invention branch condition to be resolved prior to executing subse The invention generally relates to computer systems and O quent instructions. The advantages of performing operations in particular, to the execution of page table walks within a out-of-order or speculatively is ideally exploited in micro computer system capable of performing speculative memory processors which are also capable of pipelined executions access operations. wherein two or more operations are performed simulta 2. Description of Related Art neously. Current state of the art microprocessors typically include 15 Microprocessors capable of out-of-order or speculative one or more components for facilitating the processing of execution of instructions are described in "Superscalar memory access operations. One such component is a data Microprocessor Design" by Mike Johnson, Prentice-Hall, cache unit ("DCU") which stores a portion of data within a Inc. 1991. high speed memory. Typically, data from the most recently 20 Although speculative processing has considerable advan accessed external memory locations are stored within the tages over non-speculative processing, certain difficulties DCU such that, if access to the data is required again, the arise in implementing a page table walk within micropro data need not necessarily be retrieved from external cessors capable of speculative execution. For example, if a memory. Another component commonly employed is a TLB miss is detected for a speculative memory instruction, translation lookaside buffer (“TLB") which caches linear 25 a question arises as to whether a page table walk should be addresses and corresponding physical addresses for use in performed speculatively or deferred until all preceding microprocessors wherein data is internally processed using instructions have retired. The present invention is drawn, in only linear addresses. The TLB is used in connection with a part, to solving problems which arise in performing page page miss handler ("PMH") which performs a translation of table walks within microprocessors capable of speculative or a linear address to a physical address for those addresses not 30 out-of-order execution of memory instructions. cached within the TLB.
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