1 STANDARD COMBINATIONAL MODULES

• DECODERS

• ENCODERS

(Selectors)

• DEMULTIPLEXERS (Distributors)

• SHIFTERS

Introduction to Digital Systems 9 – Standard Combinational Modules 2 BINARY DECODERS

HIGH-LEVEL DESCRIPTION:

Inputs: x = (xn−1, . . . , x0), xj ∈ {0, 1} Enable E ∈ {0, 1} Outputs: y = (y2n−1, . . . , y0), yi ∈ {0, 1}

 1 if (x = i) and (E = 1)  Function: yi =  otherwise  0 

n−1 j x = X xj2 j=0 and i = 0, . . . , 2n − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 3

E y En 0 0 y 1 1 y x 2 0 0 2

x 1 1 Inputs Outputs x n-1 n-1

n-Input Binary Decoder n-Input Binary y n n 2 -1 2 -1

Figure 9.1: n-INPUT BINARY DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 4 EXAMPLE 9.1: 3-INPUT BINARY DECODER

E x2 x1 x0 x y7 y6 y5 y4 y3 y2 y1 y0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 0 2 0 0 0 0 0 1 0 0 1 0 1 1 3 0 0 0 0 1 0 0 0 1 1 0 0 4 0 0 0 1 0 0 0 0 1 1 0 1 5 0 0 1 0 0 0 0 0 1 1 1 0 6 0 1 0 0 0 0 0 0 1 1 1 1 7 1 0 0 0 0 0 0 0 0 - - - - 0 0 0 0 0 0 0 0 BINARY SPECIFICATION:

Inputs: x = (xn−1, . . . , x0), xj ∈ {0, 1} E ∈ {0, 1} Outputs: y = (y2n−1, . . . , y0), yi ∈ {0, 1}

n Function: yi = E · mi(x) , i = 0, . . . , 2 − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 5 EXAMPLE 9.2: IMPLEMENTATION OF 2-INPUT DECODER

0 0 0 0 y0 = x1x0E y1 = x1x0E y2 = x1x0E y3 = x1x0E

E

y 0

x y 0 1

y x 2 1 y 3

Figure 9.2: GATE NETWORK IMPLEMENTATION OF 2-INPUT BINARY DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 6 DECODER USES

OPCODE field

Instruction Other fields

4-Input Binary E=1 En Decoder

15 . . . 4 3 2 1 0

LOAD STORE ADD Decoded operations JUMP

Figure 9.3: OPERATION DECODING.

Introduction to Digital Systems 9 – Standard Combinational Modules 7 DECODER USES

Cell referenced when address is Data input Data input 00000000000010 Binary cell

E=1

0 1 Address 14 14 2 RAM Module Address 14 (2 x 1) 16383 Binary Decoder

Read/write

Read/write Data output

(a) (b) Data output

Figure 9.4: RANDOM ACCESS MEMORY (RAM): a) MODULE; b) ADDRESSING OF BINARY CELLS.

Introduction to Digital Systems 9 – Standard Combinational Modules 8 BINARY DECODER AND or GATE

• UNIVERSAL

Example 9.5:

x2x1x0 z2 z1 z0 000 0 1 0 001 1 0 0 010 0 0 1 011 0 1 0 100 0 0 1 101 1 0 1 110 0 0 0 111 1 0 0

Introduction to Digital Systems 9 – Standard Combinational Modules 9

(y7, . . . , y0) = dec(x2, x1, x0, 1) z2(x2, x1, x0) = y1 y5 y7 z1(x2, x1, x0) = y0 y3 z0(x2, x1, x0) = y2 y4 y5

E=1 y 0 En 0 y 1 1 y z 2 2 2 x 0 y 0 3 3 x y z 1 1 4 1 4 x 2 y 2 5 Binary Decoder 5 y z 6 0 6 y 7 7

Figure 9.5: NETWORK IN EXAMPLE 9.5

Introduction to Digital Systems 9 – Standard Combinational Modules 10 DECODER NETWORKS: COINCIDENT DECODING

x = (xleft, xright)

xleft = (x7, x6, x5, x4) xright = (x3, x2, x1, x0) 4 x = 2 × xleft + xright

y = DEC(xleft) w = DEC(xright)

zi = AND(ys, wt)

i = 24 × s + t

Introduction to Digital Systems 9 – Standard Combinational Modules 11

x3 x2 x1 x0 0 1 0 0 4-Input Binary 1 En Decoder 15 . . .4 3 2 1 0

w 4 1

z0

x4 0 1 y x5 2 0 1 x6 Decoder 0 z36 x7 4-Input Binary

En 0 15 . . . 2 1 1

E

z255

Figure 9.6: 8-INPUT COINCIDENT DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 12 n-INPUT COINCIDENT DECODER

y = dec(xleft, E)

w = dec(xright, 1)

and and and z = ( (y2n/2−1, w2n/2−1), . . . , (ys, wt), . . . , (y0, w0))

Introduction to Digital Systems 9 – Standard Combinational Modules 13

x n/2-1 x0

1 En DECODER W

w n/2 w 2 -1 0 wt

z0 y0

xn/2

ys x n-1 DECODER Y

En z n/2 y n/2 2 s+t 2 -1 E

z n 2 - 1

Figure 9.7: n-INPUT COINCIDENT DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 14 TREE DECODING

x = (xleft, xright)

xleft = (x3, x2)

xright = (x1, x0)

Introduction to Digital Systems 9 – Standard Combinational Modules 15 4-INPUT TREE DECODER

x x x3 x2 1 0 x=6: 0 1 1 0

1 0 Level 1 E En DEC 3 2 1 0

0 0 1 0

1 0 En 1 0 En 1 0 En 1 0 En Level 2 DEC 3 DEC 2 DEC 1 DEC 0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

z z z z 15 12 8 z6 =1 z4 0

Figure 9.8: 4-INPUT TREE DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 16 n-INPUT TREE DECODERr

w = dec(xleft, E)

dec dec dec z = ( (xright, w2n/2−1), . . . , (xright, wt), . . . , (xright, w0))

Introduction to Digital Systems 9 – Standard Combinational Modules 17

x x left right

x n-1 xn/2 x n/2-1 x0

E En Level 1 DEC

w n/2 2 - 1 w0 wt

En En En n/2 Level 2 DEC 2 -1 DEC t DEC 0

z n z (n/2) z 2 - 1 2 t+s 0

Figure 9.9: n-INPUT TWO-LEVEL TREE DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 18 COMPARISON OF DECODER NETWORKS

Coincident Tree Decoder modules 2 2k + 1 and gates 22k – Load per network input 1 decoder input 2k decoder inputs (max) Fanout per decoder output 2k and inputs 1 enable input Number of module inputs 2k + 2 + 22k+1 1 + k + 2k + k2k (related to number of connections) Delay tdecoder + tAND 2tdecoder

Introduction to Digital Systems 9 – Standard Combinational Modules 19 EXAMPLE 9.6: 6-INPUT DECODER

E x 0 0 z0 x 1 1 z x0 0 0 x z z 2 1 x 1 1 Decoder 7 1 E x 2 z Decoder 7 7 0 x3 1

1 x4 x5

Decoder 7

x3 0 1 0 z56 x4 1 z57 x5 z63

Decoder 7

Decoder 7 z63 (a) (b)

Figure 9.10: IMPLEMENTATION OF 6-INPUT DECODER. a) COINCIDENT DECODER. b) TREE DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 20 EXAMPLE 9.6 (cont.)

Coincident Tree Decoder modules 2 9 and gates 64 – Load per network input 1 decoder input 8 decoder inputs (max) Fanout per decoder output 8 and inputs 1 enable input Number of module inputs 136 36 Delay 3d 4d

Introduction to Digital Systems 9 – Standard Combinational Modules 21

Decoder Cell array

Data input Binary cell

E=1 0

0 1 1 12 2 2

Address

Tree Decoder 4095

4096 lines from decoder to cell array 4095

Read/write Data output (a)

Figure 9.11: a) SYSTEM WITH TREE DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 22

Decoder E=1 Cell array Data input

0 6 0 Binary

Decoder 63 1

12

Address E=1

0 6 Binary

Decoder 63 4095

Read/write 128 lines from decoder Modified binary cell Data output to cell array

equivalent to coincident decoder

(b)

Figure 9.11: b) SYSTEM WITH COINCIDENT DECODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 23 BINARY ENCODERS

E

En

x 0 0 x y 1 1 0 0 y 1 1 Inputs y n-1 Outputs n-1 -Input Binary Encoder n 2 x n n 2 -1 2 -1 Ac

A

Figure 9.12: 2n-INPUT BINARY ENCODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 24 BINARY ENCODER: HIGH-LEVEL SPECIFICATION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}, with at most one xi = 1 E ∈ {0, 1} Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1} A ∈ {0, 1}

 i if (x = 1) and (E = 1)  i Function: y =  otherwise  0   1 if (some x = 1) and (E = 1)  i A =  otherwise  0 

n−1 j y = X yj2 j=0 and i = 0, . . . , 2n − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 25 EXAMPLE 9.7: FUNCTION OF AN 8-INPUT BINARY ENCODER

E x7 x6 x5 x4 x3 x2 x1 x0 y y2 y1 y0 A 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 1 0 0 2 0 1 0 1 1 0 0 0 0 1 0 0 0 3 0 1 1 1 1 0 0 0 1 0 0 0 0 4 1 0 0 1 1 0 0 1 0 0 0 0 0 5 1 0 1 1 1 0 1 0 0 0 0 0 0 6 1 1 0 1 1 1 0 0 0 0 0 0 0 7 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ------0 0 0 0 0

Introduction to Digital Systems 9 – Standard Combinational Modules 26 BINARY SPECIFICATION OF ENCODER

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1}, with at most one xi = 1

E ∈ {0, 1}

Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1}

A ∈ {0, 1}

Function: yj = E · P(xk), j = 0, . . . , n − 1

n A = E · P(xi), i = 0, . . . , 2 − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 27 EXAMPLE 9.8

y0 = E · (x1 x3 x5 x7)

y1 = E · (x2 x3 x6 x7)

y2 = E · (x4 x5 x6 x7)

A = E · (x0 x1 x2 x3 x4 x5 x6 x7)

Introduction to Digital Systems 9 – Standard Combinational Modules 28

x x x x x x x x 7 6 5 4 3 2 1 0 E

y0

y1

y2

A

Figure 9.13: IMPLEMENTATION OF AN 8-INPUT BINARY ENCODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 29 USES OF BINARY ENCODERS

Wind direction in unary code 0 0 1 Wind direction 1 in binary code n 0 nw ne 2 0 1 0 3 1 0 w e 0 4 0 2 0 sw se 5 s 0

6 BINARY ENCODER 0 7

Figure 9.14: WIND DIRECTION ENCODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 30 PRIORITY ENCODERS: HIGH-LEVEL DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1} Outputs: y = (yn−1, . . . , y0), yj ∈ {0, 1}

Function:  i if (x = 1) and (x = 0, k > i) and (E = 1)  i k y =  otherwise  0 

 1 if (some x = 1) and (E = 1)  i A =  otherwise  0 

n−1 j y = X yj2 j=0 and i, k ∈ {0, 1, . . . , 2n − 1}

Introduction to Digital Systems 9 – Standard Combinational Modules 31 8-INPUT PRIORITY ENCODER

E x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0 A 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 - 0 0 1 1 1 0 0 0 0 0 1 - - 0 1 0 1 1 0 0 0 0 1 - - - 0 1 1 1 1 0 0 0 1 - - - - 1 0 0 1 1 0 0 1 - - - - - 1 0 1 1 1 0 1 ------1 1 0 1 1 1 ------1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ------0 0 0 0

Introduction to Digital Systems 9 – Standard Combinational Modules 32

E

Lowest En priority z 0 x 0 0 0 0 z x 1 y 1 1 1 1 0 0 y 1 1 Inputs Outputs y n-1 n-1 Priority Resolution Priority Resolution -Input Binary Encoder

z n n x n n n 2 -1 n 2 2 -1 2 -1 2 -1 2 -1 Highest Ac priority A

Figure 9.15: PRIORITY ENCODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 33 PRIORITY RESOLUTION: HIGH-LEVEL AND BINARY-LEVEL DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1} Outputs: z = (z2n−1, . . . , z0), zi ∈ {0, 1}

 1 if (x = 1) and (x = 0, k > i)  i k Function: z =  i 0 otherwise  with i, k = 0, 1, . . . , 2n − 1 • BINARY DESCRIPTION: 0 0 0 n zi = x2n−1x2n−2 . . . xi+1xi , i = 0, 1, . . . , 2 − 1 OR ITERATIVELY

ci−1 = ci xi 0 zi = cixi

Introduction to Digital Systems 9 – Standard Combinational Modules 34

x 0 z 0 c0 x0 z 0 Cell

x x1 1 z z 1 1 c1

x2 z 2 x 2 z x z 2 3 3 c2

x3 z 3

(a) (b)

Figure 9.16: 4-BIT PRIORITY RESOLUTION NETWORKS: a) PARALLEL; b) ITERATIVE.

Introduction to Digital Systems 9 – Standard Combinational Modules 35 USES OF PRIORITY ENCODERS

Request E=1 lines

1 Device A 0 En lowest Highest priority priority request 0 0 Device B 1 0

PROCESSOR 1 1 Device C 2 1 PRIORITY ENCODER

0 3 Device D Ac highest Request present priority A=1

Figure 9.17: RESOLVING INTERRUPT REQUESTS USING A PRIORITY ENCODER.

Introduction to Digital Systems 9 – Standard Combinational Modules 36

E=1 x 7 x 6 x5 x 4 x3 x2 x1 x0 0 0 1 0 1 0 0 1 En 1 0 0 1 1 2 PRIORITY ENCODER

Ac

SHIFTER

(x shifted left 2 positions with 0s inserted into vacated positions) 1 0 1 0 0 1 0 0

Figure 9.18: DETECTING THE LEFTMOST 1 IN A BIT-VECTOR AND REMOVING LEADING ZEROES.

Introduction to Digital Systems 9 – Standard Combinational Modules 37 MULTIPLEXERS (selectors)

• HIGH-LEVEL AND BINARY-LEVEL DESCRIPTION

Inputs: x = (x2n−1, . . . , x0), xi ∈ {0, 1} s = (sn−1, . . . , s0), sj ∈ {0, 1} E ∈ {0, 1} Outputs: z ∈ {0, 1}

 x if E = 1  s Function: z =  if  0 E = 0 

n−1 j s = X sj2 j=0

n 2 −1  z = E ·  X xi · mi(s)  i=0 

Introduction to Digital Systems 9 – Standard Combinational Modules 38

E

x En 0 0 x 1 1

x 2 2 Data output

z Data inputs - Input n 2 x n n 2 -1 2 -1 n-1 0

s n-1 s0 Select inputs

Figure 9.19: 2n-INPUT MULTIPLEXER.

Introduction to Digital Systems 9 – Standard Combinational Modules 39 EXAMPLE 9.11: 4-INPUT MULTIPLEXER

E s1 s0 z 1 0 0 x0 1 0 1 x1 1 1 0 x2 1 1 1 x3 0 - - 0

z = E · (x0m0(s1, s0) x1m1(s1, s0) x2m2(s1, s0) x3m3(s1, s0)) 0 0 0 0 = E · (x0s1s0 x1s1s0 x2s1s0 x3s1s0)

Introduction to Digital Systems 9 – Standard Combinational Modules 40

x 0

x 1

x z 2

x 3

E s s 1 0

Figure 9.20: GATE IMPLEMENTATION OF 4-INPUT MULTIPLEXER

Introduction to Digital Systems 9 – Standard Combinational Modules 41 TYPICAL USES

R0 R1 R0 R2 R3 R4

0 1 2 3 SelA 0 1 SelB MUX A MUX B

For n-bit operands, Mux A and MuxB replicated n times A B and connected to the corresponding bit s of the input vectors. FUNCTIONAL f UNIT

Example: SelA = 1, SelB = 2 Z = f(R1,R3) Z= f(A,B)

Figure 9.21: MULTIPLEXER: EXAMPLE OF USE.

Introduction to Digital Systems 9 – Standard Combinational Modules 42 MULTIPLEXER AS UNIVERSAL COMBINATIONAL MODULE

• connect input variables x to select inputs of multiplexer s

• set data inputs to multiplexer equal to values of function for corresponding assignment of select variables

• using a variable at data inputs reduces size of the multiplexer

Introduction to Digital Systems 9 – Standard Combinational Modules 43 EXAMPLE

E(x2, x1, x0) = X m(1, 2, 4, 6, 7)

0 0 0 0 0 0 0 = x2(x1x0) x2(x1x0) x2(x1x0) x2(x1x0) x2(x1x0)

0 0 = x2m1(x1, x0) x2m2(x1, x0)

x2m0(x1, x0) x2m2(x1, x0) x2m3(x1, x0)

0 = x2m0(x1, x0) x2m1(x1, x0) 1 · m2(x1, x0) x2m3(x1, x0)

Introduction to Digital Systems 9 – Standard Combinational Modules 44 E=1

En 0 0 E=1 1 1 En x 0 1 2 2 x' 2 1 0 3 f = one-set(1,2,4,6,7) f = one-set(1,2,4,6,7) 1 2 1 4 x 3 0 5 2 4 - Input Multiplexer 8 - Input Multiplexer 1 6 1 0 1 7 2 1 0 x x Select 1 0 x x x inputs 2 1 0 (a) (c)

x0 x0

0 1 0 1

x2 x'2 x2 1

x2 1 0 1 1

x1 x1 (b)

Figure 9.22: IMPLEMENTATION OF f(x2, x1, x0) = one-set(1,2,4,6,7): a) 8-INPUT MULTIPLEXER; b) K-map; c) 4-INPUT MULTIPLEXER.

Introduction to Digital Systems 9 – Standard Combinational Modules 45 EXAMPLE 9.12: ONE-BIT

Inputs: a, b, cin ∈ {0, 1} Outputs: z, cout ∈ {0, 1}

a b cin z cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

0 0 0 0 0 0 z = (a b ) · cin (a b) · cin (ab ) · cin (ab) · cin 0 0 = cinm0(a, b) cinm1(a, b) cinm2(a, b) cinm3(a, b) cout = 0 · m0(a, b) cinm1(a, b) cinm2(a, b) 1 · m3(a, b)

Introduction to Digital Systems 9 – Standard Combinational Modules 46 E=1 E=1

En En cin 0 0 0 c'in 1 1 z cout 2 2

3 1 3 4-Input Multiplexer 4-Input Multiplexer 1 0 1 0

a

b

cin cin z: cout : 0 1 0 1 0 0 1 0

a 1 0 1 0 a 0 1 1 1

b b

c c' in in 0 cin

a c'in cin a cin 1

b b

Figure 9.23: IMPLEMENTATION OF ONE-BIT ADDER WITH 4-INPUT MULTIPLEXERS.

Introduction to Digital Systems 9 – Standard Combinational Modules 47 MULTIPLEXER TREES

sleft = (s3, s2)

sright = (s1, s0)

wj = x(4j+sright) , 0 ≤ j ≤ 3

z = wsleft

s = 4sleft + sright

z = x4sleft+sright = xs

Introduction to Digital Systems 9 – Standard Combinational Modules 48 16-INPUT TREE MULTIPLEXER

x x x x x3 x2 x1 x0 x15 x14 x13 x12 x11 x10 x9 x8 7 6 5 4

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1 En 1 En 1 En 1 En 1 MUX 1 MUX 1 MUX 1 MUX 0 0 0 0

s1 0 s0 1

x13 x9 x5 x1

3 2 1 0 s E En 3 1 MUX 1 s2 0 0

z = x9

Figure 9.24: TREE IMPLEMENTATION OF A 16-INPUT MULTIPLEXER.

Introduction to Digital Systems 9 – Standard Combinational Modules 49 DEMULTIPLEXERS (distributors)

• A HIGH-LEVEL DESCRIPTION: Inputs: x, E ∈ {0, 1} s = (sn−1, . . . , s0) , sj ∈ {0, 1} Outputs: y = (y2n−1, . . . , y0) , yi ∈ {0, 1}

 x if (i = s) and (E = 1)  Function: yi =  if or  0 (i 6= s) (E = 0) 

n−1 j n s = X sj2 , 0 ≤ i ≤ 2 − 1 j=0

Introduction to Digital Systems 9 – Standard Combinational Modules 50

E y 0 En 0 y 1 1 y 2 2 Data input Data outputs x (DMUX) Demultiplexer

y n n 2 -1 2 -1

n-1 0

s s n-1 0 Select inputs

Figure 9.25: 2n-OUTPUT DEMULTIPLEXER.

Introduction to Digital Systems 9 – Standard Combinational Modules 51 EXAMPLE 9.13: 4-OUTPUT DEMULTIPLEXER

E s1 s0 s y3 y2 y1 y0 1 0 0 0 0 0 0 x 1 0 1 1 0 0 x 0 1 1 0 2 0 x 0 0 1 1 1 3 x 0 0 0 0 - - - 0 0 0 0

n yi = E · x · mi(s), 0 ≤ i ≤ 2 − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 52 E

x y 0

y 1

y 2

y 3

s s 1 0

Figure 9.26: GATE NETWORK IMPLEMENTATION OF A 4-OUTPUT DEMULTIPLEXER.

Introduction to Digital Systems 9 – Standard Combinational Modules 53

Y

DMUX Sel 0 1 2 3

S0 S1 S2 S3

0 1 2 3 MUX

X For n-bit operands, Mux and Dmux replicated n times and connected to the corresponding FUNCTIONAL bit s of the input/output vectors. f UNIT

Z= f(X)

Figure 9.27: DEMULTIPLEXER: example of use.

Introduction to Digital Systems 9 – Standard Combinational Modules 54 SIMPLE SHIFTER E E=1 E=1 -1 -1 -1 -1 x x x 0 0 0 0 0 0 0 0 x x x y y y 1 x i-1 x i i i i i i y y x y (c) (b) (a) i+1 x n-2 x n-1 n-1 n-1 n-1 n-1 n-1 n-bit Simple Shifter n-bit Simple x x y y n-1 n-1 y x n n n n x x x left/ right shift/ no shift shift/ no shift shift/ no shift left/ right left/ right s d YES YES LEFT RIGHT s= s= d= d=

Figure 9.28: n-BIT SIMPLE SHIFTER: a) BLOCK DIAGRAM; b) RIGHT SHIFT; c) LEFT SHIFT.

Introduction to Digital Systems 9 – Standard Combinational Modules 55 SIMPLE SHIFTER: HIGH-LEVEL DESCRIPTION

Inputs: x = (xn, xn−1, . . . , x0, x−1) , xj ∈ {0, 1} d ∈ {RIGHT, LEF T } s ∈ {Y ES, NO} E ∈ {0, 1} Outputs: y = (yn−1, . . . , y0) , yj ∈ {0, 1}

Function:  x if (d = LEF T ) and (s = Y ES) and (E = 1)  i−1    x if (d = RIGHT ) and (s = Y ES) and (E = 1)  i+1 yi =  xi if (s = NO) and (E = 1)    if  0 (E = 0)   for 0 ≤ i ≤ n − 1.

 0 left shift with 0 insert    x−1 =  1 left shift with 1 insert    xn−1 left rotate   0 right shift with 0 insert    xn =  1 right shift with 1 insert    x0 right rotate 

Introduction to Digital Systems 9 – Standard Combinational Modules 56 EXAMPLE 9.14: 4-INPUT SHIFTER

Control Data s d x4 x3 x2 x1 x0 x−1 1 0 0 1 1 0 No shift no – 0 0 1 1 Right shift yes right 1 0 0 1 Left shift yes left 0 1 1 0 y3 y2 y1 y0

Coding: s d 0 no 0 right 1 yes 1 left

Introduction to Digital Systems 9 – Standard Combinational Modules 57 xn xn-1 xn-2 x1 x0 x-1 d LEFT RIGHT

E s NO SHIFT

yn-1 y0

(a)

xn xn-1 xn-2 x1 x0 x-1

E En 3 2 1 0 En 3 2 1 0

1 MUX 1 MUX 0 0 s d

yn-1 y0

(b)

Figure 9.29: IMPLEMENTATION OF A SIMPLE SHIFTER: a) WITH GATES; b) WITH MULTIPLEXERS.

Introduction to Digital Systems 9 – Standard Combinational Modules 58 p-SHIFTER: HIGH-LEVEL DESCRIPTION

Inputs: x = (xn+p−1, . . . , xn, xn−1, . . . , x0, x−1, . . . , x−p) , xj ∈ {0, 1} s ∈ {0, 1, ..., p} d ∈ {LEF T, RIGHT } E ∈ {0, 1} Outputs: y = (yn−1, . . . , y0) , yj ∈ {0, 1}

Function:  x if (d = LEF T ) and (E = 1)  i−s   if and yi =  xi+s (d = RIGHT ) (E = 1)  if  0 (E = 0)   0 ≤ i ≤ n − 1

Introduction to Digital Systems 9 – Standard Combinational Modules 59 p-SHIFTER

x n+p-1 x n x n-1 x 0 x -1 x -p

s distance log(p+1) n-bit p-Shifter En E d left/right

y n-1 y 0

Figure 9.30: n-BIT p-SHIFTER.

Introduction to Digital Systems 9 – Standard Combinational Modules 60 Stage 0 Stage 1 Stage 2 Stage 3 n+2p x y 0 or 2 SHIFT 0 or 1 SHIFT 0 or 4 SHIFT 0 or 8 SHIFT d 2 3 0 1 s s s s

Figure 9.31: BARREL SHIFTER FOR p = 15.

Introduction to Digital Systems 9 – Standard Combinational Modules 61 UNIDIRECTIONAL SHIFTERS

x6 x5 x4 x3 x2 x1 x0

E

En 3 2 1 0 En 3 2 1 0 En 3 2 1 0 En 3 2 1 0

1 MUX 1 MUX 1 MUX 1 MUX 0 0 0 0

s1

s0

y3 y2 y1 y0

Figure 9.32: MULTIPLEXER IMPLEMENTATION OF A 4-BIT RIGHT 3-SHIFTER.

Introduction to Digital Systems 9 – Standard Combinational Modules 62 TYPICAL USES OF SHIFTERS

• ALIGNMENT OF A BIT-VECTOR

• REMOVAL OF THE LEADING (or trailing) BITS OF A VECTOR

• PERFORMING MULTIPLICATION OR DIVISION BY A POWER OF TWO

• EXTRACTING A SUBVECTOR from a bit-vector, using a shifter instead of a selector

Introduction to Digital Systems 9 – Standard Combinational Modules