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(12) United States Patent (io) Patent No.: US 9,831,873 B2 Stoica et al. (45) Date of Patent: Nov. 28, 2017
(54) METHOD AND APPARATUS FOR (52) U.S. Cl. SIMULTANEOUS PROCESSING OF CPC ...... H03K 19/0002 (2013.01); G06F 7/00 MULTIPLE FUNCTIONS (2013.01); G06F 7/49 (2013.01); H03K 19/08 (2013.01) (71) Applicant: California Institute of Technology, (58) Field of Classification Search Pasadena, CA (US) CPC ...... H03K 19/0002; H03K 19/08; G06F 7/00; G06F 7/49 (72) Inventors: Adrian Stoica, Altadena, CA (US); USPC ...... 326/105, 59, 106 Radu Andrei, Shelby Township, MI See application file for complete search history. (US) (56) References Cited (73) Assignee: California Institute of Technology, Pasadena, CA (US) U.S. PATENT DOCUMENTS
(*) Notice: Subject to any disclaimer, the term of this 4,275,265 A * 6/1981 Davida ...... H04L 9/0618 380/29 patent is extended or adjusted under 35 4,463,344 A 7/1984 Adler et al. U.S.C. 154(b) by 0 days. 4,706,299 A * 11/1987 Jorgensen ...... G06E 1/04 326/60 (21) Appl. No.: 14/618,953 5,650,783 A 7/1997 Murashita et al. 6,133,754 A 10/2000 Olson (22) Filed: Feb. 10, 2015 7,088,141 132 8/2006 Deogun et al. 7,221,711 132 5/2007 Woodworth et al. (65) Prior Publication Data (Continued) US 2016/0233862 Al Aug. 11, 2016 Primary Examiner Daniel D Chang US 2017/0244410 A9 Aug. 24, 2017 (74) Attorney, Agent, or Firm KPPB LLP
Related U.S. Application Data (57) ABSTRACT (60) Division of application No. 13/235,188, filed on Sep. Electronic logic gates that operate using N logic state levels, 16, 2011, now Pat. No. 8,975,922, which is a where N is greater than 2, and methods of operating such continuation-in-part of application No. 12/393,562, gates. The electronic logic gates operate according to truth filed on Feb. 26, 2009, now abandoned. tables. At least two input signals each having a logic state that can range over more than two logic states are provided (60) Provisional application No. 61/383,488, filed on Sep. to the logic gates. The logic gates each provide an output 16, 2010, provisional application No. 61/067,666, signal that can have one of N logic states. Examples of gates filed on Feb. 29, 2008. described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, (51) Int. Cl. and C, where A, B and C can take any of four logic states. H03K 19/20 (2006.01) Systems using such gates are described, and their operation H03K 19/00 (2006.01) illustrated. Optical logic gates that operate using N logic G06F 7/00 (2006.01) state levels are also described. G06F 7/49 (2006.01) H03K 19/08 (2006.01) 13 Claims, 26 Drawing Sheets
11
X2 US 9,831,873 B2 Page 2
(56) References Cited U.S. PATENT DOCUMENTS
7,339,500 B2 3/2008 Noda et al. 7,502,464 B2 * 3/2009 Macchetti ...... H04L 9/0631 380/29 8,975,922 B2 3/2015 Stoica et al. 2005/0030207 Al 2/2005 Craven et al. 2005/0258863 Al 11/2005 Chang et al. 2007/0152710 Al 7/2007 Lablans 2007/0176800 Al 8/2007 Rijavec et al. 2008/0088345 Al 4/2008 Whetsel 2008/0094260 Al 4/2008 Motoyama et al. 2008/0212776 Al 9/2008 Motoyama et al. 2012/0236378 Al 9/2012 Stoica et al. * cited by examiner 0 VA
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IF= FIG. 19 M,U AJ_.T)8; -with drivers Y 4 lovel drivers VA 4-k 'x 8 bit Al,t s standardimplementerin c J(;~ "■ r}.... }3in17ti'tCo . .fit level to'. bina*! Conversion +s +s r. lu~~l~ U.S. Patent Nov. 28, 2017 Sheet 24 of 26 US 9,831,873 B2 EW I, U.S. Patent Nov. 28, 2017 Sheet 25 of 26 US 9,831,873 B2 N N C 21 LL s m U.S. Patent Nov. 28, 2017 Sheet 26 of 26 US 9,831,873 B2 0 cY) N Q LL v, E ~~ m US 9,831,873 B2 N METHOD AND APPARATUS FOR Also known in the prior art is Deogun et al., U.S. Pat. No. SIMULTANEOUS PROCESSING OF 7,088,141, issued Aug. 8, 2006, which is said to disclose a MULTIPLE FUNCTIONS multi-threshold complementary metal-oxide semiconductor (MTCMO)bus circuit reduces bus power consumption via CROSS-REFERENCE TO RELATED 5 a reduced circuit leakage standby and pulsed control of APPLICATIONS standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator This application is a Divisional application of co-pending pulses the high-threshold voltage power supply rail standby U.S. patent application Ser. No. 13/235,188 filed Sep. 16, switching devices in response to changes detected at the bus 2011, which application claimed priority to and the benefit io circuit inputs. The delay penalty associated with leaving the of then U.S. provisional patent application Ser. No. 61/383, standby mode is overcome by reducing cross-talk induced 488 filed Sep. 16, 2010, and was a continuation-in-part of delay via a cross-talk noise minimization encoding and co-pending U.S. patent application Ser. No. 12/393,562, decoding scheme. A subgroup of bus wires is encoded and filed Feb. 26, 2009, which application claimed the priority decoded, simplifying the encoding, decoding and change and benefit of U.S. provisional patent application Ser. No. 15 detection logic and results in the bus subgroup being taken 61/067,666 filed Feb. 29, 2008, each of which applications out of standby mode only when changes occur in one or is incorporated herein by reference in its entirety. more of the subgroup inputs, further reducing the power consumption of the overall bus circuit. STATEMENT REGARDING FEDERALLY Also known in the prior art is Rijavec, U.S. Patent FUNDED RESEARCH OR DEVELOPMENT 20 Application Publication No. 2007/0176800 Al, published Aug. 2, 2007, which is said to disclose methods and systems The invention claimed herein was made in the perfor- for improving performance of data decoding using a priori mance of work under a NASA contract, and is subject to the information about the data steam. In one aspect a decoder provisions of Public Law 96-517(35 USC 202)in which the may determine the degree oflossiness inherent in the data or Contractor has elected to retain title. 25 in the application of the data as a maximum resolution of data to be decoded and may thereby streamline entropy FIELD OF THE INVENTION decoding ofthe data. For example,in DCT-based image data compression coupled with Huffman or other entropy encod- The invention relates to electronic logic gates. ing, a priori data may be analyzed to determine the maxi- 30 mum required resolution in bits of the DCT encoded data so BACKGROUND OF THE INVENTION as to simplify the entropy decoding. Other aspects optimize DCT decoding computation with faster approximations A substantial amount of research in electronic microsys- where the quantization values indicate a higher degree of tems has focused on bringing more computing power to lossiness or noise in the DCT encoded data. A priori infor- smaller devices. Traditional approaches to increase comput- 35 mation may generally comprise values in the quantization ing bandwidth has often focused on exploiting concurrency, table of a DCT encoded image and may be analyzed to such as by allocating increasingly more gates to specific determine the maximum symbol size and/or degree of tasks, or by performing instructions faster, such as operating lossiness. gates at higher speeds. These traditional approaches are Also known in the prior art is Noda, U.S. Pat. No. expected to have diminishing returns, and may bump up 4o 7,339,500, issued Mar. 4, 2008, which is said to disclose two against technological barriers, such as for example limita- different block codes that can be encoded by one-type of tions on power dissipation. encoding section. A first-point-fixed encoding section Another technological barrier has to do with the substan- divides m-bit data into a first-half code and a second-half tial increase in the number of transistors built in modern code, and encodes them into an n-bit provisional code with devices, which increases by approximately a factor of two 45 fixed start-point state. A code A/B counter receives a reset- every 18 to 24 months, and which is predicted by Moore's signal and outputs a code selection signal to a code-order Law. As the number of devices increases, more and more reversing section and a top-code correction section. The area on a chip needs to be devoted to interconnects. At some code-order reversing section receives a codeword excluding point, the portion of the chip devoted to interconnects the top code from the start-point-fixed encoding section; and becomes excessive, possibly exceeding the area of the chip 50 outputs the codeword as is, when the code selection signal devoted to transistors or active devices. indicates a code B, and reverses the order of the codeword Also known in the prior art is Adler et al., U.S. Pat. No. to generate a new codeword, and outputs the new codeword 4,463,344, issued Jul. 31, 1984, which is said to disclose an to a latch, when the code selection signal indicates a code A. algorithm and the hardware embodiment for producing a run The top-code correction section determines whether the top length limited code useful in magnetic recording channels. 55 code needs to be modified, and modifies the top code, if The system described produces sequences which have a necessary. minimum of 2 zeros and a maximum of 7 zeros between Also known in the prior art is Motoyama, U.S. Patent adjacent 1's. The code is generated by a sequential scheme Application Publication No. 2008/0094260 Al, published that maps 1 bit of unconstrained into 2 bits of constrained Apr. 24, 2008, which is said to disclose a logic circuit that data. The encoder is a finite state machine whose internal 60 executes a prescribed arithmetic processing that includes a state description requires 3 bits. It possesses the attractive decoder that converts one or more binary input data into a feature ofreset data blocks which reset it to a fixed state. The first plurality of bit data of a constant hamming weight decoder requires a lookahead of three future channel sym- regardless of a hamming weight of the input data, an bols (6 bits) and its operation is channel state independent. interconnect network that is connected to the decoder, The error propagation due to a random error is 3 bits. The 65 changes a bit pattern of the first plurality of bit data and hardware implementation is extremely simple and can oper- generates a second plurality of bit data, according to receiv- ate at very high data speeds. ing the first plurality of bit data converted according to the US 9,831,873 B2 3 4 decoder, and substituting a bit position of the received first In one embodiment, the electronic logic gate further plurality of bit data for the purpose of the prescribed comprises a binary to N logic level encoder. arithmetic operation, and an encoder connected to the inter- In another embodiment, the electronic logic gate further connect network and converts the second plurality of bit data comprises an N logic level driver. generated in the interconnect network into one or more 5 In yet another embodiment, the electronic logic gate binary output data. further comprises an N logic level to binary decoder. Also known in the prior art is Motoyama, U.S. Patent In still a further embodiment, the N monotonic logic Application Publication No. 2008/0212776 Al, published signal levels are equally spaced signal levels. Sep. 4, 2008, which is said to disclose an encryption According to another aspect, the invention relates to a processing circuit that includes a decoder configured to io method of processing electronic signals. convert a binary input data used for predetermined encryp- The method comprises the steps of. providing an elec- tion computing into a first plurality of bit data of a constant tronic logic gate; providing a truth table; applying at least hamming weight independently of a hamming weight of the first and second electrical input logic signals each having input data; a wiring network configured to receive the first one logic state selected from a number N of logic states to plurality of bit data converted by the decoder, the wiring 15 the at least the first input terminal and the second input network further configured, for the purpose of the predeter- terminal; sensing the electrical output signal; and perform- mined encryption computing, to change a bit pattern of the ing at least one ofrecording the result, transmitting the result received first plurality of bit data by replacing bit positions to a data handling system, or to displaying the result to a of the first plurality of bit data, and to generate a second user. The electronic logic gate, comprises at least a first input plurality of bit data; and an encoder configured to convert 20 terminal and a second input terminal, each input terminal the second plurality of bit data generated in the wiring configured to receive a respective electrical input logic network into a binary output data. signal having one logic state selected from a number N of Mechanical computation systems that rely on a plurality logic states, and an output terminal configured to provide an of states, including machines that operate using N=10 states, electrical output logic signal having one logic state selected such as Babbage's Difference Engine, have been known for 25 from a number N of logic states, where N is an integer many years. However, electronic computation systems use greater than two; the electronic logic gate configured to two states (e.g., binary logic). perform a logic operation using the electrical input logic There is a need for electronic logic gates and electronic signals received at the at least the first input terminal and the computational systems that use more logic states than two second input terminal, the logic operation is defined by a binary logic states. 30 truth table. In one embodiment, the truth table is selected from the SUMMARY OF THE INVENTION group of truth tables consisting of a NAND/NAND truth table, a NOR/NOR truth table, an OR/OR truth table, an According to one aspect, the invention features an elec- XOR/XOR truth table, a NOT/NOT truth table, and an tronic logic gate. The electronic logic gate comprises at least 35 AND/AND truth table. a first input terminal and a second input terminal, each input In another embodiment, the number N of logic states terminal configured to receive a respective electrical input correspond to N monotonic logic signal levels. logic signal having one logic state selected from a number In yet another embodiment, the N monotonic logic signal N of logic states, and an output terminal configured to levels are equally spaced signal levels. provide an electrical output logic signal having one logic 40 In a further aspect, the invention provides an optical logic state selected from a number N of logic states, where N is gate. The optical logic gate comprises at least a first input an integer greater than two; the electronic logic gate con- terminal and a second input terminal, each input terminal figured to perform a logic operation using the electrical input configured to receive a respective optical input logic signal logic signals received at the at least the first input terminal having one logic state selected from a number N of logic and the second input terminal, the logic operation defined by 45 states, and an output terminal configured to provide an a truth table. optical output logic signal having one logic state selected In one embodiment, the electronic logic gate further from a number N of logic states, where N is an integer comprises a selector input configured to receive a selector greater than two; said optical logic gate configured to signal having a plurality of logic states, the logic gate perform a logic operation using said optical input logic configured to perform a plurality of different logic functions 50 signals received at said at least said first input terminal and using the electrical input logic signals received at the at least said second input terminal, said logic operation defined by the first input terminal and the second input terminal in a truth table. response to the selector signal. In one embodiment, the optical logic gate further com- In another embodiment, the truth table is a NAND/NAND prises a selector input configured to receive a selector signal truth table. 55 having a plurality of logic states, said logic gate configured In yet another embodiment, the truth table is a NOR/NOR to perform a plurality of different logic functions using said truth table. optical input logic signals received at said at least said first In still another embodiment, the truth table is an OR/OR input terminal and said second input terminal in response to truth table. said selector signal. In a further embodiment, the truth table is an XOR/XOR 60 In another embodiment, said N logic states correspond to truth table. N monotonic logic signal levels. In yet a further embodiment, the truth table is a NOT/ The disclosed subject matter describes a method to pro- NOT truth table. vide an input-output relationship to process K input multi- In an additional embodiment, the truth table is an AND/ level logic signals into an output signal. The method com- AND truth table. 65 prises the steps of choosing a decoding scheme to decode the In one more embodiment, the N logic states correspond to K input multi-level logic signals into a set of M'bits on each N monotonic logic signal levels. channel of M channels; choosing Boolean functions for each US 9,831,873 B2 5 6 channel; and choosing an encoding scheme to encode the FIG. 2 illustrates the input-output relationship of an output of the Boolean functions into the output signal. (AND, OR)logic gate according to an embodiment. In one embodiment, M-M. FIG. 3 illustrates a methodology for constructing the In another embodiment, the decoding scheme applies the input-output relationship of a logic gate according to an same decoding function to each of the K input multi-level 5 embodiment. logic signals. FIG. 4 illustrates the input-output relationship of an adder The disclosed subject matter describes a logic gate to logic unit according to an embodiment. provide an output signal y in response to K input signals xk, FIG. 5 is a circuit diagram of a NAND-NAND logic gate k=1, 2, ... , K. The logic gate comprises M channels Cm, operating on signals having N=4 logic states. m=1, 2, .. , M to propagate data signals to perform M 10 FIG. 6 is the truth table that corresponds to the logic gate Boolean functions fm, m=1, 2...., M, where for each k=1, of FIG. 5. 2, .. , K, input signal xk maps into an M'-tuple of bits FIGS. 7A through 7C are diagrams illustrating the behav- (xk(M'), xk(M'-1), ..., xk(2), Xk(l)), where each x,(m) is a ior of a NAND-NAND logic gate such as shown in FIG. 5 binary logic signal, where a subset of the set of K M'-tuples in which the logic levels are spaced equidistantly in voltage. I(xk(M'), xk(M'-I), ... , xk(2), xk(l)), k=1, 2, ... , K} is 15 FIG. 8A is a diagram of a decoder for logic level A-0. transmitted over the M channels, and where the output signal FIG. 8B is a diagram of a decoder for logic level A<3. y is a function of the M-tuple of binary signals (fmJCM}, FIG. 8C is a diagram of a decoder for logic level A=1. f.,lcm i}, fz{Cz}, fi{CJ), where for each m=1, 2, ... , FIG. 8D is a diagram of a decoder for logic level A=2. M, {Cm} is the subset of the set of K M'-tuples {(xk (M'), FIG. 8E is a schematic diagram of a circuit element that xk(M'-I), . . . , xk(2), xk(1)), k=1, 2, . . . , K} that is 20 behaves as a wired minimum. transmitted over the channel Cm, and fm{m}is an output of FIG. 9 is a circuit diagram of an alternative embodiment Boolean function f_ for the set ofbinary logic signals {Cm}. of a NAND/NAND gate. The input signals can be multi-level logic signals. FIG. 10 is a graph that illustrates the voltage transfer In one embodiment, M-M, where for each k=1, 2, ... , characteristics for a NAND/NAND gate. K, xk(m)is sent over channel Cm for each m=1, 2, ..., M, 25 FIG. 11 is a circuit diagram of an embodiment of a where for each m=1, 2, ... , M,{C m} is the set of binary NOT/NOT gate. logic signals {xi(m), xz(m), ... , xK(m)}. FIGS. 12A and 12B are a circuit diagram of an embodi- In yet another embodiment, a same mapping is applied to ment of a OR/OR gate. each signal xk. FIGS. 13A and 13B are a circuit diagram of an embodi- The disclosed subject matter describes a method to syn- 30 ment of a XOR/XOR gate. thesize a simul-gate logic circuit given a logic circuit FIGS. 14A and B are a circuit diagram of an embodiment comprising a set of Boolean logic gates {B,, i=1, 2,... , N1. of a NAND3/NAND3 gate. The method comprises the steps of replacing, for each i=1, FIG. 15 is a schematic diagram of an embodiment of a 2, ..., N,the Boolean logic gate B,in the logic circuit with simultaneous arithmetic logic unit ("SIMU-ALU") that the simul-gate (B,, Bi,... , BJ, where B,is repeated M times. 35 operates using four logic levels. In one embodiment,for each i=1, 2,... , N,the simul-gate FIG. 16 is a circuit diagram of a 4-level to binary decoder. (Bi, Bi,... , BJ is such that in response to K(i)input signals FIG.17 is a circuit diagram of a binary to 4-level encoder. xk(i), k-L 2, ..., K(i), the simul-gate (B,t B,t ... , BJ FIG. 18 is a circuit diagram that illustrates 4-level output comprises M channels C_(i), m=1, 2, ..., M to propagate driver circuits. data signals to perform the Boolean function B, M times, 40 FIG. 19 is a table that illustrates the values of the selector where for each k1,2, ... , K(i), input signal xk (i) maps into S and the corresponding logical operations that will be an M-tuple of bits (xk(i, M), xk(i,M-1),... , x k(i,2), xk(ij )), performed by each of a SIMU-ALU and a parallel arithmetic where each xk(i, m)is a binary logic signal, where xk (i,m) logic unit. is sent over channel C_(i) for each m=1, 2, ... , M, and FIG. 20 is a diagram that illustrates a circuit layout for a where an output signal y(i) is a function of the M-tuple of 45 device that operates according to principles of the invention binary signals(BJC M(i)}, BJCM ,(i)}, BJCz (i)1, BJC,(i) that is illustrated by the schematic in FIG. 15. 1), where for each k=1, 2, ... , K(i), xk(i,m) is sent over FIG. 21 is an image of the SIMU-ALU device being channel C_(i)for each m=1, 2,... , M, where for each m=1, tested. 2,... , M,{C_(i)} is the set of binary logic signals {x,(i,m), FIG. 22 is a graph showing A and B inputs for a logic xz(i,m), . . . , xk(i,m)}, and B,{C_(i)} is the output of 50 function A (e.g., output=A input) that demonstrates the Boolean function B, for the set of binary logic signals identity of output for the SIMU-ALU and the parallel {Cm(i)}. arithmetic logic unit using conventional binary logic. The foregoing and other objects, aspects, features, and FIG. 23 is a graph showing A and B inputs for a logic advantages ofthe invention will become more apparent from function (A+B)-1 (e.g., output NAND (A and B) that the following description and from the claims. 55 demonstrates the identity of output for the SIMU-ALU and the parallel arithmetic logic unit using conventional binary BRIEF DESCRIPTION OF THE DRAWINGS logic. The objects and features of the invention can be better DETAILED DESCRIPTION understood with reference to the drawings described below, 60 and the claims. The drawings are not necessarily to scale, In the description that follows, the scope of the term emphasis instead generally being placed upon illustrating "some embodiments" is not to be so limited as to mean more the principles of the invention. In the drawings, like numer- than one embodiment, but rather, the scope may include one als are used to indicate like parts throughout the various embodiment, more than one embodiment, or perhaps all views. 65 embodiments. FIG. 1 illustrates the input-output relationship of a logic A methodology is presented for describing an input- gate according to an embodiment. output behavior of a multi-level logic gate to process simul- US 9,831,873 B2 7 8 taneously a multiplicity of independent Boolean logic func- provided to the last channel. For the particular embodiment tions, with each Boolean function processing signals carried illustrated in FIG. 1, each channel carries binary signals on an individual, separate channel. An embodiment may obtained from all the multi-level logic signals provided as simultaneously process the same data with the same function input to decoder 104. However, other embodiments may or with different functions, multiple data with the same 5 have one or more channels that do not carry any binary function, or multiple data with different functions. In addi- signals associated with one or more input multi-level logic tion, multi-level logic signals (having more than two levels) signals. Each channel may be viewed as carrying binary may be processed, so that a higher communication band- signals to its corresponding Boolean gate, where each Bool- width may be obtained without necessarily increasing the ean gate then processes its binary signals to provide a binary number of traces (wires). 10 output to encoder 110. Encoder 110 then encodes these Embodiments increase functional density at the logic gate binary signals to provide a multi-level logic signal at output level by combining multiple functions within a single gate. port 112. Embodiments may process simultaneously a multiplicity of Embodiments may be described in more detail by intro- independent Boolean logic functions, with each Boolean 15 ducing additional notation. Decoder 104 maps input signal function processing signals carried on an individual, sepa- xkinto the M-tuple of bits(x k(M), xk(M-1),... , x k(2), xk(1)) rate channel. An embodiment may simultaneously process the same data with the same function or with different for each k=1, 2, ..., K, where each xk(m)is a binary logic functions, multiple data with the same function, or multiple signal, and where xk(m) is sent over channel Cm for each m=1, 2, ... , M and for each k. In this way, for each m=1, data with different functions. In addition, multi-level logic signals (having more than two levels) may be processed, so 20 2, ... , M, channel Cm carries the set of binary signals that a higher communication bandwidth may be obtained {xi(m), xz(m), , xK(m)}. For each m=1, 2, .. , M, without necessarily increasing the number of traces (wires). Boolean gate fm operates on the set ofbinary signals {xi(m), Such an embodiment may be referred to as a simul-gate. xz(m), .... xK(m)} to provide an output binary signal that Embodiments may be described by their input-output may be expressed as f XAM), xz(m), .... xK(m)}. This behavior. The input signals, and the output signal, may each 25 output binary signal may be written more compactly as in general have more than two logic levels, or values. For fm{Cm}, where when Cm is the argument off m, it stands for example, an input or output signal may have logic levels in the set of binary signals carried on channel Cm. Encoder 112 the set has as its input the M-tuple of binary signals (fM{Cm}, fM_i WM-i!, ... , fz{Cz}, fjCj), and maps this into a 30 multi-level logic output signal y. For some embodiments, the output of each Boolean gate l0'(3) °'GY °)' does not depend upon the ordering of its input signals. This was the motivation for using set notation in describing the input and output relationship of a Boolean gate. For where v is some voltage scale. A correspondence between 35 example, the output binary signal of Boolean gate fm was the binary symbols 0 and 1 and these logic voltage levels written as fm{Cm}. For some embodiments, the decoding may be taken as: 00"0; scheme is separable in the sense that the same decoding scheme is applied separately to each xk. If each Boolean gate does not depend upon the ordering of its input signals, and 01H(3)';10-GY 40 if the decoding scheme is separable so that the same decod- ing scheme is applied to each xk, then because each channel Cm carries the set of binary signals {xi(m), xz(m), ... and 11 v. Other embodiments may have more than four xK(m)} for each m=1, 2,... , M,the output ofthe simul-gate logic levels. It is not necessary that the number of logic is independent of the ordering of the input signals xk. levels in a set of logic levels be a power of two. 45 For some embodiments the output of encoder 110 depends Referring to FIG. 1, the input-output behavior of an upon the ordering of its input signals. This was the motiva- embodiment may be represented by K input ports 102, tion for using M-tuple notation for the encoder. As a result, decoder 104, M channels 106, M Boolean gates 108, for some embodiments the output signal y may depend upon encoder 110, and output port 112. There are K input signals, the ordering of the correspondence between the Boolean one for each input port, denoted by xk, k=1, 2, ..., K. The 50 gates and the channels. With this in mind, the input-output output signal at output port 112 is represented by y. The M behavior for the embodiment of FIG. 1 may be referred to Boolean functions fm, m=1, 2, ..., M denote the functional as an (fm, fM ,, ... ,f 2,f l)simul-gate, where the use of an behavior of the Boolean gates, where each fm denotes the M-tuple reminds one that the input-output behavior may functional input-output behavior of its corresponding Bool- depend upon the ordering ofthe correspondence between the ean gate. The M channels may be represented by the 55 Boolean gates and the channels. symbols Cm, m=1, 2, . . . , M. A channel Cm may be For some embodiments, the signals xk for k=1, 2, ..., K considered a set of input ports for the Boolean gate corre- may be such that a decoder maps input signal xk into the sponding to the Boolean function fm . M'-tuple of bits (xk(M'), xk(M'-1),... , xk(2), x,(1))for each In describing the input-output behavior of the embodi- k=1, 2, ... , K, where each xk(m) is a binary logic signal, ment in FIG. 1, each input signal xk is considered a multi- 6o but where M';-M. For example, if M'>M, then not all of the level logic signal, where decoder 104 decodes each multi- binary signals may be carried by the channels. As another level logic signal into a set of binary signals. Each set of example, if M'