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(12) United States Patent (Io) Patent No.: US 9,831,873 B2 Stoica Et Al

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(12) United States Patent (Io) Patent No.: US 9,831,873 B2 Stoica Et Al 11111111111111111111111111111111111111111111111111111111111111111111111111 (12) United States Patent (io) Patent No.: US 9,831,873 B2 Stoica et al. (45) Date of Patent: Nov. 28, 2017 (54) METHOD AND APPARATUS FOR (52) U.S. Cl. SIMULTANEOUS PROCESSING OF CPC ........... H03K 19/0002 (2013.01); G06F 7/00 MULTIPLE FUNCTIONS (2013.01); G06F 7/49 (2013.01); H03K 19/08 (2013.01) (71) Applicant: California Institute of Technology, (58) Field of Classification Search Pasadena, CA (US) CPC ...... H03K 19/0002; H03K 19/08; G06F 7/00; G06F 7/49 (72) Inventors: Adrian Stoica, Altadena, CA (US); USPC ........................................... 326/105, 59, 106 Radu Andrei, Shelby Township, MI See application file for complete search history. (US) (56) References Cited (73) Assignee: California Institute of Technology, Pasadena, CA (US) U.S. PATENT DOCUMENTS (*) Notice: Subject to any disclaimer, the term of this 4,275,265 A * 6/1981 Davida ................. H04L 9/0618 380/29 patent is extended or adjusted under 35 4,463,344 A 7/1984 Adler et al. U.S.C. 154(b) by 0 days. 4,706,299 A * 11/1987 Jorgensen ................. G06E 1/04 326/60 (21) Appl. No.: 14/618,953 5,650,783 A 7/1997 Murashita et al. 6,133,754 A 10/2000 Olson (22) Filed: Feb. 10, 2015 7,088,141 132 8/2006 Deogun et al. 7,221,711 132 5/2007 Woodworth et al. (65) Prior Publication Data (Continued) US 2016/0233862 Al Aug. 11, 2016 Primary Examiner Daniel D Chang US 2017/0244410 A9 Aug. 24, 2017 (74) Attorney, Agent, or Firm KPPB LLP Related U.S. Application Data (57) ABSTRACT (60) Division of application No. 13/235,188, filed on Sep. Electronic logic gates that operate using N logic state levels, 16, 2011, now Pat. No. 8,975,922, which is a where N is greater than 2, and methods of operating such continuation-in-part of application No. 12/393,562, gates. The electronic logic gates operate according to truth filed on Feb. 26, 2009, now abandoned. tables. At least two input signals each having a logic state that can range over more than two logic states are provided (60) Provisional application No. 61/383,488, filed on Sep. to the logic gates. The logic gates each provide an output 16, 2010, provisional application No. 61/067,666, signal that can have one of N logic states. Examples of gates filed on Feb. 29, 2008. described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, (51) Int. Cl. and C, where A, B and C can take any of four logic states. H03K 19/20 (2006.01) Systems using such gates are described, and their operation H03K 19/00 (2006.01) illustrated. Optical logic gates that operate using N logic G06F 7/00 (2006.01) state levels are also described. G06F 7/49 (2006.01) H03K 19/08 (2006.01) 13 Claims, 26 Drawing Sheets 11 X2 US 9,831,873 B2 Page 2 (56) References Cited U.S. PATENT DOCUMENTS 7,339,500 B2 3/2008 Noda et al. 7,502,464 B2 * 3/2009 Macchetti ............. H04L 9/0631 380/29 8,975,922 B2 3/2015 Stoica et al. 2005/0030207 Al 2/2005 Craven et al. 2005/0258863 Al 11/2005 Chang et al. 2007/0152710 Al 7/2007 Lablans 2007/0176800 Al 8/2007 Rijavec et al. 2008/0088345 Al 4/2008 Whetsel 2008/0094260 Al 4/2008 Motoyama et al. 2008/0212776 Al 9/2008 Motoyama et al. 2012/0236378 Al 9/2012 Stoica et al. * cited by examiner 0 VA 0 FIG. VA F'ICr..2 U.S. Patent Nov. 28, 2017 Sheet 3 of 26 US 9,831,873 B2 CHOOSE DECODING SCHEME X,""XK Cl ,(C2 V0, ),-(CM 1-304 CHOOSE BOOLEAN FUNCTIONS m CHOOSE ENCODING SCHEME (fm(cm),,Jl(C. ) FIG. 3 VA FIG, U.S. Patent Nov. 28, 2017 Sheet 5 of 26 US 9,831,873 B2 FIG. 5 B tJ 1 2 3 D 3 3 3 3 1 3Z 32 2 3 3 1 2 3 3 2 3 (? FIG. 6 U.S. Patent Nov. 28, 2017 Sheet 6 of 26 US 9,831,873 B2 Q m Ut d d Ca L- LL H 0 or: IN ry ci (JS) I'i U.S. Patent Nov. 28, 2017 Sheet 7 of 26 US 9,831,873 B2 FIG. 8A FIG. 8C =O >1 i W 9 7 (pall doNv i to 2) bia s FIG. 8D U.S. Patent Nov. 28, 2017 Sheet 8 of 26 US 9,831,873 B2 B=O & A<2 FIG. 8E ----------------- VA ,,,dd • A t~ M u -- wired mire mode .. .f)Y S: .......... ...... _... .._....... d14~.. el ss dvs>s ilvsa - d~as~~' plus pl7jas 3 lwys~. nbias FIG. 9 OVA Level 0 ------------------------- -------- - ------------- vin ` FIG. 10 not / n t FA w dvd~ . dvdd i q,< dvdd. ir•7 r n d35.4 FIG. 11 U.R. Patent &nv 28 2017 Sheet 12 026 US 9,831,873 G2 Awl2A I FIG. iZB !2-I d? 1 a : ±; add !22 ISa > & dvdd ~ \ !23 dAd;dvdd§ .< . ~\ ` 12 5 ~ ( ` ss . l. \y ^ ddb s.ƒ ss S: 3v 9fi~ gs=.,:rbias : [c U.S. Patent Nov. 28, 2017 Sheet 13 of 26 US 9,831,873 B2 y or/or b 0 is f - l:. r, 12-1 ------------- 12-2 12 Y,S s 12- FIG.12B U.S. Patent Nov. 28, 2017 Sheet 14 of 26 US 9,831,873 B2 I G. 13.3 I 171G. 138 pk dvdd r-i-. dvdd dYs L -3 ~y'ss rrbi as- E -ribs as pb as tr.-- ; ;~pbi s 19 U.S. Patent Nov. 28, 2017 Sheet 15 of 26 US 9,831,873 B2 W 13-1 OCIEW-1-1 U.S. Patent Nov. 28, 2017 Sheet 16 of 26 US 9,831,873 B2 dvdd FIG. 14A FIG.14BB t----:dv ss vs dvdd phial-tj', Cl cegl or ceg3; 4 14-3 , cgtl---- ------------ No. alt2- a12; doss doss FIG. 14A dvss dvss Ms dvdd dvdd dvdd dvdd dv dvdd _j pbias phias-- `i hlt2~ hgtl clt2 cgtI ~L c doss d,;s5 U.S. Patent Nov. 28, 2017 Sheet 17 of 26 US 9,831,873 B2 ISMINUM-9 14-1 14-2 14-3 ------------------ 6 dvdd --dvdd j dvss ~- dvss t buq 3- j ~l beg3 Pb as - pbias nbia nbias aegl 1 cgtl dvss UPS 'dV 55 dvdd dvdd dvdd_1 dvdd dvdd dvdd 4 pbias t .r pbias r~'' aeg0 —. agi:0 begl7 '1 bpto c eqO 1 c9t0 b e 6L doss dvss dVSS55 dvss doss dvdd dvdd dvdd dvdd dvdd d,'dd --r —r a b c fi dlt3 aeg3 blt3 + - r beg3 °ced3 r clt3 + ribias jI ---- n blas nblas dWSs dvss.. dvss dvss dWss doss VA 4ltlllll D Q01Yk~S/ Si): 23 `{ 4 qtfiftw SI1p11T, 16\ 4 stage output pb a5 I ,bias pull up pin nbias extl~<ti4 nb:ls FIG. 15 dvdd d dvdd'' s> pbias II bias doss doss • • ' doss doss id dvdd j ...., dvdd doss ( doss pbias( pbias <. y nbias ..... nbias ss FIG. 16 dvdd --- dvdd dvss doss pbsas > ;.. pbias VA dvdd FIG. 17 U.S. Patent Nov. 28, 2017 Sheet 21 of 26 US 9,831,873 B2 00 r-- (D LL * v U.S. Patent Nov. 28, 2017 Sheet 22 of 26 US 9,831,873 B2 fictive High Data Selection M=H M=L- Logic $2 S1 Function Cn H' carry)' L L F= F= L L H L F = AB F= + L L H H F=O IF .. Minu l x p!) L H L L F ::,, F ...:A Flu A L H L H F=.. F (A ..;.. ',) Fps ALA' L H H L F ,,-.A 9 B F A Minus B Minus 1 L H H H F Ab F .... is -' H L L L. F'=;, 4.. BF=APiusAB H L L H F'. A 0 B F =A Plus H L H L F=B F )Plus AB H L H H F=AB F =AS Minus H H L L F=1 F= FIu * ...' H H L. H F=A a. F..:::( ) I A H H L F=A + F .., ~ ''~ l H H H F'=... IF= FIG. 19 M,U AJ_.T)8; -with drivers Y 4 lovel drivers VA 4-k 'x 8 bit Al,t s standardimplementerin c J(;~ "■ r}.... }3in17ti'tCo<t$3... t R~Vct Conversion 'fis . .fit level to'. bina*! Conversion +s +s r. lu~~l~ U.S. Patent Nov. 28, 2017 Sheet 24 of 26 US 9,831,873 B2 EW I, U.S. Patent Nov. 28, 2017 Sheet 25 of 26 US 9,831,873 B2 N N C 21 LL s m U.S. Patent Nov. 28, 2017 Sheet 26 of 26 US 9,831,873 B2 0 cY) N Q LL v, E ~~ m US 9,831,873 B2 N METHOD AND APPARATUS FOR Also known in the prior art is Deogun et al., U.S. Pat. No. SIMULTANEOUS PROCESSING OF 7,088,141, issued Aug. 8, 2006, which is said to disclose a MULTIPLE FUNCTIONS multi-threshold complementary metal-oxide semiconductor (MTCMO)bus circuit reduces bus power consumption via CROSS-REFERENCE TO RELATED 5 a reduced circuit leakage standby and pulsed control of APPLICATIONS standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator This application is a Divisional application of co-pending pulses the high-threshold voltage power supply rail standby U.S.
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