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Low-Complexity Decoding Algorithms and Architectures for Non-Binary Ldpc Codes

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Low-Complexity Decoding Algorithms and Architectures for Non-Binary Ldpc Codes LOW-COMPLEXITY DECODING ALGORITHMS AND ARCHITECTURES FOR NON-BINARY LDPC CODES by FANG CAI Submitted in partial fulfillment of the requirements For the degree of Doctor of Philosophy Thesis Adviser: Dr. Xinmiao Zhang Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY August, 2013 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the thesis/dissertation of Fang Cai ______________________________________________________ Doctor of Philosophy candidate for the ________________________________degree *. Xinmiao Zhang (signed)_______________________________________________ (chair of the committee) Christos Papachristou ________________________________________________ Daniel Saab ________________________________________________ Francis Merat ________________________________________________ ________________________________________________ ________________________________________________ 06/13/2013 (date) _______________________ *We also certify that written approval has been obtained for any proprietary material contained therein. Table of Contents List of Tables v List of Figures vi Acknowledgments viii Abstract x Chapter 1. Introduction 1 1.1 Summary of Contributions .................... 5 1.1.1 Relaxed Min-max Decoding Algorithm and Architecture 5 1.1.2 Enhanced Iterative Hard Reliability-based Majority-logic Decoding Algorithm and Architectures .......... 5 1.1.3 Power Representation Based Decoding Algorithm and Ar- chitecture .......................... 7 1.2 Outline of the Thesis ....................... 8 Chapter 2. NB-LDPC Decoding Algorithms 10 2.1 Existing Works for Belief Propagation Algorithm ........ 10 2.1.1 Belief-propagation Algorithm ............... 10 2.1.2 FFT-based Decoder .................... 10 2.1.3 Mixed Domain Decoder .................. 11 2.2 Extended Min-sum (EMS) Algorithm .............. 11 2.2.1 Existing works based on EMS algorithm ......... 11 2.2.2 Dataflow of EMS algorithm ................ 12 2.2.3 Simplified Min-sum algorithm ............... 14 2.3 Min-max Algorithm ........................ 15 2.3.1 Existing works based on Min-max algorithm ....... 15 2.3.2 Dataflow of Min-max algorithm .............. 16 ii 2.3.3 Boundary tracking based check node processing for Min- max algorithm ....................... 17 2.3.4 Path construction based check node processing for Min- max algorithm ....................... 18 2.4 Error Correcting Performance of Extended Min-sum and Min- max algorithm ........................... 24 2.5 The IHRB-MLGD and ISRB-MLGD Algorithm ........ 28 2.6 Error Correcting Performance of IHRB-MLGD and ISRB-MLGD Algorithm ............................. 31 2.7 Layered Decoding ......................... 34 Chapter 3. Relaxed Min-max Decoding Algorithm and Archi- tecture 35 3.1 Introduction ............................ 35 3.2 Relaxed Min-max Check Node Processing ............ 36 3.2.1 Relaxed Min-max Check Node Processing ........ 38 3.2.2 Simplified Relaxed Min-max Check Node Processing . 45 3.3 Relaxed Min-max CNU Architecture .............. 53 3.3.1 Reordering Network and Min1 Selector .......... 54 3.3.2 Trellis Basis Constructor ................. 54 3.3.3 Minimum Basis Constructor ............... 58 3.3.4 Basis Recovery Module .................. 61 3.4 Simplified Min-max NB-LDPC Decoder Architecture ..... 65 3.4.1 Top Level Decoder Architecture ............. 66 3.4.2 Computation Scheduling .................. 70 3.5 Complexity Analyses and Comparisons ............. 71 3.6 Summary .............................. 74 Chapter 4. Enhanced Iterative Hard Reliability-based Majority- logic Decoding Algorithm and Architecure 78 4.1 Introduction ............................ 78 4.2 Enhanced IHRB-MLGD Algorithm ............... 79 4.3 Partial-parallel Architectures for IHRB-MLGD ......... 87 4.3.1 IHRB-MLGD Architecture for QCNB-LDPC Codes . 87 iii 4.3.2 IHRB-MLGD Architecture for Cyclic NB-LDPC Codes 90 4.4 Partial-parallel Architectures for E-IHRB-MLGD ........ 97 4.4.1 Extra storage ........................ 99 4.4.2 Selector ........................... 100 4.4.3 VNU modification ..................... 101 4.5 Complexity Analyses and Comparisons ............. 102 4.6 Summary .............................. 110 Chapter 5. Power Representation Based Decoding Algorithm and Architecture 114 5.1 Introduction ............................ 114 5.2 Check Node Processing for the Min-max Algorithm ...... 115 5.2.1 Min-max Check Node Processing Based on Power Repre- sentation .......................... 115 5.2.2 Min-max CNU Architectures Based on Power Represen- tation ............................ 119 5.2.3 Reducing Shifting Latency Overhead ........... 124 5.3 Check Node Processing for the SMSA .............. 125 5.3.1 SMSA Check Node Processing Based on Power Represen- tation ............................ 126 5.3.2 SMSA CNU Architecture Based on Power Representation 128 5.4 Complexity Comparisons ..................... 132 5.5 Summary .............................. 136 Chapter 6. Conclusions and Future Research 137 6.1 Conclusions ............................ 137 6.2 Future Research .......................... 138 Bibliography 140 iv List of Tables 3.1 Example of Algorithm F ..................... 42 3.2 Example for Function Φ ..................... 49 3.3 Example for Function Θ ..................... 51 3.4 Configurations and sizes of memories .............. 76 3.5 CNU complexities for (837, 726) QCNB-LDPC code ...... 77 3.6 Decoder complexities for (837, 726) QCNB-LDPC code .... 77 4.1 Word lengths of reliability measures used in simulations .... 84 4.2 Extra variables need to be stored to implement E-IHRB-MLGD 98 4.3 Extra value updating in the E-IHRB decoding ......... 101 4.4 NB-LDPC decoder complexities ................. 111 4.5 Generalized complexity analyses for IHRB and E-IHRB decoders112 4.6 FPGA Implementation results of (403, 226) QCNB-LDPC de- coders on Xilinx Virtex-5 XC5VLX200t Device ......... 113 4.7 Synthesis results using SMIC 0.18μm CMOS technology . 113 5.1 Latency overhead reduction examples for codes over GF (32) . 125 5.2 Finite field element additions over GF (8) for Step I3a ..... 129 5.3 Finite field element additions over GF (8) for Step I3b ..... 130 5.4 Synthesis results of the Min-max CNUs in Fig. 5.1 and [1] using IBM 90nm CMOS Technology .................. 132 5.5 Synthesis results for Min-max CNUs over GF (8) using IBM 90nm CMOS Technology ..................... 134 5.6 Synthesis results for K = 4 SMSA CNUs over GF (32) with 90nm CMOS Technology ..................... 135 v List of Figures 2.1 Trellis of variable-to-check messages ............... 21 2.2 FERs of a (744, 653) NB-LDPC code over GF (25) and a (3683, 3175) binary LDPC code under AWGN channel ........ 25 2.3 BERs of a (744, 653) NB-LDPC code over GF (25) and a (3683, 3175) binary LDPC code under AWGN channel ........ 26 2.4 FERs of a (248, 124) NB-LDPC code over GF (25) and a (1270, 635) binary LDPC code under AWGN channel ......... 27 2.5 BERs of a (248, 124) NB-LDPC code over GF (25) and a (1270, 635) binary LDPC code under AWGN channel ......... 28 2.6 FER of a (837, 726) QCNB-LDPC code over GF (25) with 15 iterations and nm =16...................... 29 2.7 WERs of NB-LDPC decoding for a (255, 175) cyclic EG code over GF (28)............................ 32 2.8 WERs of NB-LDPC decoding for a (403, 226) QC code over GF (25)............................... 33 3.1 Trellises of variable-to-check messages: (a) original trellis; (b) reordered trellis .......................... 37 3.2 FERs of a (837, 726) QCNB-LDPC code over GF (25) and a (4191, 3602) binary LDPC with 15 decoding iterations under the AWGN channel ........................ 43 3.3 FERs of a (248, 137) QCNB-LDPC code over GF (25) and a (1270, 652) binary LDPC with 15 decoding iterations under the AWGN channel .......................... 44 3.4 Architecture of trellis basis constructor ............. 55 3.5 Architecture of minimum basis constructor ........... 58 3.6 Architecture of basis recovery module .............. 62 3.7 Top level architecture of QCNB-LDPC decoder ........ 66 3.8 Scheduling of the computations in the decoding process .... 71 4.1 WERs of the E-IHRB-MLGD for a (255, 175) cyclic EG code over GF (28)............................ 84 vi 4.2 WERs of the E-IHRB-MLGD for a (403, 226) QC code over GF (25)............................... 85 4.3 (a) IHRB-MLGD architecture for QCNB-LDPC codes (b) VNU architecture when all q messages are kept ............ 88 4.4 IHRB-MLGD architecture for cyclic NB-LDPC codes ..... 90 4.5 Computation scheduling in IHRB-MLGD for cyclic codes . 91 4.6 VNU architecture when nm <qmessages are kept . .... 94 4.7 E-IHRB-MLGD architecture for cyclic NB-LDPC codes .... 99 4.8 Architecture for the selector ................... 100 4.9 VNU architecture modification .................. 101 5.1 Proposed CNU modified from [1] for GF (8).......... 119 5.2 Proposed CNU modified from [2] for GF (8).......... 122 5.3 Proposed architecture for the SMSA over GF (8)........ 128 vii Acknowledgments First and foremost, I wish to thank my advisor, Professor Xinmiao Zhang, for her guidance and support throughout my studies and research at Case Western Reserve University. I am very grateful for her recognition, in- spiration, and the exposure and opportunities that I have received during the course of my study. I would also like to thank Professor Christos Papachristou, Professor Daniel Saab and Professor Francis Merat for their support as members of my defense committee. I am also grateful to Prof.
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