DIGITAL SYSTEM FUNDAMENTALS (ECE421) COURSE / CODE FUNDAMENTAL (ECE422)

Medium Scale Integrated (MSI) devices It’s sometimes not reasonable to do all the design work at the gate-level. For example, it is a common practice to use full-adders as the building blocks in building a ripple-carry . When designing circuits, there are certain building blocks that are used over and over again. Thus, being familiar with a set of building blocks that are commonly used can make designing digital devices easier. Building blocks that are more complex than gates are sometimes called medium-scale integrated devices, or MSI devices for short. Exactly what makes a device “medium” in scale rather than “large” or “very large” (as in VLSI) is not always agreed on, but generally it’s all right stick with devices that are fairly simple and where small versions of them can be implemented in a couple dozen gates or so.

Special Combinational Logic Circuits 1. Adders A half adder can add two bits. It has two inputs, generally labeled A and B, and two outputs, the sum S and carry C. S is the two-bit XOR of A and B, and C is the AND of A and B. Essentially the output of a half adder is the sum of two one-bit numbers, with C being the most significant of these two outputs. A half adder is a logical circuit that performs an addition operation on two binary digits. The half adder produces a sum and a carry value which are both binary digits. The drawback of this circuit is that in case of a multi-bit addition, it cannot include a carry.

Sum(S) = A B and Carry(C) = AB

A full adder is capable of adding three bits: two bits and one carry bit of earlier calculation. It has three inputs - A, B, and carry Cin, such that multiple full adders can be used to add larger numbers. Hence, a full adder can perform an addition operation on three binary digits. The full adder produces a sum and carry value, which are both binary digits.

Exercises: Q1. Draw the half-adder circuit using NAND gates only. Q2. Draw the truth table for a full adder and write down the output expressions. Q2. Implement the operation of a full adder using two half-adders and an OR gate. Q3. What are the advantages of full-adder over half-adder? Mohd Uzir Kamaluddin / July 2019 page 1

Parallel Binary Adders As we discussed that a single full adder performs the addition of two one bit numbers and an input carry. For performing the addition of binary numbers with more than one bit, more than one full adder is required depends on the number bits. Thus, a parallel adder is used for adding all bits of the two numbers simultaneously.

By connecting a number of full adders in parallel, n-bit parallel adder is constructed. From the below figure, it is to be noted that there is no carry at the least significant position, hence we can use either a half adder or made the carry input of full adder to zero at this position.

The figure below shows a parallel 4-bit binary adder which has three full adders and one half-adder. The two binary numbers to be added are A3A2A1A0 and B3B2B1B0 which are applied to the corresponding inputs of full adders. This parallel adder produces their sum as C4S3S2S1S0 where C4 is the final carry.

In the 4-bit adder, first block is a half-adder that has two inputs as A0B0 and produces their sum S0 and a carry bit C1. Next block should be full adder as there are three inputs applied to it. Hence this full adder produces their sum S1 and a carry C2. This will be followed by other two full adders and thus the final sum is C4S3S2S1S0. Most commonly Full Adders designed in dual in-line package integrated circuits. A typical 74LS83 is a 4-bit full adder. Arithmetic and Logic Unit of a unit computer consist of these parallel adders to perform the addition of binary numbers.

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2. Subtractor is a circuit which is used to subtract two binary number (digit) and provides Difference and Borrow as output. Half Subtractor is used for subtracting one single bit binary digit from another single bit binary digit.

A logic circuit which is used for subtracting three single bit binary digit is known as Full Subtractor.

Parallel Binary To perform the subtraction of binary numbers with more than one bit is performed through the parallel subtractors. This parallel subtractor can be designed in several ways, including combination of half and full subtractors, all full subtractors, all full adders with subtrahend complement input, etc.

The below figure shows a 4-bit parallel binary subtractor formed by connecting one half subtractor and three full subtractors.

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In this subtractor, 4-bit minuend A3A2A1A0 is subtracted by 4-bit subtrahend B3B2B1B0 and gives the difference output D3D2D1D0. The borrow output of each subtractor is connected as the borrow input to the next preceding subtractor. It is also possible to design a 4 bit parallel subtractor 4 full adders as shown in the below figure. This circuit performs the subtraction operation by considering the principle that the addition of minuend and the complement of the subtrahend is equivalent to the subtraction process. We know that the subtraction of A by B is obtained by taking 2’s complement of B and adding it to A. The 2’s complement of B is obtained by taking 1’s complement and adding 1 to the least significant pair of bits.

Hence, in this circuit 1’s complement of B is obtained with the inverters (NOT gate) and a 1 can be added to the sum through the input carry.

Parallel Adder / Subtractor The operations of both addition and subtraction can be performed by a one common binary adder. Such binary circuit can be designed by adding an Ex-OR gate with each full adder as shown in below figure. The figure below shows the 4-bit parallel binary adder/subtractor which has two 4 bit inputs as A3A2A1A0 and B3B2B1B0. The mode input control line M is connected with carry input of the least significant bit of the full adder. This control line decides the type of operation, whether addition or subtraction.

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When M = 1, the circuit is a subtractor and when M = 0, the circuit becomes adder. The Ex-OR gate consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR of 0 produce B. Then full adders add the B with A with carry input zero and hence an addition operation is performed. When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s complement operation. Therefore, the subtraction operation is performed. Note: B  0  B and B 1 B

Exercises: Q1. Show on the parallel adder/subtractor circuit the operation of 10012 + 01112. Q2. Show on the parallel adder/subtractor circuit the operation of 11012 - 10012.

3. Multiplier A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. A simple 2-bit multiplier, A2A1 x B2B1 can be designed using logic gates as shown in the truth table below.

Another method commonly used is to do multiplication by repeated addition. The multiplicand is added by itself the number of times as indicated by the multiplier. See the block diagram.

To increase the speed of the multiplication process, other method of multiplication is used such as:  Shift and add multiplier  Serial multiplier Mohd Uzir Kamaluddin / July 2019 page 5  Serial/Parallel multiplier  Array multiplier  Booth multiplier

Exercise: The multiplication of a 3-bit number B by a 4- bit number A is illustrated below. i) Based on the multiplication process shown, implementation a 4-bit x 3-bit multiplier using adders. ii) Show the multiplication of 10112 by 1002 by clearly indicating the values at the inputs and outputs.

4. Comparator A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. Comparators are used in central processing units (CPUs) and (MCUs). An XNOR gate is a basic comparator, because its output is "1" only if its two input bits are equal.

The truth table shows a 1-bit comparator and its logic circuit is given below.

Figure below shows the logic diagram and truth table for a 2-bit comparator.

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A 4-bit magnitude comparator TTL 74LS85.

An 8-bit word comparator.

For comparators that compares 3 bits or more, the truth table method of designing comparators will result in a huge truth table.

Design of a 4-bit comparator using the deduction method.

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Exercises: a) What does a comparator circuit do? What are the output of a comparator? b) A comparator determines when two binary numbers are equal, true or false? c) If a comparator compares two 2-bit numbers A, B and produces the output D1 = 1 if A B Derive the expressions for output O1, O2 and O3, then implement the comparator circuit for the outputs using suitable logic gates.

5. Decoders and Encoders In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n- to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output". The diagram below shows the 2 to 4 binary decoder with active HIGH output.

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The IC Decoder 74LS138 is shown in the diagram. It is a 3 to 8 decoder, with active high output. Some binary decoders have an additional input pin labelled “Enable” that controls the outputs from the device. This extra input allows the decoders outputs to be turned “ON” or “OFF” as required. These types of binary decoders are commonly used as “memory address decoders” in memory applications.

A 4 to 16 decoder can be designed using two 3 to 8 decoders as shown.

Mohd Uzir Kamaluddin / July 2019 page 9 But some binary decoders are constructed using NAND gates instead of AND gates for their decoded output, since NAND gates are cheaper to produce than AND’s as they require fewer transistors to implement within their design. The use of NAND gates as the decoding element, results in an active-“LOW” output while the rest will be “HIGH”. As a NAND gate produces the AND operation with an inverted output, the NAND decoder looks like this with its inverted truth table.

Implementation of logic functions using a decoder: A decoder can be used to implement logic functions. Since all the minterms of the function are available at the output then there is no need for simplification. All is needed is an OR gate for each function to sum the required minterms. As an example, implement the following functions using an appropriate decoder and OR gates.

S(x,y,z) = ∑m(1,2,4,7) and C(x,y,z) = ∑m(3,5,6,7)

The implementation using 3 to 8 decoder active high output and OR gates is as shown.

If an active low output decoder is used, the implementation uses a NAND gate.

Exercise 1: a) Explain what is a decoder circuit. b) A decoder detects the presence of a specified combination of input bits, true or false? c) Explain why some decoder has active-high output and some has active-low output. d) The 4-line to-10-line decoder and the 1-of-10 decoder are two different types, true or false?

Mohd Uzir Kamaluddin / July 2019 page 10 e) Design a circuit that will detect the three-bit binary code at its input. The output must be logic HIGH to indicate the corresponding binary code. (Hint: decoder circuit). f) Design a circuit that will detect the three-bit binary code at its input. The output must be logic LOW to indicate the corresponding binary code. (Hint: decoder circuit).

Exercise 2: Given the function F  A[BC (A B  C  D)] a) Implement the function F using 4 to 16 decoder with active high output. b) Implement the function F using 3 to 8 decoder with active high output. c) Implement the function F using 4 to 16 decoder with active low output.

Exercise 3: a) Design a full-adder logic circuit using an active-low 2-to-4 decoder(s) and suitable logic gates. b) A 3 to 8 decoder is connected as shown, where x, y and z are inputs (z is the MSB) and F is an output. Write down the expression for F.

An encoder is a digital function that performs the inverse operation of a decoder. An encoder has 2n (or fewer) input lines and n output lines. The output lines generate the binary code corresponding to the input value.

One of the main disadvantages of standard digital encoders is that they can generate the wrong output code when there is more than one input present at logic level “1”. One simple way to overcome this problem is to “Prioritize” the level of each input pin and if there was more than one input at logic level “1” the actual output code would only correspond to the input with the highest designated priority. Then this type of digital encoder is known commonly as a Priority Encoder or P-encoder for short.

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Exercises: a) Explain what is an encoder circuit. b) An encoder essentially performs a reverse decoder function, true or false? c) What happen if more than one input of an encoder is active? d) An incomplete truth table for an octal-to-binary priority encoder with valid bit indicator is given below. Complete the table. D7 has the highest priority and D0 the lowest.

6. (MUX) and De-Multiplexer (DEMUX) A multiplexer or MUX is a device that performs multiplexing; it selects one of many analog or digital input signals and forwards the selected input into a single output line. A multiplexer of 2n inputs has n select bits, which are used to select which input line to send to the output. A multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal.

A simple 2-line to 1-line (2-to-1) multiplexer from basic logic NAND gates.

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Logic diagrams of 4 input multiplexer, a) using NAND gates only b) using AND, OR and NOT gates.

A de-multiplexer (or DEMUX) is a device taking a single input signal and selecting one of many data-output-lines, which is connected to the single input. A multiplexer is often used with a complementary de-multiplexer on the receiving end. A DEMUX is also known as data distributor.

The 1 to 4 DEMUX can be designed using logic gates as shown.

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Another way to implement a 1 to 4 DEMUX is by using a 2 to 4 decoder with AND gates as shown.

Implementation of logic functions using Multiplexer A multiplexer can be used to implement logic functions. There are a few ways to design such circuit, depending on the multiplexer used. Consider the function: f (A,B,C)  AB  BC  AC a) Using an 8 to 1 multiplexer The function f(A,B,C) is tabulated in the form of truth table, and then the logic function is implemented directly using the 8-1 multiplexer.

A B C f 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1

b) Using a 4 to 1 multiplexer For this design, the input A and B is connected to the select lines C1 and C2. The expression for mux input is obtained by comparing the output f with the input which is not used, that is C. Thus the method is called residue method.

MUX A B C f Input 0 0 0 0 I0 = C 0 0 1 1 0 1 0 1 I1 = 1 0 1 1 1 1 0 0 0 I2 = 0 1 0 1 0 1 1 0 0 I3 = C 1 1 1 1

Mohd Uzir Kamaluddin / July 2019 page 14 Exercise 1: a) What is the function of a multiplexer circuit? b) A multiplexer is a logic circuit that allows digital information from a single source to be routed onto several lines, true or false? c) Draw the block diagram of a 4 to 1 MUX and its truth table. d) For the MUX in part b) above, determine the output for the following states: D0=0, D1=1, D2=1, D3=0, S0=1, S1=0. e) Design a logic circuit to produce a HIGH output if and only if the input, represented by a 4-bit binary number, is greater than twelve or less than three. First develop the truth table, write the Boolean function, simplify it using K-map and then draw the logic diagram. f) Implement the logic circuit in part d) above using 8 to 1 MUX, and other logic gates if necessary. g) What is the function of a de-multiplexer circuit? h) Given the function F  A[BC (A B  C  D)] i) Implement the function F using 16 -1 MUX. ii) Implement the function F using 8 - 1 MUX. iii) Implement the function F using 4 - 1 MUX. iv) Implement the function F using 2 - 1 MUX.

Exercise 2: A Boolean function F of four variables A, B, C and D is given by the sum of minterms: F = ∑m(1 ,2, 4, 7, 8, 10, 12) a) Implement the function F using a 16-to-1 line multiplexer. b) Implement the function F using an 8-to-1 line multiplexer. c) Implement the function F using an 4-to-1 line multiplexer. d) Implement the function F using an 2-to-1 line multiplexer.

Exercise 3: Determine the Boolean function that the following circuits implements.

A special decoder: 7-segment decoder/driver A seven-segment display is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot- matrix displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information.

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The common way of driving the 7-segment display is by the use of a special IC called the 7-segment decoder/driver. This IC receives input as BCD and output the 7-segment codes for the 7-segment display. The 74LS47 has active-low outputs, and can only be used to drive common anode 7-segment display unit. BCD input Display 0011 3 0101 5 1001 9

Exercise Q1 Implement a full adder circuit using: a) a 3-to-8 active high output decoder. b) 4-to-1 .

Exercise Q2 a) Draw the logic circuit of the following function using a 3-to-8 active high output decoder. F = ∑m(1 ,2, 4, 6, 7) b) Draw the logic circuit of the following function using a 3-to-8 active low output decoder. F = ∑m(0 ,2, 3, 5, 6)

Exercise Q3 A Boolean function F of four variables A, B, C and D is given by the sum of minterms: F = ∑m(1 ,2, 4, 7, 8, 10, 12, 14) a) Implement the function F using a 16-to-1 line multiplexer. b) Implement the function F using an 8-to-1 line multiplexer. c) Implement the function F using a 4-to-1 line multiplexer.

Exercise Q4 By creating the truth table for the following decoder circuit (inputs are a,b,c,d and output is F), determine the SOP short hand expression for F. (Answer: F=Σm(0,1,2,3,4,5,12,13))

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