"SNR=6.02N + 1.76Db," and Why You Should Care by Walt Kester REV
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
SSB Exciter Circuits Using a New Beam-Deflection Tube
8/24/2008 7360 Circuits SSB Exciter Circuits Using a New Beam-Deflection Tube Practical Circuit Data for Modulation, Frequency Conversion and Detection BY H. C. VANCE K2FF Extracted from QST March 1960 The new beam deflection tube described here appears to be a bulb-full of versatility, with more applications than were visualized when the tube was under development as an improved type of balanced modulator. This article tells how the 7360 can be put to work in a number of ways in the amateur field, particularly in SSB transmission and reception. A new beam-deflection tube, the RCA-7360, incorporates novel design features which, with suitable circuits, allow it to be used in many kinds of applications with improved performance at frequencies at least as high as 100 megacycles. The tube was originally developed to provide a high degree of stable carrier suppression when used as a balanced modulator in single-sideband service. More than 60 dB of carrier suppression has been obtained with it as a balanced modulator in SSB exciters of both the filter and phasing types. It is of course equally valuable in double-sideband suppressed carrier service. Frequency conversion, product detection, synchronous detection, single-ended to push-pull phase inversion, switching circuits, fader circuits and compressor- expander-limiter circuits are among the many other interesting applications in which the unique properties of this new tube have been found to be valuable. In this article circuits will be described which make use of the 7360 as a balanced modulator, a frequency mixer and a product detector. -
Brookhaven National Laboratory
BROOKHAVEN NATIONAL LABORATORY quarterly Progress Report April 1 - June 30~ 1950 Associated Universities Inc. under contract with the United States Atomic Energy Commission. BROOKHAVEN NATIONAL LABORATORY QUARTERLY PROGRESS REPORT April 1 - June 30, 1950 Associated Universities, Inc~ under contract with the United States Atomic Energy Commission Printed at Upton, New York, for distribution to individuals and organizations associated with the national atomic energy program. July, 1950 7.00 copies FOREWORD This is the second of a series of Quarterly Progress Re ports. While most of the departments have summarized their work or used a form comparable to abstracts, the Chemistry Department has given both abstracts and complete reports on its work. The major part of the progress in the Reactor Science and Engineer ing Department is being presented simultaneously in a separate classified report. iii CONTENTS Foreword • • • iii· Physics Department • 1 Instrumentation and Health Physics Department 15 Accelerator Projeot • • 22 Chemistry Department • 28 Reactor Science and Engineering Department • 91 Biology Department • • 96 Medioal Department • • 107 PHYSICS DEPARTMENT The research progress of the Physics Department is described under five subdivisions: 1) dynamic properties of atomic nuclei, 2) stationary proper ties of nuclei, 3) high energy particle physics, 4) research in other branches of physics carried out with the use of neutrons or other nuclear techniques, and 5) theoretical topics not included under the above headings. Under sub division (1) are included investigations of radioactivity and nuclear reac tions induced by gamma rays, neutrons, and particles accelerated in the cyqlotron or Van de Graaff accelerator. Under (2) are the measurements of nuclear mass and moment. -
Clock Jitter Effects on the Performance of ADC Devices
Clock Jitter Effects on the Performance of ADC Devices Roberto J. Vega Luis Geraldo P. Meloni Universidade Estadual de Campinas - UNICAMP Universidade Estadual de Campinas - UNICAMP P.O. Box 05 - 13083-852 P.O. Box 05 - 13083-852 Campinas - SP - Brazil Campinas - SP - Brazil [email protected] [email protected] Karlo G. Lenzi Centro de Pesquisa e Desenvolvimento em Telecomunicac¸oes˜ - CPqD P.O. Box 05 - 13083-852 Campinas - SP - Brazil [email protected] Abstract— This paper aims to demonstrate the effect of jitter power near the full scale of the ADC, the noise power is on the performance of Analog-to-digital converters and how computed by all FFT bins except the DC bin value (it is it degrades the quality of the signal being sampled. If not common to exclude up to 8 bins after the DC zero-bin to carefully controlled, jitter effects on data acquisition may severely impacted the outcome of the sampling process. This analysis avoid any spectral leakage of the DC component). is of great importance for applications that demands a very This measure includes the effect of all types of noise, the good signal to noise ratio, such as high-performance wireless distortion and harmonics introduced by the converter. The rms standards, such as DTV, WiMAX and LTE. error is given by (1), as defined by IEEE standard [5], where Index Terms— ADC Performance, Jitter, Phase Noise, SNR. J is an exact integer multiple of fs=N: I. INTRODUCTION 1 s X = jX(k)j2 (1) With the advance of the technology and the migration of the rms N signal processing from analog to digital, the use of analog-to- k6=0;J;N−J digital converters (ADC) became essential. -
Effective Bits
Application Note Effective Bits Effective Bits Testing Evaluates Dynamic Performance of Digitizing Instruments The Effective Bits Concept desired time resolution, run the digitizer at the requisite Whether you are designing or buying a digitizing sys- sampling rate. Those are simple enough answers. tem, you need some means of determining actual, Unfortunately, they can be quite misleading, too. real-life digitizing performance. How closely does the While an “8-bit digitizer” might provide close to eight output of any given analog-to-digital converter (ADC), bits of accuracy and resolution on DC or slowly waveform digitizer or digital storage oscilloscope changing signals, that will not be the case for higher actually follow any given analog input signal? speed signals. Depending on the digitizing technology At the most basic level, digitizing performance would used and other system factors, dynamic digitizing seem to be a simple matter of resolution. For the performance can drop markedly as signal speeds desired amplitude resolution, pick a digitizer with the increase. An 8-bit digitizer can drop to 6-bit, 4-bit, requisite number of “bits” (quantizing levels). For the or even fewer effective bits of performance well before reaching its specified bandwidth. Effective Bits Application Note Figure 1. When comparing digitizer performance, testing the full frequency range is important. If you are designing an ADC device, a digitizing instru- components. Thus, it may be necessary to do an ment, or a test system, it is important to understand the effective bits evaluation for purposes of comparison. If various factors affecting digitizing performance and to equipment is to be combined into a system, an effective have some means of overall performance evaluation. -
Noise-Shaping Sar Adcs
NOISE-SHAPING SAR ADCS by Jeffrey Alan Fredenburg A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of Michigan 2015 Committee: Professor Michael P. Flynn, Chair Professor Zhong He Professor Dave D. Wentzloff Professor Zhengya Zhang “Nobody tells this to people who are beginners; I wish someone told me. All of us who do creative work, we get into it because we have good taste. But there is this gap. For the first couple years you make stuff; it’s just not that good. It’s trying to be good, it has potential, but it’s not. But your taste, the thing that got you into the game, is still killer. And your taste is why your work disappoints you. A lot of people never get past this phase. They quit. Most people I know who do interesting, creative work went through years of this. We know our work doesn’t have this special thing that we want it to have. We all go through this. And if you are just starting out or you are still in this phase, you gotta know it's normal and the most important thing you can do is do a lot of work. Put yourself on a deadline so that every week you will finish one story. It is only by going through a volume of work that you will close that gap and your work will be as good as your ambitions. And I took longer to figure out how to do this than anyone I’ve ever met. -
MT-200: Minimizing Jitter in ADC Clock Interfaces
Applications Engineering Notebook MT-200 One Technology Way • P. O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Minimizing Jitter in ADC Clock Interfaces by the Applications Engineering Group POWER SUPPLY Analog Devices, Inc. INPUT V REF DATA ANALOG OUTPUT IN THIS NOTEBOOK INPUT ADC Since jitter around the threshold region of a clock interface CLOCK FPGA INTERFACE can corrupt the dynamic performance of an analog-to- INPUT CONTROL digital converter (ADC), this notebook provides an overview of clocking considerations and jitter-reduction techniques. The Applications Engineering Notebook Educational Series TABLE OF CONTENTS Clock Input Noise.............................................................................. 2 Frequency Domain View ............................................................. 3 Time Domain View ....................................................................... 2 Phase Domain View ..................................................................... 4 Effect of Slew Rate..................................................................... 3 Solutions for Clocking Converters ............................................. 5 REVISION HISTORY 1/12—Revision 0: Initial Version Rev. 0 | Page 1 of 8 MT-200 Applications Engineering Notebook CLOCK INPUT NOISE Jitter around the threshold region of the clock interface can TIME DOMAIN VIEW corrupt the timing of an analog-to-digital converter (ADC). For example, jitter can cause the ADC to capture a sample at the wrong time, resulting in false sampling of the analog input and reducing the signal to noise (SNR) ratio of the device. A reduction in jitter can be achieved in a number of different ways, including improving the clock source, filtering, frequency division, and clock circuit hardware. This document provides dV suggestions on how to improve the clock system to achieve the best possible performance from an ADC. Noise in the circuit between the clock and ADC is the root ERROR VOLTAGE cause of clock jitter. -
An95091 Application Note Understanding Effective Bits
AN95091 APPLICATION NOTE UNDERSTANDING EFFECTIVE BITS Tony Girard, Signatec, Design and Applications Engineer INTRODUCTION One criteria often used to evaluate an Analog to Digital Converter (ADC) or data acquisition system is the effective number of bits achieved. The effective number of bits provides a means to evaluate the overall performance of a system. However, like any other parameter, an understanding of the theory behind the effective bits, and different methods used to determine effective bits is necessary to properly compare components and systems. The intent of this application note is to provide the basic theory behind effective bits, describe different methods used to determine effective bits, and to explain the limitations in its usage. NUMBER OF BITS VERSES EFFECTIVE BITS The number of bits in a data acquisition system is normally specified as the number of bits of the digitizer. Any data acquisition system, or ADC, has inherent performance limitations. When evaluating an acquisition system the effective number of bits provided by the system can useful in determining if the system is right for the application. There are many sources of error in an acquisition system. Considering a system in terms of effective bits, all error sources are included. Evaluation of system performance is made without the need to consider the individual error sources, all of which may not be characterized by the manufacturer. THE PERFECT SYSTEM A perfect data acquisition system is one in which the captured analog signal is free from noise and distortion. The system is free from any frequency dependent performance characteristics, up to the maximum sampling rate and the bandwidth limit of the system. -
Analog Digital Conversion
Analog digital conversion (in beam instrumentation systems) Marek Gasior CERN Beam Instrumentation Group BI CAS 2018, Tuusula, Finland Introduction . One hour lecture for the topic described in many thick books and lectured at universities over months . More standard topic than for most of other lectures . Focus on aspects important in beam instrumentation . What should I take into consideration while choosing an ADC for my system ? Outline: . ADC fundamentals . Which sampling rate do I need ? . How many bits do I need ? . A glance on three datasheets . A few examples of ADC modules 2 Literature . “From analog to digital” by Jeroen Belleman . two hour lecture during CAS 2008 in Dourdan . lecture: http://cas.web.cern.ch/files/lectures/dourdan-2008/belleman.pdf . paper (pages 281 – 316): http://cdsweb.cern.ch/record/1071486/files/cern-2009-005.pdf . “Art of Electronics, 3rd edition”, P. Horowitz, W. Hill . Chapter 13: “Digital meets analog”, pages 879 – 955 . Excellent book . For everybody, beginners and experts 3 Why ADCs ? What is an ADC ? . Beam instrumentation signals (voltages, currents, light, …) are analog and the control room is “numeric” . Processing of numbers is by far more powerful than processing of analog signals . ADCs are very important parts of BI systems and often put a limit for the system performance . An ADC is an electronic circuit which converts an analog signal (continuous time, continuous amplitude) into a digital signal (discrete time, discrete amplitude = series of pairs of numbers) . An ADC is an integrated circuit (except very special cases) . Unfortunately an ADC chip does not work alone . Digital data must be taken and send further 4 Sampling 5 Sampling 6 Sampling 7 Sampling and quantization 8 Sampling and quantization 9 Sampling and quantization 10 ADC errors 11 Quantization error . -
Understanding Noise, ENOB, and Effective Resolution in Analog-To-Digital Converters
Maxim > Design Support > Technical Documents > Application Notes > A/D and D/A Conversion/Sampling Circuits > APP 5384 Keywords: noise, ENOB, ADC, analog-to-digital converters, effective resolution, factory automation, temp sensing, data acquisition, delta-sigma, sigma-delta, SNR, NFR APPLICATION NOTE 5384 Understanding Noise, ENOB, and Effective Resolution in Analog-to-Digital Converters May 07, 2012 Abstract: Specifications such as noise, effective number of bits (ENOB), effective resolution, and noise- free resolution in large part define how accurate an ADC really is. Consequently, understanding the performance metrics related to noise is one of the most difficult aspects of transitioning from a SAR to a delta-sigma ADC. With the current demand for higher resolution, designers must develop a better understanding of ADC noise, ENOB, effective resolution, and signal-to-noise ratio (SNR). This application note helps that understanding. A similar version of this article was published in Planet Analog on September 16, 2011. One of the major trends for ADCs is the move toward higher resolution. The trend impacts a wide range of applications, including factory automation, temperature sensing, and data acquisition. The need for higher resolution is leading designers from traditional 12-bit successive approximation register (SAR) ADCs to delta-sigma ADCs with resolutions that reach 24 bits. All ADCs have a certain amount of noise. That includes both input-referred noise, which is inherent to the ADC, and quantization noise, which is the noise generated while the ADC is converting. Specifications such as noise, effective number of bits (ENOB), effective resolution, and noise-free resolution in large part define how accurate an ADC really is. -
An Experimental Investigation of a Low Distortion Mixer
AN EXPERIMENTAL INVESTIGATION OF A LOW DISTORTION MIXER USING A BEAM-DEFLECTION TUBE A THESIS Presented to the Faculty of the Graduate Division By Guy Herbert Smith, Jr. In Partial. Fulfillment of the Requirements for the Degree Master of Science in Electrical Engineering Georgia Institute of Technology June, I96I "In presenting the dissertation as a partial fulfillment of the requirements for an advanced degree from the Georgia Institute of Technology, I agree that the Library of the Insti tution shall make it available for inspection and circulation in accordance with its regulations governing materials of this type. I agree that permission to copy from, or to publish from, this dissertation may be granted by the professor under whose di rection it was written, or,, in his .absence, by the dean, of the Graduate Division when such copying or publication is solely for scholarly purposes and does not involve potential financial gain. It is understood that any copying from, or publication of, this dissertation which involves potential financial gain will not be allowed without written permission. " /y~ J* AN EXPERIMENTAL INVESTIGATION OF A LOW DISTORTION MIXER USING A BEAM-DEFLECTION TUBE Approved: - \ A . \ h T T - / /) l Date Approved by Chairman: 11 PREFACE This study is an experimental investigation of a low distortion mixer using a beam-deflection tube as the active circuit element. The material herein is limited in its scope in that the investigation covers only one of several basic circuit configurations that are suitable for use with beam-deflection tubes. It is also limited because only one type of beam-deflection tube has been considered. -
Proquest Dissertations
u Ottawa I.'I 'nr.i-i-ili' r;iii,iiliriiMr I '.iii.iihi's iini'.i'i illy ITTTT FACULTE DES ETUDES SUPERIEURES ^==1 FACULTY OF GRADUATE AND ET POSTOCTORALES U Ottawa POSDOCTORAL STUDIES L'UmversitcS eanadienne Canada's university Amine Kharrat AUTEUR DE LA THESE / AUTHOR OF THESIS M.Sc. (Systems Science) GRADE/DEGREE System Science FACULTE, ECOLE, DEPARTEMENT / FACULTY, SCHOOL, DEPARTMENT A Floating-point Analog-to-Digital Architecture for a Wide Range-Dynamic Acquisition System TITRE DE LA THESE / TITLE OF THESIS Voicu Groza DIRECTEUR (DIRECTRICE) DE LA THESE / THESIS SUPERVISOR CO-DIRECTEUR (CO-DIRECTRICE) DE LA THESE / THESIS CO-SUPERVISOR EXAMINATEURS (EXAMINATRICES) DE LA THESE/THESIS EXAMINERS Emil Petriu Tet Yeap Gary W. Slater Le Doyen de la Faculte des etudes superieures et postdoctorales / Dean of the Faculty of Graduate and Postdoctoral Studies A Floating-Point Analog-to-Digital Architecture for a Wide Range-Dynamic Acquisition System By Amine Kharrat A Thesis Presented to School of Graduate Studies and Research In partial fulfillment of the Requirements for the degree of Master of Science Master program in Systems Science University of Ottawa Ottawa, Ontario, Canada, 2009 Copyright © 2009 Amine Kharrat Library and Archives Bibliotheque et 1*1 Canada Archives Canada Published Heritage Direction du Branch Patrimoine de I'edition 395 Wellington Street 395, rue Wellington OttawaONK1A0N4 OttawaONK1A0N4 Canada Canada Your file Votre reference ISBN: 978-0-494-61147-0 Our We Notre reference ISBN: 978-0-494-61147-0 NOTICE: AVIS: The -
Understanding Key Parameters for RF-Sampling Data Converters
White Paper: Zynq UltraScale+ RFSoCs WP509 (v1.0) February 20, 2019 Understanding Key Parameters for RF-Sampling Data Converters Xilinx® Zynq® UltraScale+™ RFSoCs provide a single device RF-to-output platform for the most demanding applications. Updated performance metrics more accurately present the direct-sampling RF capabilities of these devices. ABSTRACT In direct-sampling RF designs, data converters are typically characterized by the NSD, IM3, and ACLR parameters rather than by traditional metrics like SNR and ENOB. In software-defined radio and similar narrow-band use cases, it is more important to quantify the amount of data-converter noise falling into the band(s) of interest; legacy data conversion metrics are ill-suited to do this. This white paper first presents the mathematical relationships underlying traditional ADC parameters—SFDR, SNR, SNDR (SINAD), and ENOB—and illustrates why these metrics provide good characterization of data converters in wide-band applications such as superheterodyne receivers. It then delineates why these metrics are inappropriate for data converters that do not function over their full Nyquist bandwidth, as in direct RF sampling applications like SDR. Derivation and measurement of NSD, IM3, and ACLR are described in detail, including use of the Xilinx RF Data Converter Evaluation Tool in the measurement of RF data conversion parameters. © Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. WP509 (v1.0) February 20, 2019 www.xilinx.com 1 Understanding Key Parameters for RF-Sampling Data Converters Introduction Analog data converters based on vacuum-tube technology were developed during World War II for message encryption systems.