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Low Power Conference L. Le Pailleur Technology Line Management Director STMicroelectronics, Crolles, France Biography Laurent Le Pailleur is director for advanced Cmos technology line with STMicroelectronics, Crolles France. He previously enjoyed various positions as head of technology management (semiconductor, packaging and IPs) with ST-Ericsson, audio/power management product line and 2.5G mobile platform/3G mobile digital System-on-Chip product management at ST. This allowed him to develop deep understanding on RF, analog and digital technologies, architecture and system partitioning. Prior to ST, he has been working on mixed-signal video systems and imaging digital processors design with Philips Semiconductors. In 1989, he received the degree in electrical engineering from Caen National Engineering School, the M.S. degree in instrumentation and automation from Caen University and the Business degree from IAE (Enterprise Administration Institute). He participated to numerous international conferences and hold multiple patents. Low Power Technology and it's application in SoC, Energy Efficient Designs and IoT - From Foundry Perspective R. Wijburg Senior VP and General Manager Fab Management GLOBALFOUNDRIES, Dresden, Germany Abstract We were used to walk down Moore's Law road over the last decades. This road brings our industry into the land of highly scaled technologies: 14, 10 and 7 nanometer. However economically one need to look on the next "hype" building up: "Internet of Things". Going down this road it is more critical to have the "right" technology at a certain "cost point" with focus on the application and with "build in connectivity". This automatically leads to Fully Depleted technologies with optional embedded RF capability as well as 28/22nm patterning with no need of extensive use of double patterning or new light sources for lithography. 28nm is known as the "sweet spot" in Foundry Industry for yield/performance AND cost. This node is in high volume production and will be the basis to add technology features like embedded RF, Flash, High Voltage (HV) or other value add solutions and is already predicted to have a long lifetime in our industry. In particular embedded RF and HV are key do communicate with the outside analog world in an power efficient and user friendly way. 22nm FD SOI is to a big portion technology wise proven in 28nm. FD SOI can operate at voltages down to approx. 0.4V with decent performance. This technology meets the desire of IOT products to be ultra mobile and enables small form factors. In addition this technology setup is simpler, requires much lower number of mask layers and is ideal for a broad range of IOT applications at lower cost. 22nm FDSOI makes "Faster, cooler, simpler" a reality and extends the "sweet spot" of 28nm to an even longer lifetime. Biography Dr. Rutger Wijburg is Senior Vice President and General Manager of GLOBALFOUNDRIES Fab 1 in Dresden, Germany. He is responsible for GLOBALFOUNDRIES' highend 300mm manufacturing operations in Europe. Prior to joining GLOBALFOUNDRIES in 2011, Rutger Wijburg was Senior Vice President and Operations Manager Front End at NXP Semiconductors (formerly Philips Semiconductors) in the Netherlands. In this role, he was responsible for the company's seven wafer fabs, led outsourcing and building strategic partnerships, and was in charge of real estate and facilities management. Rutger Wijburg has also held leadership positions with Mesa Research Institute in the Netherlands and CSEM SA in Switzerland. He holds both a Master of Science degree and Ph.D. in Electrical Engineering from the University of Twente, the Netherlands. T. Mikolajick scientific director NaMLab Gmbh / TU Dresden, Dresden, Germany Biography Thomas Mikolajick received the Diploma (Dipl.-Ing.) in electrical engineering from the University Erlangen- Nuremberg in 1990 and his phD in electrical engineering in 1996. From 1996 till 2006 he was in the semiconductor industry developing CMOS processes,ferroelectric memories, emerging non-volatile memories and Flash memories first at Siemens Semiconcuctor and later at Infineon. In late 2006 he moved back to academia taking over a professorship for material science of electron devices and sensors at the University of Technology Freiberg, and in October 2009 he started at Technische Universität Dresden were he now holds a professorship for nanoelectronic materials in combination with the position of scientific director at NaMLab GmbH. Since April 2010 he is the coordinator of the "Cool Silicon" Cluster in Dresden. Prof. Mikolajick is author or co-author of about 220 Publications in scientific journals or at scientific conferences and inventor or co-inventor of about 50 patents. Why is fully depleted SOI best for ultra-low power? M. Haond Director STMicroelectronics, CROLLES, France Abstract Depleted devices are definitely the solution to maintain Moore's Law trends. We will explicit the advantages of the use of depleted channel devices for reaching very low threshold voltages, thanks to an aggressive electrostatic allowing a tight control of the short channel effects. This helps a lot for one of the key application fields for these devices: Low Voltage and Low Power applications for the handheld, the mobile or any other IOT business. 2 alternative process constructions are proposed today: one 2D silicon film running over an oxide (UTBB FDSOI) or a 3D vertical thin wall (or fin) wrapped around by a Gate (FinFET). However, we will explain why FDSOI has some additional features allowing to further lower the applied supply voltage to the device and therefore better suited for Low Voltage applications : firstly, its undoped channel provides better variability control with a better Vt mismatch and a lower SRAM Vmin; secondly, its unique access to back-biasing allows to further reduce locally and/or temporally the Vt of the transistors by appling a forward body biasing through the virtual back gate formed by the underlying substrate through the Buried Oxide in the 2D FDSOI construction. Biography Received a MS Degree from Université Lyon1 in 1976 and an Electrical Engineering degree from Ecole Nationale Supérieure des Télécommunications (ENST) de Paris in 1978. He joined France Telecom Research Center (CNET) in Paris, where he worked on III-V Laser Diode Optoelectronics for Optical Communications. In 1981, he moved to CNET in Grenoble, where he was engaged in Material studies: Rapid Thermal Anneal of implanted junctions; SOI Material fabrication and characterisation. He became Team leader for PDSOI integration of a CMOS 2 µm process. He led the advanced CMOS & BiCMOS Process Integration Department. In 1996, he joined ST-Crolles as Process Integration Manager and developed the 0.18 and the 0.13µm CMOS. In 2000 he was assigned by ST to set-up a Central R&D research group for the future CMOS & Interconnect in connection with CEA-Leti. He was nominated Technical R&D Director, leading the 90 nm, the 45 and 40nm CMOS developments. In 2010 he launched the FDSOI Project with the 28FDSOI Integration and in 2012 the 14FDSOI. He authored or coauthored over 100 publications and owns more than 30 patents. He has been a Member of the Technical or Steering Committee of major Conferences (IEDM, IEEE SOI/S3S Conference, ESSDERC, ULIS-EUROSOI). He is presently Technical Director and Fellow, managing the 14FDSOI Project. 28/22nm RF Technology status and future roadmap D. Harame CTO RF Technology and Enablement Global Foundries, Burlington, United States Abstract The IoT with billions of connected devices will require wireless connectivity, faster processing, faster data rates, longer battery life and lower cost. For the wireless connectivity, especially IOT, low power, cost, and RF performance are the most important considerations. FDSOI offers a unique combination of low cost, low power, and RF performance which nicely meets these targets. This presentation will focus on the RF performance. All RF designs require RF passives including RF capacitors (MOMs), Inductors, Varactors, and Resistors, supported with models tuned to S-parameter data. An RF custom PDK with RF models for all RF devices is provided. 22FDX transistors have excellent electrostatics compared to bulk. The HiK Metal Gate stack and short gate length (Lg) provide high transconductance (gM > 2mS/um) with low gDS. The high gM, and low gDS gives a high self gain, important for all RF/Analog applications. The FDSOI transistor is architected for effective body biasing. The Back Gate Bias (VBG) enables reducing the threshold voltage (FBB) for increased current drive or increasing the threshold voltage (RBB) for decreased leakage. The RF performance of 28nm FDSOI has been published by Lucci as fT= 380 GHz and fMAX= 390 GHz (2015 IMS Symposium). This combination of high fT and fMAX is amongst the highest achieved for any RFCMOS technology and clearly demonstrates the performance potential of FDSOI technologies. Simulations show 22FDX has better AC gain than bulk 28nm SLP technology. Using the back gate to lower Vt expands the voltage range over which a high gM is found. This expanded dynamic range is also true for fT and fMAX. In Summary, FDSOI makes an excellent RF technology. Biography David Harame joined GLOBALFOUNDRIES in 2014. David is a Global Fellow and the Chief Technical Officer for RF Development and Enablement. Prior to GLOBALFOUNDRIES worked for IBM where he was an IBM Fellow and was also the CTO for RF Development and Enablement. David has worked in the area of RF technology for over 30 years. In 2005 David was awarded the IEEE Daniel E Noble Award "For the development of manufacturable Silicon Germanium, HBT Bipolar and BiCMOS technologies." He also received the IEEE BCTM Award for his work in SiGe BiCMOS. David is an IEEE Fellow. Ferroelectric Hafnium Oxide: Material Innovation for Ferroelectric Memories J. Müller Group Manager NVM Fraunhofer IPMS, CNT, Dresden, Germany Abstract The first research and development efforts focusing on ferroelectric random access memory (FRAM) were started more than 60 years ago.

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