event guide event guide

ICC, Dresden, Germany Event 24–28 March Exhibition 25–27 March Design, Automation & Test in Europe

The European System Design Show From Systems-on-Chip to Embedded Computing

www.date-conference.com www.date-conference.com . Sponsors . sponsors . Welcome to Date 14 . welcome to DATE 14

Contents

Media Partners 2 At A Glance Timetable 4 Conference Highlights 10-14 Exhibition Theatre Programme 15 EDAA ​EDAC IEEE Council on EDA Social Networking 18 Venue Plan 19 Exhibition Floor Plan 20 Exhibitor List 21 Exhibitor Company Profiles 22

ECSI ACM-SIGDA RAS Welcome to DATE 14 On behalf of the whole Organising Committee, we thank you very much for visiting DATE 2014 and are happy to welcoming you in the beautiful city of Dresden, Germany! This event guide provides all relevant information concerning the DATE 2014 accompanying exhibition,­ a programme outline as well as venue and floor plans for your orientation. Technical co-sponsors: IEEE Computer Society Test Technology Technical Council (TTTC) All participating exhibitors are listed with contact details and information about their products and IEEE Solid-State Circuits Society (SSCS) services being presented at the conference. The company profiles will assist you in finding the right International Federation for Information Processing (IFIP) solution and/or person to contact.

The Exhibition Visit is free of charge. Sponsors event sponsor Sponsorcommercials sponsors DATE 2014 Event Secretariat Exhibition visitors have free access to the exhibition c/o K.I.T. Group GmbH Dresden Muenzgasse 2 area, the opening keynote lectures and the Exhibition 01067 Dresden, Germany Theatre Programme. Phone: +49 351 4967 541 Fax: +49 351 4956 116 Email: [email protected] OPENING PLENARY KEYNOTES: Exhibition Manager: Tuesday, March 25, 2014, 0830 – 1030, Grosser Saal, Saal Level Franziska Kremling K.I.T. Group GmbH, DE Exhibition Opening Times: Phone: +49 351 4967 541 Tuesday, March 25 1000 – 1830* Registration & Accommodation Wednesday, March 26 1000 – 1800 Eva Schubert Thursday, March 27 1000 – 1700 K.I.T. Group GmbH, DE Phone: +49 351 4967 312 *Exhibition Reception from 1830 to 1930 in the exhibition area on the Terrace Level www.date-conference.com

DATE 14 Event Guide DATE 14 Event Guide 1 . Media Partners . media partners . Media Partners . media partners

The DATE organisation and sponsors would like to extend their warmest gratitude to all press journalists who give DATE coverage in the editorial pages. Listed below are the media houses and publications who generously agree to media partnership with DATE, and whose publications can be found on-site near the Press Lounge on the Conference Level.

3D InCites EDA Confidential Engineering & Technology Magazine – Micronews Media, powered by Yole Développement Published by The IET First launched in 2009, 3D InCites is a community EDA is a commercial-free publication providing a quiet Founded in 1998, Yole Développement has grown to platform that is the only online resource devoted place for conversation about the Electronic Design Engineering & Technology is packed with articles on the become a group of companies providing marketing, exclusively to 2.5D and 3D integration technologies. 3D Automation industry and its companion technologies. latest technology covering the areas of communications, technology and strategy consulting, media in addition InCites is a resource for industry news, technology The coverage does not intend to be comprehensive, but control, consumer technology, electronics, IT, to corporate finance services. With a strong focus on innovation, market analysis and opinion. As such, it does intend to provide some food for thought. To that manufacturing & power engineering. It is Europe’s emerging applications using silicon and/or micro provides a place to learn, share, engage and collaborate end, EDA Confidential includes “Recipes”, Freddy largest circulation engineering magazine, published manufacturing, Yole Développement group has with fellow 2.5D and 3D enthusiasts. For 3D IC Santamaria’s “Gourmet Corner”, as well as “Voices” of monthly & offers a global circulation of over 140,000 expanded to include more than 50 associates worldwide integration to happen requires open collaboration other contributing authors, “Off the Record” op-ed copies to more than 100 countries & a high pass-on covering MEMS, Compound Semiconductors, LED, Image across the supply chain. Therefore, 3D InCites strives to pieces, and “Conference” coverage. readership. Sensors, Optoelectronics, Microfluidics & Medical, inform key decision makers about progress in technology Each member of the Institution of Engineering & Photovoltaics, Advanced Packaging, Manufacturing, ok development, design, standards, and infrastructure in www.aycinena.com Technology (IET) receives a copy as part of their Nanomaterials and Power Electronics. The group order to realize commercial production of 2.5D and 3D membership package. Readers include design & supports industrial companies, investors and R&D technologies. 3D InCites has grown to a registered development engineers, system designers & integrators, organizations worldwide to help them understand membership of over 1300 with many additional visitors solutions providers & installers, engineering markets and follow technology trends to develop their who stop by just to keep up with what’s happening in the distributors, consultants, planners, facilities managers business. world of 3D. & end-users. With its HQ in London & regional offices in Europe, North MEDIA & EVENTS ACTIVITY www.3DinCites.com America & Asia-Pacific, the Institution of Engineering & • i-Micronews.com, online disruptive technologies Technology provides a global knowledge network to website facilitate the exchange of ideas & promote the positive • Weekly WebTalk role of technology around the World. The Institution of • @Micronews, weekly e-newsletter Electrical Engineers, dating from 1889, became the • Technology Magazines dedicated to MEMS, Advanced Institution of Engineering & Technology in 2006. It now Packaging, LED and Power Electronics organises more than 120 conferences & other events • Communication & webcasts services each year whilst providing professional advice & • Events: Yole Seminars, Market Briefings briefings to industry, education & governments. www.i-Micronews.com Chip Design Magazine Elektronik i Norden www.eandtmagazine.com Chip Design covers all of the technical challenges and Elektronik i Norden, an important tool for the Nordic implementation options engineers face in the electronic industry. We want Elektronik i Norden to be development and manufacture of today’s complex the most important source of information for the Nordic integrated circuits. Chip Design is the only media electronic industry (Sweden, Finland, Norway and network dedicated to the advanced IC Design market. Denmark). A circulation of 25 800 personally addressed Visit www.chipdesignmag.com to stay informed about copies proves we are the major electronics paper in this the latest developments in chip modeling, architecture, area. We publish news, comments and in-depth technical design, test and manufacture, from EDA tools to digital articles. and analog hardware issues. The System Level Design and Low Power Engineering Portals offer focused www.elinor.se editorial content you won’t want to miss. And, be sure to visit www.eecatalog.com for valuable information about all of Extension Media’s outstanding technology resources.

www.chipdesignmag.com

2 DATE 14 Event Guide DATE 14 Event Guide 3 . Monday 24 March . monday 24 march . Tuesday 25 March . tuesday 25 march

0730 Tutorial Registration and Welcome Refreshments 0730 REGISTRATION, Terrace Level, AND SPEAKER’S BREAKFAST, Saal 2

0830– Breaks 1100 – 1130 Morning Coffee Break, 1600 – 1630 Afternoon Coffee Break 1.1 Opening Plenary, DATE Awards Ceremony and Keynote Addresses, Grosser Saal 1030

Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 6 Konferenz 5 1030 – Exhibition and Coffee Break M01 M02 M03 M04 M05 M06 1130 Development of Software Debug on Automatic fixed-point Dynamic Heteroge- Wireless NoC as Testing of TSV-Based mixed-criticality ARM Processors in conversion: a gate neous Architectures Interconnection 2.5D- and 3D-Stacked Executive Special Exhibition A-Track D-Track D-Track E-Track T-Track systems based on Emulation way to high-level to Address The Backbone for Multi- ICs Sessions Sessions Theatre 0930 – system partitioning power optimization Efficiency Crisis! core Chips: Promises, 1300 Challenges, and Re- Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre cent Developments 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 EXECUTIVE Panel: Making Modern Low-Power Real-Time Yield and Hot Topic: SESSION: Emerging vs. automotive Challenges in and Efficient memory Reliability Technology How to Handle Established systems Analog and Architectures hierarchies for Robust Transfer 1130 – Today’s Design Technologies: safer and Mixed-Signal Systems towards­ 1300 1300 – Complexity a Two more energy Design Horizon 2020 Lunch Break 1430 Sphinxes‘ efficient Riddle at the Crossroads? 1330 Conference Registration begins

Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 6 Konferenz 5 1300 – Lunch Break M07 M08 M09 M10 M11 M12 1430 L4/Fiasco.OC - A Microfluidic Energy-Efficient Sys- A Cyber-Physical Post-Silicon Vali- All You Need to Know Microkernel OS Biochips: A Vision tem Design Through Approach to Mode- dation and Debug: About Hardware Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre Designed for Secu- for More than Moore Error-Resilient ling, Simulation and Best Practices and Trojans and Counter- 1430 – 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 rity, Real-Time and and Biochemistry- Computing Verification of Smart Disruptive Innovation feit ICs 1800 EXECUTIVE Panel: The Secure Modeling and Robust Cyber Physical On line Hot Topic: Reliability on-Chip Systems SESSION: World Is Hardware Optimization Architectures Systems: Strategies for Mission Profile Advanced Going... Analog Primitives and of Power Security and Reliability Aware Design 1430 – Technology & Mixed- Implemen­ ­ Distribution Co-design – The Solution 1600 Challenges & Signal! What tations Networks for Successful Opportunities about EDA? Design of Tomorrows 1800– Automotive Welcome Reception, Saal 1 1900 Electronics

1600 – Coffee Break co-sponsored by ELSEVIER 1700

1600 – IP1 INTERACTIVE PRESENTATIONS AND BEST IP AWARD, Conference Level, Foyer 1630

Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 EXECUTIVE Hot Topic: Secure Device ”Almost there“ Memory Code Dependable State-of-the-art SESSION: Multicore Identification emerging System Generation and System Design in Verification: Addressing Systems in technologies Architectures Optimization European Tertulia 1700 – IC Design - Challenges of Safety Critical for Embedded 1830 Enabling AMS Reliable Chips Electronic Platforms Structured Control Units Verification / for Automotive Verification in and Avionics FPGA & IP design flows

1830 – EXHIBITION RECEPTION 1930

Executive Session Plenary Session Conference March 9 – 13, 2015 D-Track A-Track T-Track E-Track Exhibition March 10 – 12, 2015 Special Session IP Session Exhibition Theatre Session Grenoble, France

4 DATE 14 Event Guide DATE 14 Event Guide 5 . Wednesday 26 March . wednesday 26 march . Thursday 27 March . thursday 27 march

0730 REGISTRATION, Terrace Level, AND SPEAKER’S BREAKFAST, Saal 2 0730 REGISTRATION, Terrace Level, AND SPEAKER’S BREAKFAST, Saal 2

Special Exhibition Exhibition Special Day A-Track D-Track D-Track E-Track T-Track Special Day D-Track a-Track D-Track D-Track E-Track D-Track Sessions Theatre Theatre

Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 SPECIAL DAY Hot Topic: Reliable Prediction and Boosting the Emerging logic Test Embedded SPECIAL DAY Low-Cost, Hardware Timing Hot Topic: Schedulability Timing Analysis Embedded Hot Topic: Hacking and Systems in optimization Scalability technologies generation and Tutorial: Hot Topic: High- Implemen­ challenges in Connecting analysis and Cell Design Tutorial: 0830 – 0830– Different Worlds 1000 Predictable Protecting the Age of of timing of Formal optimization System 1000 CMOS Performance tations for Data validation Memcom­ Multi-Core Hardware: Variability variations Verification Integration – scaling - from NoCs Security – Technology puting: the Abstraction for Computing Threats and Technologies The Bridge evolutionary to Cape of Good Reliability-Aware Challenges between More revolutionary Design and Test Hope than Moore computing

1000 – 1000 – Exhibition and Coffee Break Exhibition and Coffee Break 1100 1100

1000 – 1000 – IP2 Interactive Presentations, Conference Level, Foyer IP4 Interactive Presentations, Conference Level, Foyer 1030 1030

Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 SPECIAL DAY Embedded Management Power delivery Beyond EDA: Model-Based Hardening First Time SPECIAL DAY Wireless NoCs Green System-level Analysis of Multi- Advances in EDA+3D+ Hot Topic: Tutorial: of Micro/ and distribution Extending the Design and Approaches Right in Hot Topic: Computing evaluation Components processor and Synthesis MEMS 1100 – The fight Emerging Macro Application Hardware/ at Different Analog Design 1100 – Memories Systems and Systems distributed Innovation 1230 against Dark Transistor Renewable Domain Software Design Levels Enabling New 1230 today and systems Agenda 2020 Silicon Technologies: Energy Storage of Formal Interfaces Business tomorrow Fueling the From Systems Methods Cases Innovation Devices to Chain of Architectures Electronics

1230 – 1230 – Lunch Break Lunch Break 1400 1400

1330 – 1330 – 7.0 Special Day Keynote, Saal 1 11.0 Special Day Keynote, Saal 1 1400 1400

Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 SPECIAL DAY Embedded Low power Runtime Emerging Performance Design-for- FD-SOI – the SPECIAL DAY Transitioning Industry Enabling Memory System-Level Power and Embedded Panel: Tutorial: methods and memory memory and timing Test and Test Enabling European Embedded NoC Design relevant validation on Resource Thermal Emerging Tutorial: Technology for 1430 – HW/SW Co- Cross Layer multicore optimization technologies analysis Access 1400 – Tutorial: Techniques research and fast platforms Allocation and Estimation and Technologies in GPGPUs: how 1600 Energy Efficient 1530 Development Resiliency in architectures and GPU/ Solutions – Crea- Alternatives to to Future practice for Scheduling in Management Reconfigurable to combine high - The Industrial Real World for mobile manycore ting a Solution CMOS Challenges system design MPSoC Computing computational Workflow health architectures Hive & Design Hub power with high applications as Eco-System for reliability Future Success

1600 – 1530 – Coffee Break Coffee Break 1700 1600

1600 – 1530 – IP3 INTERACTIVE PRESENTATIONS AND BEST IP AWARD, Conference Level, Foyer IP5 INTERACTIVE PRESENTATIONS AND BEST IP AWARD, Conference Level, Foyer 1630 1600

Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre Saal 1 Konferenz 6 Konferenz 1 Konferenz 2 Konferenz 3 Konferenz 4 Konferenz 5 Exhibition Theatre 8.1 SPECIAL 8.2 Hot Topic: 8.3 8.4 8.5 8.6 8.7 8.8 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 DAY: Near Threshold Physical Efficient Modeling & Mapping and Performance Hot Topic: SPECIAL DAY Hot topic: Multimedia Physical System-level Error Built-in Panel: 1700 – System Computing Attacks and Designs for Specification Scheduling Modeling and Beyond 1600 – Hot Topic: How Secure Systems Aspects Design Space Resilience self-test Future SoC 1830 Simulation (NTC) counter­ Telecom and for Many-Core Delay Test CMOS Ultra- 1730 The future of are PUFs Exploration and Power solutions for verification and Virtual measures Financial Embedded low-power interfacing to Really? On the Management mixed-signal methodology: Prototyping Applications Systems Computing the natural Reach and and RF ICs UVM evolution world Limits of Recent or revolution? PUF Attacks

1930 – DATE Party co-sponsored by the City of Dresden 2300

Special Day 1 Special Session IP Session Exhibition Theatre Session D-Track A-Track T-Track E-Track Special Day 2 Special Session IP Session Exhibition Theatre Session D-Track A-Track T-Track E-Track

6 DATE 14 Event Guide DATE 14 Event Guide 7 . Friday 28 March . friday 28 march SAN FRANCISCO, CA • JUNE 1 - 5, 2014 • DAC.COM 0730 Workshop Registration and Welcome Refreshments DESIGN AUTOMATION CONFERENCE

Breaks Please see individual workshop programmes for lunch and break times

0830-1700 Konferenz 1 0830-1700 Konferenz 2 0830-1700 Konferenz 3 0830-1700 Konferenz 4

W1 W2 W3 W4 International Workshop on Depen- ES4CPS - Engineering Simulations Electronic System-Level Design Workshop on Design Automation for dable GPU Computing for Cyber-Physical Systems towards Heterogeneous Computing Understanding Hardware Designs REGISTRATION OPENS: MARCH 27 Where IC Design and the EDA ecosystem DAC learns, networks, and conducts business

0815-1630 Konferenz 5 0830-1630 Konferenz 6 0830-1700 Seminar 5+6 0830-1700 Seminar 3+4

W5 W6 W7 W8 3D Integration: Applications, MEDIAN - Workshop on Manufac- Memristor Science & Technology 3PMCES – Performance, Power DAC DELIVERS: Technology, Architecture, Design, turable and Dependable Multicore and Predictability of Many-Core • A world-class technical program on EDA, Automotive Systems and Automation, and Test Architectures at Nanoscale Embedded Systems Software, Security, IP, Embedded Systems and Software Sponsored By: • Designer Track presentations by and for users • Colocated Conferences, Tutorials and Workshops • Over 175+ Exhibitors including: The New Automotive Village • The ARM Connected Community® (CC) Pavilion • Daily Networking Events INTERACTIVE PRESENTATIONS • Thursday Training Day Sponsored By: Interactive presentations allow presenters to interactively discuss novel ideas and work in progress that may require additional research work and discussion, with other researchers working in the same area. NEW TRACKS FOR 2014: Interested attendees can walk around freely and talk to any author they want in a vivid face-to-face AUTOMOTIVE SYSTEMS & SOFTWARE - IP - SECURITY format. The author may illustrate his work with a slide show on a laptop computer, a demonstration, etc. IP presentations will also be accompanied by a poster. Each IP will additionally be introduced in a relevant regular session prior to the IP Session in a one-minute presentation. KEY ANNOUNCING 2014 KEYNOTES

To give an overview, there will be one central projection displaying a list of all the presentations James Ernie Dr. Cliff Hou Raj Talluri Jim Tung Sir Hossein Buczkowski Brickell Vice President, Senior Vice MathWorks Yassaie going on at the same time in the IP area. Interactive Presentation (IP) Sessions will be held on the Henry Ford Chief Research and President Fellow CEO and Technical Security Development of Product MathWorks, President Fellow Architect TSMC Management Inc. Imagination Conference Level of the congress centre in 30-minute time slots on the following days: Ford Motor Intel Corp. Qualcomm Technologies Company IP Session 1, Tuesday, March 25, 2014 Conference Level, Foyer 1600 – 1630 IP Session 2, Wednesday, March 26, 2014 Conference Level, Foyer 1000 – 1030 IP Session 3, Wednesday, March 26, 2014 Conference Level, Foyer 1600 – 1630 IP Session 4, Thursday, March 27, 2014 Conference Level, Foyer 1000 – 1030 IP Session 5, Thursday, March 27, 2014 Conference Level, Foyer 1530 – 1600 WWW.DAC.COM

After the last IP Session of each day, the “Best IP of the Day” will be awarded.

in technical sponsored by: cooperation with: #51DAC 8 DATE 14 Event Guide DATE 14 Event Guide 9 . Plenary Session . plenary session . Special Day . special day keynote addresses Tuesday, March 25, 2014, 0830 – 1030, Grosser Saal Opening Plenary, DATE Awards Ceremony and Keynote Addresses . keynote address . first keynote address . keynote address . wednesday keynote address Tuesday, March 25, 2014, 0910 Wednesday, March 26, 2014, 1330 – 1400, Saal 1 System design challenges­ for next generation The connected car and its implication to the 1.1.1 wireless and embedded Systems 7.0 automotive chip roadmap David Fuller, National Instruments, US Michael Bolle, Robert Bosch GmbH, DE

Application demands in our embedded world are growing real-world sensor data. As the systems grow in complexity, The automotive industry is in a radical change process video, ultrasound sensors and usage of state of the art dramatically. Consumer expectations and the industry’s new design approaches must also be developed and driven by technology. On the one hand side the CPU and GPU processor architectures. In our talk we forward-looking technology roadmaps paint a picture of a employed to expedite the research, design, and proliferation of communication technologies into the will address both developments and outline foreseen connected world full of intelligent devices once thought development cycle. David Fuller will outline challenges car leads to internet connected vehicles. The vehicle future applications as future driving assistant and to have fixed functionalities. Researchers exploring next system designers face in developing cyber-physical will become an integral part of the internet – opening infotainment systems as well as highly automated generation wireless systems, Internet of Things (IOT), systems and explore a graphical system design approach new processing paradigms for the car itself. On the driving. We will discuss major requirements for the and even machine-to-machine (M2M) communications that includes hardware abstraction and comprehends a other hand the vehicle itself significantly expands its future electrical architectures and implications for face many challenges in making this vision a reality. heterogeneous multiprocessing environment while sensor and processing capabilities by the use of radar, future automotive chips. Where once a single, isolated design flow addressed the embracing different models of computation. Through this discrete application, heterogeneous multi-processing new approach, system designers can shorten design architectures must be considered and embraced along cycles and the time to prototype ultimately accelerating with the connections to other devices and systems, and deployment. . keynote address . second keynote address . keynote address . thursday keynote address Tuesday, March 25, 2014, 0950 Thursday, March 27, 2014, 1330 – 1400, Saal 1 The growing importance of microelectronics Organic electronics – from lab to markets 1.1.2 11.0 from a foundry perspective Karl Leo, Technische Universität Dresden, DE Gerd Teepe, GLOBALFOUNDRIES, DE

Microelectronics is the dominant industrial technology technological complexity is transferred to the design Organic semiconductors with conjugated electron During this talk, I will discuss some of the recent of today. Its rate of innovation, spelled out by Moore’s space at an accelerated pace - The SOC is dominating system are currently intensively investigated for progress in realizing devices, in particular highly Law, is exceptional by any commercial metric, the design space - Intelligent Things are emerging with optoelectronic applications. This interest is spurred by efficient white OLED for lighting and flexible organic especially, as it has been on this trajectory for almost unprecedented cognitive and motion capabilities - The novel devices such as organic light-emitting diodes solar cells. 40 years. It is not surprising, that other industrial supply chain transformation is in full motion, with the (OLED), organic solar cells, and flexible electronics. sectors are taking advantage of the innovation engine foundry model at the forefront With these powerful of the semiconductors for its own product innovation: trends in motion, we will have to rethink our approach Cars are safer and more economic, medical diagnostics towards semiconductors as part of the industrial are performing to a significantly higher level, and system. It will not be sufficient any more to “enhance” energy efficiency from the generation to the consumer traditional products like Cars, TVs, machines or phones is a lot more efficient. “The Internet” has become the with semiconductor content to make them perform at a basis for our communication, organization and planning higher level to increase its value to consumers. We need in our economies with significant impact to our society. to rethink the connected world around us to truly assess However, the Semiconductor industry is under a the next generation of intelligent applications, which powerful transformation marked by the following we are about to enter. trends: - Design Complexity is facing new challenges, as

10 DATE 14 Event Guide DATE 14 Event Guide 11 . Tuesday 25 March . tuesday 25 march . Wednesday 26 March . wednesday 26 march Executive Sessions Special Day: System-Level Design

Organiser: Yervant Zorian, Synopsys, US Organisers and Co-Chairs: Jürgen Teich, University of Erlangen-Nuremberg, DE Johannes Stahl, Synopsys, US DATE 2014 will again feature an Executive Track of presentations All three executive sessions will first provide each executive by leading company executives representing a range of semicon- with a time-slot to present his/her vision, followed by a ques- The special day System-Level Design will reflect current indus- different input languages as well as software code generation ductor manufacturers, EDA vendors, fables houses and IP pro- tion and answer period to provide interaction with the attend- trial practices as well as present recent advances in this techniques. Important topics also include multicore enable- viders. This one-day program will be held on Tuesday 25 March, ees. The Executive Track should offer prospective attendees research area. A particular emphasis will be on ultra-low power ment for safety-critical and real-time embedded systems as well the first day of the DATE conference immediately after the Open- valuable information about the vision and roadmaps of their design and modeling at multiple abstraction levels, virtu­al as accelerator-rich design for the fight against dark silicon. ing Session and it will be comprised of three sessions where the corresponding companies from a business and technology platforms for software development and architecture design of executives will present their technical/business vision in this point-of-view. MPSoCs. We will also take a look at high-level synthesis from nanometer technology era. Each session will feature 3-4 execu- tives and run in parallel to the technical conference­ tracks. 5.1 Hot Topic: Predictable Multi-Core Computing Saal 1 0830 – 1000 2.1 EXECUTIVE SESSION: How to Handle Today’s Design Complexity Saal 1 1130 – 1300 Organiser: Jürgen Teich, University of Erlangen-Nuremberg, DE Organiser: Yervant Zorian, Synopsys, US Chair: Petru Eles, Linkoping University, SE Executives: Sanjive Agarwala, Texas Instruments, US Co-Chair: Jürgen Teich, University of Erlangen-Nuremberg, DE Paul Lo, Synopsys, US The requirement of high performance computing at low power tions on multi-core platforms by presenting results of the Rainer Kress, Infineon, DE can be met by the parallel execution of an application on a pos- impact of resource sharing on performance, an architecture Leon Stock, IBM, US sibly large number of programmable cores. However, the lack of that has been designed to meet predictability requirements as accurate timing properties may prevent parallel execution from well as new results on scheduling mixed critical applications on Sanjiv Taneja, Cadence, US being applicable to time-critical applications. This session multi-core platforms. treats this important problem of time predictability of applica- The widening gap between growing SOC complexity and aspects of complex SOC design. Executives in this session will designer productivity limits traditional chip design methods discuss the impact of complexity and the new opportunities it and flows. This results in several new approaches and innovative may bring in designing today’s SOC. methods that work to elevate the limitations of different 6.1 Hot Topic: The fight against Dark Silicon Saal 1 1100 – 1230 Organiser: Jörg Henkel, Karlsruhe Institute of Technology, DE Chair: Jörg Henkel, Karlsruhe ­Institute of Technology, DE EXECUTIVE SESSION: Advanced Technology Challenges & Opportunities Saal 1 1430 – 1600 3.1 Co-Chair: Jürgen Teich, University of Erlangen-Nuremberg, DE Organiser: Yervant Zorian, Synopsys, US Executives: giorgio Cesana, STMicroelectronics, FR Dark Silicon is predicted to dominate the chip footage of This special session gives a snapshot of current research activi- Joachim Kunkel, Synopsys, US upcoming many-core systems within a decade since Dennard ties of this grand challenge. In particular, the three talks pre- Scaling fails mainly due to the voltage-scaling problem that sent the newest trends and developments starting with the Rudy Lauwereins, IMEC, BE results in higher power densities. It would deem upcoming problem of Dennard Scaling and how it mandates new design Maria Merced, TSMC, NL technologies nodes inefficient since a majority of cores would constraints followed by the problem of power delivery and cool- Gerd Teepe, GLOBALFOUNDRIES, DE lie fallow. Significant research efforts have started within the ing, and concluding with the newest directions in efficient last couple of years to investigate and mitigate Dark Silicon resource management for many-core systems. The continuous technology scaling and their new applications them. The executives in this session will discuss upcoming effects to ensure an effective use of available chip footage. are dramatically impacting the semiconductor industry. This innovations in the semiconductor industry and their impact on may also significantly affect the dependency between eco-sys- the solutions offered by the eco system players. tem players necessitating smooth interdependency between 7.0 The connected car and its implication to the automotive chip roadmap Saal 1 1330 – 1400 Michael Bolle, Robert Bosch GmbH, DE  See page 11 4.1 EXECUTIVE SESSION: Addressing Challenges of Reliable Chips Saal 1 1700 – 1830 Organiser: Yervant Zorian, Synopsys, US Panel: HW/SW Co-Development – The Industrial Workflow Saal 1 1430 – 1600 Executive: dan Alexandrescu, iROC Technologies, FR 7.1 Robert Aitken, ARM, US Organiser: Johannes Stahl, Synopsys, US Robert Hum, Mentor Graphics, US Chair: iris Stroh, Markt & Technik, DE Ronald Martino, Freescale, US This panel brings together the entire supply chain for the use of panelists will discuss what are the benefits and challenges of virtual prototyping starting with the end users at an automo- accelerating software development using virtual prototy­ping While today’s SOCs systematically use semiconductor produc- such requirements. The speakers in this executive session will tive Tier1, a semiconductor supplier, IP providers and the vir- are for deployment in industrial projects. tion quality assessment and optimization solutions, meeting address the current trends and challenges in the semiconductor tual prototyping and software development tool providers. The end-product requirements for reliability and availability aug- reliability and discuss the level of readiness needed in a chip to ments the need to prepare the SOC design in advance to address meet today’s SOC requirements. 8.1 System Simulation and Virtual Prototyping Saal 1 1700 – 1830 Organiser: Johannes Stahl, Synopsys, US Chair: Johannes Stahl, Synopsys, US

In this session we will review several practical applications of ences in using the virtual prototyping methodology and cur- virtual prototyping for architecture design work and software rent commercial tools. development across different markets such as mobile, industrial and automotive. The authors will share their practical experi-

12 DATE 14 Event Guide DATE 14 Event Guide 13 . Thursday 27 March . thursday 27 march . Exhibition Theatre . exhibition theatre Special Day: Advancing Electronics beyond CMOS Organiser: Juergen Haase, edacentrum, DE Organisers and Co-Chairs: ian O’Connor, Lyon Institute of Nanotechnology, FR In addition to the conference programme during DATE 14, there design event. The theatre is located in the exhibition area on Thomas Mikolajick, Namlab (cfAED), DE will be a presentation theatre from Tuesday, 25 March, to Thurs- the Terrace Level and affords easy access for exhibition visitors As the issues associated with CMOS scaling become harder and switching devices and computing nanofabrics, trends in day, 27 March, 2014. Attendees will profit from having an indus- as well as for conference delegates. more costly to solve, the special day Advancing Electronics ­memory technologies in hybrid 3D integration, flexible and try forum in the midst of Europe’s leading electronic systems beyond CMOS will cover the latest trends towards alternative organic electronics, new state variable vectors (spintronics, devices and paradigms for computing and data acquisition, photonics) and interfaces to the natural world (sensor net- storage and transport. Important topics include nanoscale works, data analysis, displays, MEMS). 2.8 SPECIAL SESSION Hot Topic: Technology Transfer towards Horizon 2020 Tuesday, March 25, 2014, 1130 – 1300 Hot Topic: CMOS scaling - from evolutionary to revolutionary computing 9.1 Organiser: rainer Leupers, RWTH Aachen, DE Saal 1 0830 – 1000 Chair: norbert Wehn, TU Kaiserslautern, DE Organisers: thomas Mikolajick, NamLab gGmbH, DE, Ian O’Connor, Lyon Institute of Nanotechnology, FR Chair: thomas Mikolajick, NamLab gGmbH, DE European research projects produce many excellent results, and research community is currently investigating novel ways of Co-Chair: ian O’Connor, Lyon Institute of Nanotechnology, FR the quality of research papers at DATE and other major European stimulating additional academia-industry technology transfer. conferences is often outstanding. But how many academic This special session contributes by discussing concrete transfer Transistors as switches have now scaled down to a point where looks at how the use of switches with controllable polarity, research results in computing technologies and EDA actually experiences and new concepts. Furthermore it will exemplify the classical bulk structure is no longer tenable and it is neces- such as in silicon nanowire devices, can improve the energy effi- make it into industrial practice? In the context of the transi- several success stories from both academic and industrial pers­ sary to change the nature of the channel structure. In this ses- ciency of systems on chip. The devices themselves are explored tion into the Horizon 2020 framework program, the European pectives. sion, the three principal contenders for following on from con- in detail in the third paper, with the concept of fine-grain ventional devices will be examined. The first paper looks at the reconfigurability at the fore. The fourth and final paper gives a use of III-V nanowires, with expected benefits in terms of speed reality check on carbon electronics and the most promising 3.8 SPECIAL SESSION and energy, as well as integration challenges. The second paper devices in this class. Hot Topic: Mission Profile Aware Design – The Solution for Successful Design of Tomorrows 10.1 Hot Topic: Memories today and tomorrow Saal 1 1100 – 1230 Automotive Electronics Tuesday, March 25, 2014, 1430 – 1600 Organisers: thomas Mikolajick, NamLab gGmbH, DE, Ian O’Connor, Lyon Institute of Nanotechnology, FR Organisers: goeran Jerke, Robert Bosch GmbH, DE Chair: ian O’Connor, Lyon Institute of Nanotechnology, FR Oliver Bringmann, University of Tuebingen, DE Co-Chair: thomas Mikolajick, NamLab gGmbH, DE Chair: goeran Jerke, Robert Bosch GmbH, DE Co-Chair: oliver Bringmann, University of Tuebingen, DE Memory devices and technologies have undergone huge transfor- paper examines phase change memories, while magnetic memo- mations in recent years and many industrially viable replacements ries are discussed in the third paper, both in terms of standard In order to benefit from modern automotive semiconductor are formalized in so-called “mission profiles”. We introduce the to conventional technologies are on the brink of entering the mar- memory applications but also in terms of how they can improve technologies, application robustness must now be considered motivation to use mission profiles from an OEM and Tier n pers­ ket. The first paper in this session gives an overview of alternative logic performance. Resistive memories are the topic of the fourth as a design target. This includes the consequent consideration pective. Additionally, we introduce the mission profile aware memory technologies and how each can contribute or disrupt paper, where new applications are considered – in FPGAs, NoCs of environmental stress conditions and functional loads, which design flow and present several application scenarios. accepted memory hierarchies. The quest for a universal memory and crossbars. The fifth paper in this session looks at low-cost device is still underway, and the other papers in this session focus memory with a printable manufacturing approach, leading to on various approaches for future memory devices. The second other applications and market segments. 4.8 Exhibition Theatre Session 11.0 Organic electronics – from lab to markets Saal 1 1330 – 1400 State-of-the-art in Verification: European Tertulia IC Design – Enabling AMS Structured Karl Leo, Technische Universität Dresden, DE  See page 11 Verification / Verification in FPGA & IP design flows Tuesday, March 25, 2014, 1700 – 1830 11.1 Embedded Tutorial: Alternatives to CMOS Saal 1 1400 – 1530 Details to be announced. Organisers: ian O’Connor, Lyon Institute of Nanotechnology, FR, Thomas Mikolajick, NamLab gGmbH, DE Chair: ian O’Connor, Lyon Institute of Nanotechnology, FR SPECIAL SESSION Co-Chair: thomas Mikolajick, NamLab gGmbH, DE 5.8 System Integration - The Bridge between More than Moore and More Moore Alternative approaches to CMOS-based computing structures architectures. Silicon photonics, with anticipated benefits for abound, for logic, memory, interconnect and interfaces. This interconnect structures, is examined in the second paper. The Wednesday, March 26, 2014, 0830 – 1000 embedded tutorial aims to give in-depth analyses of three third paper looks at the status of organic electronics and the Organiser: manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE promising technologies. The first paper covers spintronics and properties of thin-film transistors for large displays and sensor its use in logic and memory to achieve low-power computing arrays on flexible supports. Kai Hahn, University Siegen, DE Chair: manfred Dietrich, Fraunhofer IIS/EAS Dresden, DE 12.1 Hot Topic: The future of interfacing to the natural world Saal 1 1600 – 1730 Co-Chair: Kai Hahn, University Siegen, DE Organisers: ian O’Connor, Lyon Institute of Nanotechnology, FR, Thomas Mikolajick, NamLab gGmbH, DE System Integration using 3D technology is a very promising way for future applications. This so called “More than Moore” Chair: thomas Mikolajick, NamLab gGmbH, DE to cope with current and future requirements for electronic sys- approach complements the conventional SoC product enginee­ Co-Chair: ian O’Connor, Lyon Institute of Nanotechnology, FR tems. Since the pure shrinking of devices (known as “More ring. This session gives insights in System Integration design Moore”) will come to an end due to physical and economic challenges from different perspectives, ranging from design Challenges for acquiring and processing data from the real ous chemical conditions. Interfaces to living organisms are restrictions, the integration of systems (e.g. by stacking dies, technology over MEMS product engineering and 3D inter­ world includes the development of interfaces capable of examined in the second paper, which discusses challenges and or by adding sensor functions) shows a way to maintain the connect to automotive cyber physical systems. extracting relevant information from massive sensor networks approaches for efficient detection of disease. In the third growth in complexity as well as in diversity which is necessary or from living organisms, sifting through the wealth of data to paper, novel hardware devices and architectures are explored arrive systematically at a meaningful conclusion, and building for use in energy-efficient video analysis applications such as hardware platforms suited to carry out these operations in an movement detection and face recognition. The fourth paper energy-efficient way. The first paper in this session looks at the discusses handling of complex data with large-scale GPU-based necessarily complex processing of chemical information with recurrent networks, exploiting specific features of the data to hardware components that are capable of responding to vari- improve energy efficiency. 14 DATE 14 Event Guide DATE 14 Event Guide 15 . Exhibition Theatre . exhibition theatre . Exhibition Theatre . exhibition theatre

6.8 Exhibition Theatre Session 10.8 Exhibition Theatre Panel First Time Right in Analog Design Enabling New Business Cases EDA+3D+MEMS Innovation Agenda 2020 Fueling the Wednesday, March 26, 2014, 1100 – 1230 Innovation Chain of Electronics Thursday, March 27, 2014, 1100 – 1230 Details to be announced. Organiser: Jürgen Haase, edacentrum, DE Moderator: ahmed Jerraya, CEA-LETI, FR 7.8 Exhibition Theatre Session Panelists: gabriel Kittler, X-FAB, DE FD-SOI – the Enabling European Technology for Energy Efficient Solutions – Brandon Wang, Cadence, US Brent Gregory, Synopsys, US Creating a Solution Hive & Design Hub as Eco-System for Future Success Horst Symanzik, Bosch-Sensortec GmbH, DE Wednesday, March 26, 2014, 1430 – 1600 Gerd Teepe, GLOBALFOUNDRIES, DE Details to be announced. Today the most powerful innovations in the major industries technologies for MEMS and for 3D chips have reached a maturity and the most promising approaches to tackle burning socie­tal level that enables them to reshape our lives until 2020. This SPECIAL SESSION challenges are substantially influenced by and depending from panel will discuss how to utilize these technologies: Which 8.8 the innovations provided by the microelectronics industry. applications will become possible with the upcoming innova- Hot Topic: Beyond CMOS Ultra-low-power Computing Wednesday, March 26, 2014, 1700 – 1830 Breakthroughs in manufacturing technologies enable the reali- tions in 3D and MEMS technologies, what kind of EDA innova- zation of novel types of devices and of systems, which enable tions will be required in order to be able to implement these Organiser: Saibal Mukhopadhyay, Georgia Institute of Technology, US applications with fascinating functionality and enormous per- applications effectiv­ely and efficiently, yielding powerful yet Chair: arijit Raychowdhury, Georgia Institute of Technology, US formance. However, this innovation chain is not operational reliable components and systems. The set-up of the panel Co-Chair: Saibal Mukhopadhyay, Georgia Institute of Technology, US without appropriate innovations in design technology: We need includes the manufacturers GLOBALFOUNDRIES and X-FAB, an innovation Agenda 2020 for design methodology and EDA Bosch as leading supplier of technology and one of the MEMS With conventional CMOS scaling becoming increasingly challen­ Spintronics, and nano-electro-mechanical switches (NEMS) – tools fueling the innovation chain of electronics. 2014 the pioneers as well as leading EDA vendors Cadence and Synopsys. ging, the designers wonder what opportunities and challenges for low-power electronics. The talks will discuss the need for exist beyond-CMOS for both Boolean and non-Boolean compu­ innovating and evaluating new circuit and system design meth- ting. This session will discuss three very different and promi­ ods as new device technologies emerge. 11.8 SPECIAL SESSION sing emerging technologies – Tunneling Field-Effect Transistor, Embedded Tutorial: GPGPUs: how to combine high computational power with high reliability Thursday, March 27, 1400 – 1530 9.8 SPECIAL SESSION Organiser: matteo Sonza Reorda, Politecnico di Torino, IT Embedded Tutorial: Memcomputing: the Cape of Good Hope Thursday, March 27, 0830 – 1000 Chair: dimitris Gizopoulos, University of Athens, GR Organisers: Yiyu Shi, Missouri University of Science & Technology, US Co-Chair: rob Aitken, ARM, US Hung-Ming Chen, National Chiao Tung University, TW The embedded tutorial aims at providing with an updated view and power, but also in terms of reliability, and how the latter Chair: tsung-Yi Ho, CSIE, NCKU, TW on what GPGPUs can provide not only in terms of performance can be evaluated and possibly improved. Co-Chair: hung-Ming Chen, National Chiao Tung University, TW Energy efficiency has emerged as a major barrier to performance sor-memory traffic. Moreover, memory computing brings the SPECIAL SESSION scalability for modern processors. On the other hand, signifi- computing engine close to the data, thus drastically minimi­ 12.8 cant breakthroughs have been achieved in memory technolo- zing the von Neumann bottleneck. Finally, it exploits the Panel: Future SoC verification methodology: gies recently. As such, the fascinating idea of memcomputing advances in memory technologies and integration approaches (i.e., use memory for computation purposes) has drawn wide (e.g. 3D integration) to achieve better technology scalability. UVM evolution or revolution? Thursday, March 27, 1600 – 1730 attention from both academia and industry as an effective This special session offers a broad-spectrum retreat (devices, Organiser: alex Goryachev, IBM Research, Haifa, IL remedy.­ Compared with conventional logic computing, memory processes and systems) on this hot topic to the general CAD array provides large set of parallel resources with high band- community, hoping to inspire more contributions from the Chair: rolf Drechsler, University of Bremen/DFKI, DE width, which can be configured to perform computing in spa- design automation perspective. tial/temporal manner leading to dramatic reduction in proces- It is a recent trend that SoCs are becoming more similar to serv- ment, set of tools, and teams. It looks at the system as a whole ers. Many SoCs today are no longer tied to a single application and is not based on reusing lower level environments. and look more like general purpose PCs and high-end servers. Smartphones are the most notable example of this, but we are Formal methods are a field of intensive research, but they have also seeing this with TV chips, in-car controllers, network rout- not been adopted by the industry for SoC-level verification. ers, and more. This trend is occurring in parallel to the con- stantly growing complexity of SoCs, which support diverse IO In this panel leading experts from industry (both users and ven- interfaces and devices, and have complex architectures includ- dors) and academy will discuss the future of SoC verification ing multiple heterogeneous cores, multi-level caches, and mul- methodology. Is the gap in today’s SoC verification methodol- tiple IO bridges. ogy significant? Is it growing? Or perhaps it does not exist? What is the right way to close the gap, if one exists? Is it suffi- Today, common practice for verification is based on Universal cient to extend UVM capabilities (e.g., SystemC, TLM) or are Verification Methodology (UVM), which, at the system level, is dedicated tools and methodology needed? Are formal methods built on reusing and combining unit-level environments, fol- ready to play a significant role in SoC-level verification? In gen- lowed by running real software on an SoC. This metho­dology eral, we would like to determine the importance of system-level leaves a large gap. In high-end systems, this gap is covered by verification and its unique needs—whether generators, check- system-level verification that focuses on HW-only system inte- ing, coverage, or teams. gration. This level has its own methodology, dedicated environ-

16 DATE 14 Event Guide DATE 14 Event Guide 17 . Social Networking . social networking . Venue PLan . venue plan The DATE 2014 Programme Committee has again put emphasis on providing plenty of opportunities for conference delegates to visit the exhibition, get in touch with colleagues and attend the sessions in the exhibition theatre. International Congress Center Dresden (ICCD) A number of specialist interest groups will be holding their meetings at DATE 2014. The following meetings are scheduled at the moment. A complete list of fringe meetings can also be found on the DATE homepage www.date-conference.com.

Day+Time Meeting & Contact Room Conference Level Seminar Level Exhibition Area ACM SIGDA/EDAA PhD Forum Mon 1900-2100 Saal 1 Peter Marwedel, EDAA/ACM SIGDA, DE eTTTC Meeting (European Group of the IEEE Test Technology Technical Council Meeting) Tue 1300-1430 Seminar 3 Giorgio Di Natale, LIRMM, FR EDAA General Assembly Tue 1830-1930 Seminar 2 Georges Gielen, Katholieke Universiteit Leuven, BE IFIP Working Group 10.5 Tue 1830-2000 Seminar 4 Dominique Borrione, IMAG, FR IFIP Working Group 10.2 Tue 1830-2030 Seminar 5 Achim Rettberg, University of Oldenburg, DE DATE Sister-Events Meeting Thu 1230-1400 Seminar 5 Georges Gielen, Katholieke Universiteit Leuven, BE

Coffee & Lunch Breaks The exhibition area on the Terrace Level of the International Congress Centre also hosts the coffee and lunch break area. During the below-mentioned times, coffee and tea will be served during the coffee breaks as well as light snacks during the lunch breaks (for full conference delegates only). Furthermore, there is a cash bar on the Terrace Level for visitors and exhibitors. Restaurant Grosser Saal and Saal 1–5 Main Entrance Terrace Level with registration area Tuesday, March 25, 2014 Coffee Break 1030 – 1130 Lunch Break 1300 – 1430 Coffee Break 1600 – 1700 Wednesday, March 26, 2014 Coffee Break 1000 – 1100 Lunch Break 1230 – 1400 Coffee Break 1600 – 1700 Thursday, March 27, 2014 Coffee Break 1000 – 1100 Lunch Break 1230 – 1400 Coffee Break 1530 – 1600

Exhibition Reception, Tuesday, March 25, 2014 The Exhibition Reception will take place on Tuesday, March 25, 2014, from 1830 – 1930 in the exhibition area (Terrace Level), where free drinks and snacks for all conference delegates and exhibition visitors will be offered. Conference Level DATE Party, Wednesday, March 26, 2014 Session rooms Konferenz 1–6, The DATE Party is again scheduled on the second conference day, Wednesday, March 26, 2014, starting from 1930. This year, it will A/V Office, Press Lounge take place in one of Dresden’s most exciting and modern buildings, the “Gläserne Manufaktur” of the car manufacturer Volkswagen Main Entrance AG (www.glaesernemanufaktur.de/en/). The party will feature a flying buffet style dinner with various catering points and Seminar Level accompanying drinks. Light background music and the possibility of guided visits through the extraordinary premises will round Fringe Meetings off the evening. It provides a perfect opportunity to meet friends and colleagues in a relaxed atmosphere while enjoying local Business Meetings amenities. Please kindly note that it is no seated dinner. Terrace Level All delegates, exhibitors and their guests are encouraged to attend the party. Please be aware that entrance is only possible with Registration area, a party ticket. Each full conference registration includes a ticket for the DATE Party. Additional tickets can be purchased on-site Catering and Exhibition area at the registration desk (subject to availability of tickets). Ticket price for the full Evening Social Programme: 75 € per person. Saal Level Grosser Saal (Opening Plenary) DATE Party Shuttle: There will be an organised shuttle by tram to the DATE Party venue and back for all conference delegates having a Party Ticket. Saal 1 (Sessions) Meeting point: 1845 in front of the main entrance of the International Congress Center Dresden (ICCD). The trams then start at Saal 2 (Speaker’s Breakfast) 1900 from the tram station “Kongresszentrum”. Restaurant The DATE Party is co-sponsored by the City of Dresden.

Interactive Presentations Interactive presentations will take place from Tuesday, March 25, 2014 until Thursday, March 27, 2014 on the Conference Level, Foyer.  See page 8 18 DATE 14 Event Guide DATE 14 Event Guide 19 . Floor Plan . exhibition floor plan . Exhibitor List . exhibitor list

Company Booth Company Booth

3D InCites, LLC K 2 Conference Level Micronews Media, powered by Yole Développement K 1 ALMA - ALgorithm parallelization for Multicore ­Architectures EP 6 MOSIS 20 Terrace Level Blue Pearl Software 24 MultiPARTES EP 1 Center for Advancing Electronics Dresden (cfaed) 4+5 MunEDA GmbH 14 City of Dresden, Office of Economic Development 13 now publishers inc. 27 CLERECO – Cross-Layer Early Reliability Evaluation for the Computing cOntinuum EP 4 OneSpin Solutions GmbH 26 CMP: Circuits Multi-Projects 17 ProPlus Design Solutions, Inc. 9 Conference Level Codasip 7

Concept Engineering GmbH 11 PROXIMA EP 1

CONTREX EP 1 RacyICs GmbH TP 1

room room room room A/V Office CREATIVE CHIPS GmbH 19 Konferenz Konferenz room room Konferenz Konferenz Konferenz (Konferenz 7+8) SFB HAEC (TU Dresden) 6 6 5 Konferenz 4 3 2 1 K 1 Dream Chip Technologies GmbH TP 2 K 2 K 3 SGS INSTITUT FRESENIUS GmbH 13 IP Sessions Poster K 4 DREAMS EP 1 Press Lounge EDA Confidential K 3 Silicon Saxony e.V. 13

EDA Solutions LTD 20 SPRINGER 22+23 Terrace Level Elektronik i Norden K 4 Synflow 8 Elsevier BV 10 Tanner EDA 20 Embedded Computing Specialists 2 7 8 Cash Bar Exhibition TOSHIBA 16 Conference Theatre European Project Cluster on Mixed-Criticality Systems rooms & 9 Registration Area Press Lounge (DREAMS, PROXIMA, CONTREX, MultiPARTES) EP 1 Catering upstairs 17 27 10 Grosser EP 1-6 University Booth 3 Saal + Seminar 11 EUROPRACTICE 1 Saal 1+ rooms Saal 2 downstairs 1 downstairs WIBRATE – Wireless, Self-Powered Vibration Tp1-4 EuroTraining – Training in Nanoelectronics EP 2 24 2 22/23 19 14 Monitoring and Control for Complex

12 4-5 Techno- 3 FlexTiles Consortium EP 5 logy 20 15 Industrial Systems EP 3 Plaza University 26 13 Booth 16 6 Fraunhofer EMFT TP 3 Catering Catering Wirtschaftsförderung Sachsen GmbH (WFS) 13 Catering Fraunhofer Institute for Integrated Circuits IIS 12 Catering X-FAB Group 13 Incentia 20

Methodics 15 Zentrum Mikroelektronik Dresden AG 13 & TP 4

20 DATE 14 Event Guide DATE 14 Event Guide 21 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

booth K 2 applications on multiprocessor platforms with a high booth 4+5 booth 13 level of abstraction. Scilab is an open source, cross- 3D InCites, LLC platform numerical computational package and a high- Center for Advancing Electronics City of Dresden level, numerically oriented programming language. Dresden (cfaed) Office of Economic Development Contact: Françoise von Trapp ALMA will develop a holistic toolset that will enable faster uptake of embedded multicore technologies, 3DInCites faster time to market and reduced development cost Contact: Birgit Holthaus Contact: Michael Kaiser 605 E. Grant Street, Ste. 106 with significant impact on product innovation and TU Dresden City of Dresden Phoenix, AZ 85004 consumer prices. 01062 Dresden Office of Economic Development United States ALMA will define semantics for parallelism that will be Germany Ammonstraße 74 introduced in Scilab and develop an innovative Phone: +1 978 340-0773 01067 Dresden approach for parsing input descriptions with Phone: +49 351 463 42848 Germany Email: [email protected] annotations for parallelism. Algorithms and tools will Fax: +49 351 463 41099 Website: www.3DinCites.com be developed for (a) the estimation of the required Phone: +49 351 4888700 hardware resources to realize the targeted applications Email: [email protected] Fax: +49 351 4888702 Website: www.tu‐dresden.de/cfaed First launched in 2009, 3D InCites is a community within performance constraints, and (b) the identification of potential partitions and schedules of Email: [email protected] platform that is the only online resource devoted The Cluster of Excellence ‘Center for Advancing Website: www.dresden.de/business exclusively to 2.5D and 3D integration technologies. 3D these, using optimization techniques, utilizing the different resources of the underlying architectures. The Electronics Dresden’ (cfaed) of Technische Universität InCites is a resource for industry news, technology Dresden comprises eleven research institutes in Saxony. Network Thinking - Microelectronics in Dresden innovation, market analysis and opinion. As such, it tools allow for an iterative algorithm optimization from a high level of abstraction and will be applied in two Further members are the Technische Universität - Competencies: Research & Development, IC Design, provides a place to learn, share, engage and collaborate Chemnitz, two Max Planck Institutes, two Fraunhofer Photomasks, Chip Manufacturing, Packaging, with fellow 2.5D and 3D enthusiasts. For 3D IC state-of-the-art architectures provided by Recore and KIT. The resulting gain of the ALMA approach is Institutes, two Leibniz Institutes and the Helmholtz- Equipment, Software integration to happen requires open collaboration Research Center Dresden-Rossendorf. About 300 - The Economic Development Office of the City of across the supply chain. Therefore, 3D InCites strives to expected to be twofold: faster design space exploration and faster time to market. scientists are working in nine research paths to Dresden is your contact and partner as enterpreneur or inform key decision makers about progress in technology investigate completely new technologies for electronic investor. Our service ensures that your investment in development, design, standards, and infrastructure in information processing. These technologies are inspired Dresden can be realised without delay. order to realize commercial production of 2.5D and 3D Product Finder by innovative materials such as silicon nanowires, technologies. 3D InCites has grown to a registered Embedded Software Development: carbon nanotubes or polymers or based on completely Welcome to Dresden! membership of over 1300 with many additional visitors Compilers new conceptions such as the chemical chip or circuit who stop by just to keep up with what’s happening in the fabrication methods by self-assembling structures e.g. world of 3D. DNA-Origami. The orchestration of these new devices booth eP 4 into heterogeneous information processing systems with focus on their resilience and energy-efficiency is CLERECO – Cross-Layer Early booth eP 6 booth 24 also part of cfaed’s research program. To complement the Cluster, the Collaborative Research Center (CRC) 912 Reliability Evaluation for the ALMA - ALgorithm parallelization for Blue Pearl Software ‘Highly Adaptive Energy-Efficient Computing’ (HAEC) Computing cOntinuum Multicore Architectures has been integrated in cfaed. Both, cfaed and HAEC, are Contact: Murielle Lacombled coordinated by Prof. Dr.-Ing. Dr. h.c. Gerhard Fettweis, Contact: Stefano Di Carlo who also holds the Vodafone Chair Mobile Contact: Jürgen Becker Blue Pearl Software Politecnico di Torino 4677 Old Ironsides Drive, Suite 390 Communications Systems at TU Dresden. Karlsruhe Institute of Technology (KIT) The Dresden Center for Nanoanalysis (DCN) – an Control and Computer Engineering Department Santa Clara CA 95054 Corso Duca degli Abruzzi 24 Institute for Information Processing Technologies United States interdisciplinary technological platform in the field of Engesserstr. 5 nanoscale materials analysis – is also connected to cfaed. 10129 Torino 76131 Karlsruhe Phone: +33 616 354 892 Italy Germany Email: [email protected] Product Finder Email: [email protected] Email: [email protected] Website: www.bluepearlsoftware.com ASIC and SOC Design: Website: www.clereco.eu Website: www.alma-project.eu Design Entry Blue Pearl Software automates IP and FPGA verification Behavioural Modelling & Simulation Advanced multifunctional computing systems realized Not only traditional PCs but also novel chips in before debug. From an HDL description, designers run Power & Optimisation in forthcoming technologies hold the promise of a consumer electronics like PDAs or mobile phones are FPGA-centric structural checks for Xilinx and Altera. System-Level Design: significant increase of the computational capability based on multiprocessor systems-on-chip (MPSoC). Blue Pearl’s unique clock domain crossing analysis Behavioural Modelling & Analysis that will offer end-users ever improving services and Programming such embedded systems suffers from a includes checks through CORE Generator™ and Acceleration & Emulation functionalities. However, the same path that is complex tool-chain and programming process. MegaCore™ functions using Blue Pearl’s Grey Cell™ Hardware/Software Co-Design leading technologies toward these remarkable The ALMA project aims to mitigate this problem through methodology. Blue Pearl automatically generates SDC Embedded Software Development: achievements is also making electronic devices the introduction and exploitation of a Scilab - based timing constraints for downstream tools from Altera, increasingly unreliable. Reliability of electronic tool-chain, which enables the efficient mapping of Cadence, Mentor, Synopsys and Xilinx. Real Time Operating Systems Software/Modelling systems is therefore a key challenge for the whole

22 DATE 14 Event Guide DATE 14 Event Guide 23 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

information and communication technology and must from MEMSCAP), THELMA from STMicroelectronics, also includes support for multi-processor profiling, RTLVisionTM PRO – a graphical debugger for be guaranteed without penalizing or slowing down the MIDIS from TELEDYNE DALSA and bulk micromachining verification, programming, and debug. SystemsVerilog, Verilog and VHDL based designs. characteristics of the final products. from AMS. Design kits for most IC CAD tools and Codix IP Cores provide a proven extensible processing CLERECO research project (http://www.clereco.eu), a Engineering kits for MEMS are available. Assembling is platform that can be adapted to a customer’s needs. GateVision® PRO – a customizable debugger for Verilog, FP7 Collaboration Project involving Politecnico di provided in a wide range of plastic and ceramic packages. These cores are an ideal starting point for customers new LEF/DEF and EDIF based designs. Torino (Italy), National and Kapodistrian University of to ASIP design allowing for rapid integration while still Athens (Greece), LIRMM (France), Intel Corporation Product Finder delivering a great deal of flexibility. A variety of Codix SpiceVision® PRO – a customizable debugger for SPICE Iberia S.A. (Spain), Thales SA (France), Yogitech spa Cores are available covering DSP, RISC, and VLIW based designs. (Italy) and ABB AS (Norway), recognizes early accurate ASIC and SOC Design: technologies. reliability evaluation as one of the most important and MEMS Design StarVision® PRO - a customizable mixed-signal and challenging tasks toward this goal. Being able to Services: Product Finder mixed-language debugger. precisely and early evaluate the reliability of a system Prototyping ASIC and SOC Design: means being able to carefully plan for specific Foundry & Manufacturing Product Finder countermeasures rather than resorting to worst-case Verification approaches. System-Level Design: ASIC and SOC Design: Verification The proposed CLERECO framework for efficient reliability booth 7 Hardware/Software Co-Design evaluation and therefore efficient exploitation of Analogue and Mixed-Signal Design Services: MEMS Design reliability oriented design approaches starting from Codasip Prototyping early phases of the design process will enable circuit RF Design Embedded Software Development: integration to continue at exponential rates and enable Contact: Karel Masarik Test: the design and manufacture of future systems for the Compilers Design for Test computing continuum at a minimum cost contrary to Codasip Ltd. Debuggers existing worst-case-design solutions for reliability. The Bozetechova 1/2 Semiconductor IP: applications of such chips will play a major role in several 612 66 Brno CPUs & Controllers booth eP 1 fields ranging from avionics, automobile, smartphones, Czech Republic Processor Platforms mobile systems, and future servers utilized in the Application-Specific IP: CONTREX settings of several types of HPC systems. Phone: +420608132875 Fax: +420541 211 479 Digital Signal Processing Multimedia Graphics Contact: Kim Grüttner Email: [email protected] booth 17 Website: www.codasip.com OFFIS – Institute for Information Technology Escherweg 2 booth 11 CMP: Circuits Multi-Projects Codasip delivers leading-edge IP and EDA tools to enable 26121 Oldenburg adoption of Application Specific Instruction Set Concept Engineering GmbH Germany Contact: Bernard Courtois Processors (ASIP’s). ASIP’s utilize dedicated instructions Phone: +49 441 97 22 228 to accelerate software and are at the heart of Contact: Gerhard Angst CMP: Circuits Multi-Projects applications such as software defined radio and Email: [email protected] 46 avenue Felix Viallet computer vision - delivering very high performance with Concept Engineering GmbH Website: contrex.offis.de 38031 Grenoble low power. Codasip’s unique technology makes ASIP Boetzinger Str. 29 France adoption as simple and easy as standard embedded 79111 Freiburg CONTREX (Design of embedded mixed-criticality CONTRol Phone: +33 476574617 processor cores. Germany systems under consideration of EXtra-functional Fax: +33 476473814 The Codasip® Framework provides an all-in-one properties) will enable energy-efficient and cost aware development environment for ASIP design, verification, Phone: +49 761 470940 design through analysis and optimization of real-time, Email: [email protected] programming and debugging. Codasip® Framework Fax: +49 761 4709429 power, temperature and reliability with regard to shortens development time substantially when application demands at different criticality levels. Website: cmp.imag.fr Email: [email protected] compared to competing ASIP design platforms Website: www.concept.de automating many of the otherwise time consuming and CMP is a manufacturing broker for ICs and MEMS, for error prone tasks, while at the same time delivering prototyping and low volume production. Since 1981, Concept Engineering develops and markets innovative higher performance ASIPs. Leveraging open technologies visualization and debugging technology for commercial more than 1000 Institutions from 70 countries have and standards throughout ensures integration with any been served, more than 6700 projects have been EDA vendors, in-house CAD tool developers, FPGA and IC design and programming environment - these designers. prototyped through 800 manufacturing runs, and 60 technologies cover synthesizable RTL, UVM and TLM- different technologies have been interfaced. Integrated based verification and LLVM-based programming tool- Circuits are available on CMOS, SiGe BiCMOS, HV-CMOS, Nlview WidgetsTM – a family of schematic generation chain for the target processor. A wide variety of and visualization engines (Tcl/TK, MFC, Qt, Java, Perl/ CMOS-Opto from STMicroelectronics and AMS down to 28 processor verification models are automatically nm FDSOI, 3D-IC from TEZZARON/GLOBALFOUNDRIES. Tk, wxWidgets) that can be easily integrated into EDA generated supporting virtual prototyping, system tools. MEMS are available on various processes: specific MEMS simulation and detailed debug. The Codasip® Framework technologies (PolyMUMPS, SOIMUMPS, MetalMUMPS

24 DATE 14 Event Guide DATE 14 Event Guide 25 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

booth 19 Product Finder Next to the design service for customers, DCT develops Networking and delivers also own technologies and products. As well Security CREATIVE CHIPS GmbH ASIC and SOC Design: as technologies for 2D and 3D image processing pipelines Telecommunication Analogue and Mixed-Signal Design and for video compression functionality this also Wireless Communication RF Design includes a Super Slow Motion module which extends the Contact: Anne Stroot Test: operational area of simple industrial cameras without Test Automation (ATPG, BIST) integrated image processing capability and which is booth EP 1 CREATIVE CHIPS GmbH Mixed-Signal Test used in professional slow motion systems. Im Bubenstück 1 Services: Founded at the beginning of 2010, DCT today employs 35 DREAMS 55411 Bingen Design Consultancy development engineers; the yearly turnover is around Germany Prototyping EUR 4 million. Contact: Roman Obermaisser Phone: +49-6721-98722-14 Semiconductor IP: Universität Siegen Analogue & Mixed Signal IP Product Finder Fax: +49-6721-98722-70 Department Elektrotechnik und Informatik CPUs & Controllers ASIC and SOC Design: Lehrstuhl Embedded Systems Email: [email protected] Encryption IP Design Entry Hölderlinstraße 3 Website: www.creativechips.com Application-Specific IP: Behavioural Modelling & Simulation 57076 Siegen Analogue & Mixed Signal IP Synthesis Germany CREATIVE CHIPS offers the complete service of a Fabless Power & Optimisation Semiconductor Vendor. From specification, complete IC Physical Analysis (Timing, Themal, Signal) Phone: +49 271 740 3332 Verification development, sample production, qualification for booth TP 2 Email: [email protected] series production and the documentation up to mass System-Level Design: Website: www.dreams-project.eu production and volume deliveries of ASICs and ASSPs, Dream Chip Technologies GmbH Acceleration & Emulation tested in our in-house test department. Hardware/Software Co-Design DREAMS (Distributed Real-time Architecture for Mixed The company´s headquarter is located in Bingen /Rhein Contact: Jens Benndorf PCB & MCM Design criticality Systems) will develop a cross-domain in Germany with design center in Dresden and an Asia Test: architecture and design tools for networked complex sales office located in Israel. As an automotive supplier Dream Chip Technologies GmbH Design for Test systems where application subsystems of different the company is certified according to the quality Steinriede 10 Logic Analysis criticality, executing on networked multi-core chips, are standard for the automotive industry ISO/TS 16949. 30827 Garbsen Test Automation (ATPG, BIST) supported. CREATIVE CHIPS offers the following services: Germany Boundary Scan • Turn-key circuit design, sample production, Phone: +49 5131 90805-0 Silicon Validation evaluation and qualification for mass production of a System Test booth K 3 custom specific mixed-signal ASIC or pure analog but Fax: +49 5131 90805-102 Services: also complex digital integrated circuits – ASICs and Design Consultancy EDA Confidential standard ICs Email: [email protected] Website: www.dreamchip.de Prototyping • Test and delivery of bulk production IC volumes to Training Contact: Peggy Aycinena our customers regarding flexible and defined quality Dream Chip Technologies (DCT) - located in Garbsen near Embedded Software Development: EDA Confidential and logistic demands with backend services as tape Hanover - is an independent fabless microelectronic Real Time Operating Systems & reel, dry packing or long time storage of parts San Mateo engineering company with a long history in development Software/Modelling CA, 94402-2241 • complete supply chain management for IC of embedded Software and PCBs and in FPGAs and ASICs Hardware: United States production for highly complex System-on-Chips (SoCs). Next to pure FPGA & Reconfigurable Platforms • FPGA / ASIC conversion development, DCT offers also the delivery of the Development Boards Phone: +1 650-579-7952 developed products. Fax: +1 650-579-7952 ASICs from CREATIVE CHIPS are used in various Semiconductor IP: applications like: Founded as SICAN more than 20 years ago and belonging as SCI-WORX to Infineon for several years, DCT comes Configurable Logic IP Email: [email protected] • Automotive electronics (f.e. robust sensor and today with outstanding know-how in the development Embedded FPGA Website: www.aycinena.com control circuits for car environment) of challenging microelectronics especially for video and Embedded Software IP • Automation industry (f.e. optical transimpedance imaging applications. Encryption IP EDA is a commercial-free publication providing a quiet amplifiers with integrated sensors, bus interface ICs, DCT focuses on microelectronic manufacturers for the On-Chip Bus Interconnect place for conversation about the Electronic Design smart power supply circuits) industrial and the consumer market who want to offer On-Chip Debug Automation industry and its companion technologies. Processor Platforms The coverage does not intend to be comprehensive, but • Multimedia (f.e. broadband optical data transmission market-driven products in an optimum time frame, without permanently being able to provide the required Synthesizable Libraries does intend to provide some food for thought. To that systems, RF data transmission in 433/868 MHz band, end, EDA Confidential includes “Recipes”, Freddy buck-boost converters) capacity for development. Application-Specific IP: Our customers are mainly product makers in the Data Communication Santamaria’s “Gourmet Corner”, as well as “Voices” of • Consumer electronics and white goods (f.e. motor automotive, industrial and medical area, for professional Digital Signal Processing other contributing authors, “Off the Record” op-ed drivers, battery charging circuits). video applications and for consumer electronics. Multimedia Graphics pieces, and “Conference” coverage.

26 DATE 14 Event Guide DATE 14 Event Guide 27 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

booth 20 booth 10 ECS draws its strength from highly qualified engineers booth eP 1 with Ph.D. in computer architecture for embedded EDA Solutions LTD Elsevier BV systems. Our expertise is based on nearly ten years of European Project Cluster on Mixed- track records in advanced R&D projects and product Criticality Systems (DREAMS, Contact: Lynne Wright Contact: James Palser development. Our strong scientific background allows us to quickly find the best solutions for your project PROXIMA, CONTREX, MultiPARTES) EDA Solutions Limited Elsevier BV challenges. Unit A5, Segensworth Business Centre Radarweg 29 We have a cross-layer expertise ranging from OS down to Contact: Kim Grüttner Segenswoth Road, Fareham, Hants PO15 5RQ 1043 NX Amsterdam ASIC & FPGA physical level. It allows us to quickly United Kingdom The Netherlands understand and evaluate the impact of a technology OFFIS FuE Bereich Verkehr choice on the final performances of a particular R&D Division Transportation Phone: +44 1489 564 253 Phone: +44 1865 843237 application. This transverse knowledge is a key asset to Escherweg 2 Fax: +44 1489 557 367 cope with today’s multicore and heterogeneous platform 26121 Oldenburg Email: [email protected] Germany Email: [email protected] Website: www.elsevier.com/computerscience challenges. Website: www.eda-solutions.com Phone: +49 441 9722-228/278 ELSEVIER – COMPUTER SCIENCE Product Finder For over 10 years EDA Solutions have provided cost Elsevier is a leading international publisher of Computer Email: [email protected] System-Level Design: Website: www.offis.de effective and highly productive IC Design software and Science journals, books and electronic products. Behavioural Modelling & Analysis manufacturing services to European industry. Visit us at By delivering first class information and innovative Acceleration & Emulation The European Project Cluster on Mixed-Criticality our stand to find out more about the digital synthesis tools, we continue to refine our portfolio to serve the Hardware/Software Co-Design tools from Incentia, the analog/mixed signal design, research need of industry professionals, researchers and Systems has been started in October 2013 and consists layout and verification tools from Tanner EDA and the students worldwide. Services: of the following European projects, attacking several MPW and low volume production services from MOSIS. We are proud to play an integral part within the computer Design Consultancy challenges and aspects of Mixed-Criticality Systems: science community and to participate in the Prototyping advancement of this field. All our journals are available Training DREAMS, PROXIMA, CONTREX and MultiPARTES. For a detailed description on the individual projects, please booth K 4 online via ScienceDirect (www.sciencedirect.com) the Embedded Software Development: essential information resource for over 14 million Compilers have a look at the exhibitor list. Elektronik i Norden scientists worldwide. Real Time Operating Systems Visit our booth to meet publishers and editors and view Debuggers Contact: Göte Fagerfjäll the latest journal information on microelectronics and Software/Modelling booth 1 electronic system design. We will be introducing our Hardware: Phone: +46 8 540 865 12 new editor for Microelectronics Journal and celebrating FPGA & Reconfigurable Platforms EUROPRACTICE the 30th Anniversary of Microelectronic Engineering Email: [email protected] Development Boards Journal with various activities. Workstations & IT Infrastructure Contact: Carl Das Website: www.elinor.se We look forward to meeting you! Semiconductor IP: IMEC vzw Elektronik i Norden, an important tool for the Nordic Configurable Logic IP Kapeldreef 75 electronic industry. We want Elektronik i Norden to be CPUs & Controllers 3001 Leuven the most important source of information for the Nordic booth 2 Processor Platforms Belgium electronic industry (Sweden, Finland, Norway and Embedded Computing Specialists Application-Specific IP: Phone: +32 16 28 12 48 Denmark). A circulation of 25 800 personally addressed Digital Signal Processing copies proves we are the major electronics paper in this Contact: Bertrand Rousseau Multimedia Graphics Email: [email protected] area. We publish news, comments and in-depth technical Website: www.imec.be articles. Embedded Computing Specialists Av. de Messidor, 213/3 The EUROPRACTICE Service offers CAD tools for 1180 Brussels education, low cost and easy access to ASIC prototype Belgium and small volume fabrication. The service is offered by IMEC (B), STFC (UK) and Fraunhofer IIS (D). Low cost Phone: +32 498/105 795 prototyping is achieved by offering fabrication through Email: [email protected] regularly scheduled MPW runs whereby many designs are Website: www.ecspec.com merged onto the same fabrication run. These runs are fabricated in industrial CMOS, BiCMOS and SiGe processes Embedded Computing Specialists provides engineering from 0.7µ to 40nm at well-known foundries (ONSemi, services and solutions for embedded computing. We austiamicrosystems, IHP, LFoundry, TSMC, UMC). A total specialize in R&D projects where you are looking for integrated design and manufacturing flow is offered technology leap or performance breakthrough. including cell library and design kit access and support, deep submicron netlist-to-layout, ASIC prototyping on

28 DATE 14 Event Guide DATE 14 Event Guide 29 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

MPW or dedicated single project prototype runs, volume Furthermore, Eurotraining establishs the training booth tP 3 Training fabrication, qualification, assembly and test. Volume requirements of EU companies with production or Embedded Software Development: fabrication starts with wafer batches as low as 12 wafers development in Far East and develops dedicated Fraunhofer EMFT Software/Modelling but can go up to more than 5000 wafers per year per webinars which will be available on www.eurotraining. ASIC. net. Semiconductor IP: Contact: Pirjo Larima-Bellinghoven Analogue & Mixed Signal IP Verification IO Product Finder Fraunhofer EMFT booth eP 5 Hansastraße 27d Application-Specific IP: Test: 80686 München Analogue & Mixed Signal IP Design for Test FlexTiles Consortium Germany Data Communication Design for Manufacture and Yield Telecommunication Boundary Scan Phone: +49 89 54759 542 Wireless Communication Silicon Validation Contact: Philippe Millet Email: pirjo.larima-bellinghoven@ Mixed-Signal Test THALES R&T System Test emft.fraunhofer.de Campus Polytechnique Website: www.emft.fraunhofer.de booth 12 Services: 1 avenue Augustin Fresnel Prototyping 91767 Palaiseau Cedex Fraunhofer EMFT conducts cutting-edge applied Fraunhofer Institute for Integrated Semiconductor IP: France research into sensors and actuators for man and the Circuits IIS Analogue & Mixed Signal IP Phone: +33 1 69 41 60 49 environment. The core competences of the research Physical Libraries Fax: +33 1 69 41 60 01 departments in Munich and Regensburg with hundred Contact: Melanie Ruge employees include: silicon technology, flexible Email: [email protected] electronics, chemical sensor materials and the capability Fraunhofer Institute for Integrated Circuits IIS booth eP 2 Website: www.flextiles.eu of system integration. Each of these core competences Design Automation Division EAS in its own right allows new kinds of sensors and actuators Zeunerstr. 38 EuroTraining – Training in A major challenge in computing is to leverage multi-core to be created. But the real strength of Fraunhofer EMFT 01069 Dresden technology to develop energy-efficient high performance lies in the interaction between these areas: after all, Germany Nanoelectronics systems. This is critical for embedded systems with a innovations often emerge where technologies reach very limited energy budget as well as for supercomputers their limits and begin to cross-fertilize. This enables the Phone: +49 351 4640 707 Contact: Annette Locher in terms of sustainability. Moreover the efficient creation of innovative solutions for various business and Fax: +49 351 4640 703 FSRM – Swiss Foundation for Research in programming of multi-core architectures, as we move application areas. The business area “Design and Test” Email: [email protected] ­Microtechnology towards manycores with more than a thousand cores offers customized services from development of Website: www.eas.iis.fraunhofer.de Ruelle DuPeyrou 4 predicted by 2020, remains an unresolved issue. The integrated circuits to integrated components as well as 2001 Neuchâtel FlexTiles project will define and develop an energy- complete systems and equipment. The services portfolio The Fraunhofer Institute for Integrated Circuits IIS is Switzerland efficient yet programmable heterogeneous manycore also includes multiparametric characterization and one of Germany’s most important research facilities for platform with self-adaptive capabilities. reliability prognoses for the planned application. the development of microelectronic systems. The Phone: +41 32 720 09 30 The manycore will be associated with an innovative scientists in the Design Automation Division EAS in virtualisation layer and a dedicated tool-flow to improve Product Finder Dresden work on new methods of modeling, simulation Email: [email protected] programming efficiency, reduce the impact on time to Website: www.eurotraining.net ASIC and SOC Design: and optimization of systems as well as debugging, market and reduce the development cost by 20 to 50%. analysis and formal verification. These methods ensure FlexTiles will raise the accessibility of the manycore Design Entry EuroTraining develops and runs the website www. Behavioural Modelling & Simulation that developed complex electronic and mechatronic technology to industry – from small SMEs to large systems meet the required specifications at every design eurotraining.net offering access to hundreds of courses, companies – thanks to its programming efficiency and Verification summer schools, lecturing material and on-line tutorials Analogue and Mixed-Signal Design stage and errors are identified before components are its ability to adapt to the targeted domain using built. in the field of nanoelectronics and micro-nano systems. embedded reconfigurable technologies. MEMS Design RF Design By applying knowledge and innovative solutions, the Contract number: 288248 division aims at achieving a faster, more efficient and The service addresses industry and universities which Project coordinator: THALES System-Level Design: are also encouraged to share the basic development of last but not least a more cost saving design of products. Behavioural Modelling & Analysis One goal of particular importance is a high design courses, text books and training material on the Physical Analysis EuroTraining website. quality despite ever more complex systems. Thus, our PCB & MCM Design scientists take account of the growing requirements Course providers, universities or European project can Test: concerning reliability and robustness of systems. announce their training offer on eurotraining.net for Test Automation (ATPG, BIST) The EAS Division is involved in national and international free. The events can also be included in the monthly Silicon Validation networks in research and numerous standardization newsletter to over 10’000 addresses. Contact: Mixed-Signal Test activities. Its results of work and developments are eurotraining polito System Test applied in microelectronics and its domains, such as [dot] it. Services: communication technology, automotive industry or Design Consultancy automation. Prototyping

30 DATE 14 Event Guide DATE 14 Event Guide 31 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

Product Finder IC design, systems, and design service companies advancements from the software development • Communication & webcasts services worldwide and have produced numerous customer community. • Events: Yole Seminars, Market Briefings ASIC and SOC Design: tape-outs, including those using advanced 40nm Our highly scalable and industry proven solutions are Design Entry technologies and designs over 50 million gates. ideal for small specialized IP design teams, as well as Behavioural Modelling & Simulation Incentia are represented in Europe by EDA Solutions, large multinational, multisite, SoC design teams. booth 20 Physical Analysis (Timing, Themal, Signal) who will be happy to explain more to you about our For further information, visit www.methodics.com. Verification services, and answer any questions you may have. Why Analogue and Mixed-Signal Design MOSIS not come to our stand or visit the EDA Solutions Product Finder MEMS Design website www.eda-solutions.com for more details. RF Design ASIC and SOC Design: Contact: Lynne Wright Design Entry System-Level Design: Product Finder EDA Solutions Limited Behavioural Modelling & Analysis Analogue and Mixed-Signal Design Unit A5, Segensworth Business Centre Physical Analysis ASIC and SOC Design: Services: Segenswoth Road, Fareham, Hants PO15 5RQ Hardware/Software Co-Design Synthesis Data Management and Collaboration United Kingdom Package Design Power & Optimisation IP e-commerce & Exchange PCB & MCM Design Physical Analysis (Timing, Themal, Signal) Phone: +44 1489 564 253 Fax: +44 1489 557 367 Test: Test: Design for Test Design for Test booth K 1 Email: [email protected] Design for Manufacture and Yield Logic Analysis Website: www.eda-solutions.com Test Automation (ATPG, BIST) Test Automation (ATPG, BIST) Micronews Media, powered by Yole Mixed-Signal Test Boundary Scan Développement MOSIS is a low-cost prototyping and small-volume System Test production service for VLSI circuit development. Since Embedded Software Development: Contact: Camille Veyrier 1981, MOSIS has fabricated more than 50,000 circuit Real Time Operating Systems booth 15 designs for commercial firms, government agencies, and Software/Modelling research and educational institutions around the world. Methodics Yole Développement Processes offered include SOS, SOI, CMOS and SiGe Semiconductor IP: Le Quartz, 75 Cours Emile Zola BiCMOS, in geometries from 0.7um to 32nm, from the Analogue & Mixed Signal IP Contact: Christian Burisch 69100 Villeurbanne – Lyon foundries IBM, TSMC, ON Semiconductor, Application-Specific IP: France austriamicrosystems, Globalfoundries, and Peregrine. Networking Methodics, Inc. MOSIS are represented in Europe by EDA Solutions, who Wireless Communication 2370 Market St, #506 Phone: +33 472 83 01 01 will be happy to explain more to you about our services, San Francisco, CA 94114 and answer any questions you may have. Why not come to United States Email: [email protected] Website: i-Micronews.com our stand or visit the EDA Solutions website www.eda- booth 20 Phone: +1 415 354 5726 solutions.com for more details. Fax: +1 415 354 5726 Founded in 1998, Yole Développement has grown to Incentia become a group of companies providing marketing, Product Finder Email: [email protected] technology and strategy consulting, media in addition Website: www.methodics.com Services: Contact: Lynne Wright to corporate finance services. With a strong focus on Prototyping emerging applications using silicon and/or micro Foundry & Manufacturing EDA Solutions Limited Methodics delivers state-of-the-art semiconductor data manufacturing, Yole Développement group has expanded Unit A5, Segensworth Business Centre management (DM) for analog, digital, and SoC design to include more than 50 associates worldwide covering Segenswoth Road, Fareham, Hants PO15 5RQ teams. MEMS, Compound Semiconductors, LED, Image Sensors, United Kingdom Integration of IP Lifecycle Management with powerful Optoelectronics, Microfluidics & Medical, Photovoltaics, analytics and industry-standard DM enables Methodic’s Advanced Packaging, Manufacturing, ok Nanomaterials Phone: +44 1489 564 253 solutions to significantly reduce design cost; making Fax: +44 1489 557 367 and Power Electronics. The group supports industrial design more efficient, predictable and with higher companies, investors and R&D organizations worldwide Email: [email protected] quality. Advanced IP distribution infrastructure, to help them understand markets and follow technology Website: www.eda-solutions.com cataloging, and workspace management ensure that no trends to develop their business. matter where designers are located they have full Incentia Design Systems, Inc. is a leading provider of visibility into the IP available to them and can easily MEDIA & EVENTS ACTIVITY: advanced Timing and Signal Integrity Analysis, Design access that data regardless of its location. • i-Micronews.com, online disruptive technologies Closure, and Logic Synthesis software for multi- Methodic’s clients for analog and digital designers website million-gate nanometre designs. Incentia patented integrate natively with existing design environments • Weekly WebTalk technologies provide the fastest Static Timing making DM seamless to the users. Building our solutions • @Micronews, weekly e-newsletter Analysis (STA) tool in the market today. Incentia’s on top of standard Subversion and Perforce • Technology Magazines dedicated to MEMS, Advanced products are in use at leading semiconductor, fabless infrastructure ensures data is safe, always available, Packaging, LED and Power Electronics and that the tools can take advantage of the latest

32 DATE 14 Event Guide DATE 14 Event Guide 33 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

booth eP 1 booth 27 Product Finder Services: Design Consultancy ASIC and SOC Design: MultiPARTES now publishers inc. Verification Contact: Salvador Trujillo Contact: James Finlay booth eP 1 IKERLAN-IK4 now publishers inc. booth 9 PROXIMA JM Arizmendiarrieta, 2 PO Box 179 20500 Arrasate (Gipuzkoa) 2600 AD Delft ProPlus Design Solutions, Inc. Contact: Francisco J. Cazorla Spain The Netherlands Contact: Amit Nanda Barcelona Supercomputing Center - Centro Nacional de Phone: +34 689022454 Phone: +31 6 1448 3632 Supercomputación ProPlus Design Solutions, Inc. C/Jordi Girona, 29, Ed. Nexus II, 3rd Pl. Email: [email protected] Email: [email protected] 2025 Gateway Place, Suite 130 Website: www.multipartes.eu Website: www.nowpublishers.com 08034 Barcelona San Jose, CA 95110 Spain United States MultiPARTES (Multicore Partitioned Systems) aims at Publishers of the highly acclaimed FOUNDATIONS AND Phone: +34 93 413 7173 developing tools and solutions for building trusted TRENDS journals. Peer-reviewed surveys, reviews and Phone: +1 408-459-6067 embedded systems with mixed criticality components tutorials in electronic design automation. Visit our Email: [email protected] on multicore platforms based on the XtratuM hypervisor. booth to browse the available titles and meet the Email: [email protected] Website: www.proxima-project.eu publisher. All print titles available for the special DATE Website: www.proplussolution.com price of €35. www.nowpublishers.com/eda PROXIMA (PRObabilistic real?time control of ProPlus Design Solutions, Inc. delivers Electronic booth 14 miXed?crIticality Multicore and mAnycore systems) will Design Automation (EDA) solutions with the mission define new hardware and software architectural to enhance the link between design and MunEDA GmbH booth 26 paradigms based on the concept of randomization. It manufacturing. It is the global leader for SPICE extends this approach across the hardware and modeling solutions and the leading technology Contact: Jin Qiu OneSpin Solutions GmbH software stack ensuring that the risks of temporal provider for unique Design-for-Yield (DFY) products pathological cases are reduced to probabilistically that integrate the key DFY components –– advanced MunEDA GmbH Contact: Oliver Habeck quantifiable small levels. Stefan-George-Ring 29 device modeling software, a parallel SPICE simulation 81929 Munich OneSpin Solutions GmbH circuit simulator and hardware-validated statistical variation analysis tools. Products include: Germany Nymphenburger Str. 20a booth tP 1 80335 Munich BSIMProPlus™/Model Explorer™, a modeling Phone: +49 89 930 86 330 Germany technology platform for nanometer devices; Fax: +49 89 930 86 407 NoisePro™/9812B/9812D, the golden solution for low- RacyICs GmbH Phone: +49 89 99013498 frequency 1/f noise and Random Telegraph Signal Email: [email protected] (RTS) noise characterization and process monitoring; Contact: Holger Eisenreich Website: www.muneda.com Fax: +49 89 99013 400 NanoSpice™, a high-capacity, high-performance RacyICs GmbH Email: [email protected] parallel SPICE simulator for giga-scale circuit Graue-Presse-Weg 11 MunEDA provides leading EDA software technology for simulation; and NanoYield™/NanoExplorer™, a analysis, modelling and optimization of yield and Website: www.onespin-solutions.com 01445 Radebeul variation analysis platform for yield versus power, Germany performance of analog, mixed-signal and digital designs. performance and area trade-off of memory, analog and MunEDA´s products and solutions enable customers to OneSpin Solutions is a pioneer of advanced, award winning formal verification technologies, incubated at digital circuit designs. ProPlus Design Solutions has Phone: +49 351 418872 10 reduce the design times of their circuits and to maximize R&D centers in the San Jose, Calif. and Beijing and Fax: +49 351 418872 99 robustness, reliability and yield. MunEDA´s solutions are Infineon and leveraging 300+ engineering years of development and applications experience. The Jinan, China, with sales offices in Tokyo, Japan, in industrial use by leading semiconductor companies in Hsinchu, Taiwan, and Shanghai, China. Email: [email protected] the areas of communication, computer, memories, company’s product line includes plug & play design Website: www.racyics.com automotive, and consumer electronics. analysis requiring no knowledge of formal methods, to powerful, exhaustive, coverage-driven property Product Finder RacyICs, an experienced fabless design house based in verification and sequential FPGA and ASIC Equivalency ASIC and SOC Design: Dresden, Germany, offers design and implementation Checking. Excelling in ease-of-use, high-performance Behavioural Modelling & Simulation services for analog, mixed-signal and digital ICs. and accessibility, OneSpin’s products have been Power & Optimisation Working for leading European semiconductor companies leveraged by a large number of electronic product and Physical Analysis (Timing, Themal, Signal) for many years, the RacyICs team contributed to semiconductor companies on many leading edge Verification numerous successful chip designs down to 28nm feature designs. The company maintains its headquarters and Analogue and Mixed-Signal Design size for automotive, consumer and communication engineering teams in Munich, Germany and operates on RF Design applications. As GLOBALFOUNDRIES’ channel partner a global basis. Test: with focus on advanced and leading edge technologies, Design for Manufacture and Yield RacyICs provides access to 28nm prototyping runs

34 DATE 14 Event Guide DATE 14 Event Guide 35 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

(MPWs) and required design enablement services for industry and academia on the design of future energy governments and businesses, for suppliers and booth 22+23 European SMEs and academia. For more information, efficient-computing systems. consumers alike. visit www.racyics.com. More information: SPRINGER www.sgsgroup.de /www.institut-fresenius.sgsgroup.de Product Finder booth 13 Contact: Lothar Minicka Services: SGS INSTITUT FRESENIUS GmbH booth 13 SPRINGER Design Consultancy Tiergartenstr. 17 Prototyping Contact: Andre Möller Silicon Saxony e.V. 69121 Heidelberg Data Management and Collaboration Germany IP e-commerce & Exchange SGS INSTITUT FRESENIUS GmbH Contact: Gitta Haupold Foundry & Manufacturing Königsbrücker Landstr. 161 Phone: +49 6221 4870 Training 01109 Dresden Silicon Saxony e.V. Fax: +49 6221 4878366 Semiconductor IP: Germany Manfred-von-Ardenne-Ring 20 Email: [email protected] Analogue & Mixed Signal IP 01099 Dresden Website: www.springer.com Embedded FPGA Phone: +49 351 8841 100 Germany Memory IP Fax: +49 351 8841 190 Looking to publish your research? Discover Springer’s On-Chip Bus Interconnect Phone: +49 351 8925 887 Fax: +49 351 8925 889 print and electronic publication services, including Physical Libraries Email: [email protected] Open Access! Get high-quality review, maximum Synthesizable Libraries Website: www.institut-fresenius.sgsgroup.de Email: [email protected] readership and rapid distribution. Visit our booth or Website: www.silicon-saxony.de springer.com/authors. About SGS INSTITUT FRESENIUS You can also browse key titles in your field and buy (e) booth 6 As one of the leading providers of laboratory analysis in Silicon Saxony is Europe’s most successful trade books at discount prices. With Springer you are in good Germany, SGS INSTITUT FRESENIUS has a strong association for the semiconductor, microsystems, company. SFB HAEC (TU Dresden) reputation among manufacturers and retailers along the software and photovoltaic industries. We are connecting supply chain of the high-tech industry. The SGS 300 commercial enterprises, research institutes, INSTITUT FRESENIUS laboratory in Dresden offers Contact: Nicolle Seifert universities and public institutions. The competencies booth 8 testing services for microelectronics and nanostructures. of our members represent the entire value creation chain TU Dresden, HAEC The personnel is also specialized in the analysis and of the microelectronics industry. In addition, the Synflow Georg-Schumann-Straße 11 testing of material, surface and thin layers as well as in network is expanding to sectors as the energy and 01062 Dresden the analysis of process media. The experts analyse software industries. As a continuously growing and vital Contact: Nicolas Siret Germany nanostructures and nanolayers with regard to their high-tech network, we understand ourselves as a material-specific and structural properties. SGS communication and cooperation platform for our Synflow Email: [email protected] INSTITUT FRESENIUS also provides services for Website: www.tu-dresden.de/sfb912 members. This promotes and stabilizes the economic 2 rue de la Châtaigneraie, CS 17607 microelectronic design as construction analysis, failure development of our member companies. Intelligent 35576 Cesson-Sévigné and damage analysis and FIB modification of integrated The collaborative research center HAEC is a first attempt partnerships among them enable knowledge transfer, France circuits. For all testing services the experienced synergies, business relationships and promote to achieve high adaptivity and energy efficiency in such personnel utilise leading edge chemical and physical Phone: +33 299127902 an integrated approach. At the circuit level, we focus on innovative power. At our joint booth, you can meet us analytical equipment. SGS INSTITUT FRESENIUS is part and companies from Silicon Saxony, presenting their innovative ideas for optical and wireless chip-to-chip of the SGS Group. Email: [email protected] communication. At the network level, we research expertise in the field of microelectronics – a business Website: www.synflow.com About SGS sector Saxony has a European leadership role in! secure, high performance network coding schemes for SGS is the world’s leading inspection, verification, wired and wireless board-to-board communication. testing and certification company. SGS is recognised as Synflow SAS is an EDA start-up company that helps Innovative results at the hardware/software interface the global benchmark for quality and integrity. With hardware designers increase their productivity by level will include energy control loops, which allow more than 80.000 employees, SGS operates a network of making design and verification easier. For this purpose, hardware to adapt to varying software requirements and over 1.650 offices and laboratories around the world. we develop and market EDA software based on a vice versa. Software development in general is supported SGS provides solutions across all industries. Through a disruptive technology for IP and SoC design combining a by energy-aware runtimes, energy-aware resource, unique global network SGS delivers independent results new language called C~ (C flow) and an Eclipse-based stream and configuration management schemes and by tailored to the precise needs of the industry or sector. IDE that verifies C~ designs and translates them (on-the- an analysis framework for high performance/low energy Founded in 1878, the company is headquartered in fly) into Verilog and VHDL. We also provides support for applications. New internet applications are supported Geneva. our software to help designers learning the C~ language by innovations in energy-aware service execution. And, Since 1920, SGS has been operating in Germany. SGS faster and master the IDE, as well as advice and tips to last but not least, formal methods are developed to offer Group Germany provides inspection services for write better C~ code to design IP cores and SoCs with the a new quality of assurance in our systems of tomorrow. international trade, industrial goods, agriculture, the highest performance possible. We chose to create a new Demonstrating our results in a joint prototype - the extractive industry and the consumer goods industry. language to provide designers with a modern, hardware- HAEC Box - our goal is to become a pace setter for The company works for producers and traders, oriented language that is more adapted to their needs than RTL – this language has the particularity of

36 DATE 14 Event Guide DATE 14 Event Guide 37 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

allowing any kind of design to be created with ease and will be happy to explain more to you about our services, onsite download service. Furthermore, FlashAir allows System-Level Design: efficiency. We also made the choice of generating and answer any questions you may have. Why not come you both peer-to-peer transfers and uploads to and Behavioural Modelling & Analysis vendor-neutral, clean, readable Verilog and VHDL that to our stand or visit the EDA Solutions website www.eda- downloads from servers if the device supports iSDIO. Physical Analysis respects the coding rules imposed or recommended by solutions.com for more details. FlashAir opens up many new possibilities. Please stop by Acceleration & Emulation synthesizers and lint tools. Our users have succeeded in our TOSHIBA booth to see some demos. Hardware/Software Co-Design designing applications with a mix of control and Product Finder Package Design dataflow up to 10x faster than using RTL with equivalent PCB & MCM Design ASIC and SOC Design: Product Finder synthesis results. Test: The Synflow SAS company was founded by Nicolas Siret Design Entry Application-Specific IP: Behavioural Modelling & Simulation Wireless Communication Design for Test and Matthieu Wipliez, two PhDs specialized in hardware Design for Manufacture and Yield engineering and software engineering, who worked on Verification Analogue and Mixed-Signal Design Logic Analysis models and code compilation with other researchers in Test Automation (ATPG, BIST) the EU. MEMS Design booth 3 RF Design Boundary Scan Silicon Validation Product Finder Test: University Booth Mixed-Signal Test Silicon Validation System Test ASIC and SOC Design: Mixed-Signal Test Contact: Andreas Vörg (edacentrum), Design Entry Jens Lienig (TU Dresden) Services: Behavioural Modelling & Simulation Design Consultancy Verification edacentrum Prototyping booth 16 System-Level Design: Schneiderberg 32 Data Management and Collaboration Behavioural Modelling & Analysis 30167 Hannover IP e-commerce & Exchange TOSHIBA Germany Foundry & Manufacturing Services: Training Prototyping Contact: Mari Takada TU Dresden Helmholtzstraße 18 Embedded Software Development: Semiconductor IP: Toshiba Corporation Compilers Encryption IP 01069 Dresden 1-1, Shibaura 1-chome, Minato-Ku Germany Real Time Operating Systems Synthesizable Libraries Tokyo, 105-8001 Debuggers Application-Specific IP: Japan Phone: +49 511 762 19686 (Andreas Vörg) Software/Modelling Networking Fax: +49 511 762 19695 (Andreas Vörg) Hardware: Telecommunication Phone: +81 3 34573435 Email: [email protected] FPGA & Reconfigurable Platforms Email: [email protected] Website: wwww.date-conference.com/group/ Development Boards Website: www.toshiba.co.jp/worldwide exhibition/u-booth Workstations & IT Infrastructure booth 20 Semiconductor IP: In 1987, Toshiba invented NAND Flash technology. The University Booth is part of the DATE 2014 exhibition Analogue & Mixed Signal IP Tanner EDA Today, Toshiba offers one of the industry’s broadest line- programme and is sponsored by the DATE Sponsor Configurable Logic IP ups of NAND Flash-based storage solutions—enabling a Committee. The University Booth will be organized for CPUs & Controllers Contact: Lynne Wright wide range of applications in the consumer, mobile, EDA software and hardware demonstrations. Universities Embedded FPGA industrial, and enterprise markets. Extending its and public research institutes are presenting innovative Embedded Software IP EDA Solutions Limited industry leadership in memory storage solutions, Unit A5, Segensworth Business Centre hardware and software demonstrations. All Encryption IP Toshiba offers an innovative new SDHC memory card, demonstrations will take place during the exhibition Memory IP Segenswoth Road, Fareham, Hants PO15 5RQ “FlashAir”, which is the first to support the new Wireless United Kingdom within a dedicated time slot. The University Booth is On-Chip Bus Interconnect LAN SD standard, iSDIO. “FlashAir” is an SD memory card organized by Jens Lienig (TU Dresden) and Andreas Vörg On-Chip Debug Phone: +44 1489 564 253 with embedded wireless LAN functionality. It has a (edacentrum). Physical Libraries Fax: +44 1489 557 367 built-in web server function and a wireless LAN access Processor Platforms point. If power is supplied to the card, FlashAir can work Product Finder Synthesizable Libraries Email: [email protected] as a server. Files stored in FlashAir are accessible from Test IP Website: www.eda-solutions.com smartphones, tablets or PCs through Wi-Fi. Ad-hoc local ASIC and SOC Design: Verification IO networks between FlashAir and mobile devices are Design Entry Tanner EDA provides a complete line of software established, so that Internet access or Wi-Fi access Behavioural Modelling & Simulation Application-Specific IP: solutions that catalyze innovation for the design, layout points are not needed. The API of FlashAir is disclosed on Synthesis Analogue & Mixed Signal IP and verification of analog and mixed-signal (A/MS) the developer site. https://flashair-developers.com Power & Optimisation Data Communication integrated circuits (ICs). Customers are creating By using FlashAir, you can provide an on-site download Physical Analysis (Timing, Themal, Signal) Digital Signal Processing breakthrough applications in areas such as power service, accessible only at the venues. We have provided Verification Multimedia Graphics management, displays and imaging, automotive, the proceedings download service at ASP-DAC this Analogue and Mixed-Signal Design Networking consumer electronics, life sciences, and RF devices. January and at SASIMI last October. There are some MEMS Design Security Tanner are represented in Europe by EDA Solutions, who academic meetings which are planning to offer this RF Design Telecommunication Wireless Communication

38 DATE 14 Event Guide DATE 14 Event Guide 39 Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless Exhibitors . Exhibitorexhibitors . Ex companyhibitor profiless

booth eP 3 booth 13 applications that can be integrated with additional Product Finder functions such as high voltage, non-volatile memory or WIBRATE - Wireless, Self-Powered Wirtschaftsförderung Sachsen GmbH sensors. With its five manufacturing sites in Germany, ASIC and SOC Design: the U.S. and Malaysia, the company’s combined Design Entry Vibration Monitoring and Control for (WFS) manufacturing capacity is approximately 62,000 Behavioural Modelling & Simulation Complex Industrial Systems 8-inch equivalent wafer starts per month. X-FAB Synthesis Contact: Christiane Wagner customers benefit from high-performancePower & Optimisation Contact: Paul J. M. Havinga technologies, excellent technical design and Physical Analysis (Timing, Themal, Signal) Wirtschaftsförderung Sachsen GmbH Verification Bertolt-Brecht-Allee 22 prototyping services; and fast, easy and flexible University of Twente foundry access worldwide. The company has Analogue and Mixed-Signal Design Pervasive Systems 01309 Dresden RF Design Germany approximately 2,400 employees worldwide. For more Drienerlolaan 5 information, please visit www.xfab.com System-Level Design: 7522NB Enschede Phone: +49-351-2138 134 Behavioural Modelling & Analysis The Netherlands Fax: +49-351-2138 399 Product Finder Physical Analysis Email: [email protected] Hardware/Software Co-Design Email: [email protected] Services: PCB & MCM Design Website: www.wibrate.eu Website: www.wfs.saxony.de Prototyping Foundry & Manufacturing Test: WiBRATE’s key innovation lies in the development of a We build bridges: Between Saxon companies and Design for Test self-powered, vibration monitoring and control Semiconductor IP: Design for Manufacture and Yield cooperation partners from abroad, between potential Analogue & Mixed Signal IP platform. Unlike existing vibration monitoring devices investors and Saxony´s regions and communes, between Logic Analysis available in the market that operate as individual Memory IP Test Automation (ATPG, BIST) research and practice, between business ideas and Physical Libraries entities, WiBRATE’s unique approach is based on economic success. Boundary Scan individual intelligent sensor-actuator nodes that Synthesizable Libraries Silicon Validation communicate wirelessly to collaboratively predict Application-Specific IP: Mixed-Signal Test impending failures, perform fault diagnosis or provide Analogue & Mixed Signal IP System Test booth 13 real-time feedback. This feedback can then be used to Embedded Software Development: further minimise vibration levels using distributed and X-FAB Group Compilers autonomous micro-actuators that are capable of booth 13 & TP 4 Real Time Operating Systems carrying our robust, distributed control. The use of Contact: Anja Noack Debuggers robust wireless communication strategies ensures that Zentrum Mikroelektronik Dresden AG Software/Modelling the system is highly flexible and allows for a new class of X-FAB Semiconductor Foundries AG Hardware: monitoring and control applications that are not Haarbergstrasse 67 Contact: Andreas Brüning possible using traditional wired systems. Apart from FPGA & Reconfigurable Platforms 99097 Erfurt Development Boards measuring and controlling vibration levels, WiBRATE’s Germany Zentrum Mikroelektronik Dresden AG platform also harnesses the vibration itself thus Grenzstraße 28 resulting in a system that is both maintenance free and Phone: +49 361 427 6162 01109 Dresden environment friendly. Fax: +49 361 427 6161 Germany Email: [email protected] Phone: +49 351 8822-306 Website: www.xfab.com Fax: +49 351 8822-337

X-FAB is the leading analog/mixed-signal foundry Email: andreas.bruening@zmdi.com group manufacturing silicon wafers for analog-digital Website: www.zmdi.com integrated circuits (mixed-signal ICs). As a specialty foundry for so-called “More than Moore” technologies, Zentrum Mikroelektronik Dresden AG (ZMDI) is a global, X-FAB creates a clear alternative to typical foundry innovation-driven, customer-focused enter­prise services by combining solid, specialized expertise in delivering high-performance analog and mixed signal advanced analog and mixed-signal process technologies semiconductor solutions for over 50 years. The ZMDI with excellent service, a high level of responsiveness difference is that we partner fully through­out the and first-class technical support. It manufactures development of innovative analog and digital power and wafers for automotive, industrial, consumer, medical, sensing technologies, expertly exploring your unique and other applications on advanced modular CMOS and system requirements, solving design challenges and BiCMOS processes with technologies ranging from 1.0 then collaboratively designing and delivering subsystem to 0.13 µm, and special BCD, SOI and MEMS long- and/or architectural solutions. ZMDI’s solutions enable lifetime processes. These technologies are not intended our customers to create the most energy-efficient for digital applications with the smallest possible products for sensors, power management, and lighting. structure sizes, but rather are targeted for analog

40 DATE 14 Event Guide DATE 14 Event Guide Conference & Exhibition March 09–13, 2015 • Grenoble, France Call for PaPers Scope of the Event The 18th DATE conference and exhibition is the main European software design, test and manufacturing of electronic circuits and event bringing together designers and design automation users, systems. It puts strong emphasis on both ICs/SoCs, reconfigurable researchers and vendors, as well as specialists in the hardware and hardware and embedded systems, including embedded software. Structure of the Event The five-day event consists of a conference with plenary invited domains, such as automotive, wireless, telecom and multimedia papers, regular papers, panels, hot-topic sessions, tutorials, applications. The organization of user group meetings, fringe workshops, two special focus days and a track for executives. meetings, a university booth, a PhD forum, vendor presentations The scientific conference is complemented by a commercial and social events offers a wide variety of extra opportunities to exhibition showing the state-of- the-art in design and test meet and exchange information on relevant issues for the design tools, methodologies, IP and design services, reconfigurable and test community. Special space will also be allocated for EU- and other hardware platforms, embedded software, and funded projects to show their results. More details are given on (industrial) design experiences from different application the DATE website (www.date-conference.com).

Areas of Interest Within the scope of the conference, the main areas of interest are: embedded systems, design methodologies, CAD languages, algorithms and tools, testing of electronic circuits and systems, embedded software, applications design and industrial design experiences. Topics of interest include, but are not restricted to:

• System Specification and Modeling • Physical Design and Verification • Test Generation, Simulation and • System Design, Synthesis and • Analogue and Mixed-Signal Circuits and Diagnosis Optimization Systems • Test for Mixed-Signal, Analog, RF, MEMS • Simulation and Validation • Interconnect, EMC, EMD and Packaging • Test Access, Design-for-Test, Test • Design of Low Power Systems Modeling Compression, System Test • Temperature-Aware Design • Multiprocessor System-on-Chip and • On-Line Testing and Fault Tolerance • Power Estimation and Optimization Computing Systems • Real-time, Networked and Dependable • Temperature Modeling and Management • Communication, Consumer and Systems • Emerging Technologies, Systems and Multimedia Systems • Compilers and Code Generation for Applications • Transportation Systems Embedded Systems • Formal Methods and Verification • Medical and Healthcare Systems • Software-centric System Design • Network on Chip • Energy Generation, Recovery and Exploration • Architectural and Microarchitectural Management Systems • Model-based Design and Verification for Design • Secure, Dependable and Adaptive Embedded Systems • Architectural and High-Level Synthesis Systems • Embedded Software Architectures and • Reconfigurable Computing • Test for Defects, Variability, and Principles • Logic and Technology Dependent Reliability • Software for MPSoC, Multi/many-core Synthesis for Deep-Submicron Circuits and GPU-based Systems

Submission of Papers All papers have to be submitted electronically by Sunday, September 14, 2014 via: www.date-conference.com Papers can be submitted either for standard oral presentation or for interactive presentation. The Programme Committee also encourages proposal submissions for Special Sessions, Tutorials and Friday Workshops as well as submissions for the Special Days on “Designing Electronics for the Internet of Things” and “Designing Electronics for Medical Applications” Event Secretariat Chairs c/o K.I.T. Group GmbH Dresden General Chair: Wolfgang Nebel Muenzgasse 2 OFFIS, Oldenburg, Germany 01067 Dresden, Germany [email protected] Phone: +49 351 4967 541 Programme Chair: David Atienza Fax: +49 351 4956 116 EPFL, Lausanne, Switzerland Email: [email protected] [email protected]