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Dear Muneda Friends & Users, Schematic Porting Between Improve Design Performance & Yield Program-Announcement MUGM 2011 MunEDA User Group Meeting 2011 – Nov 24th & 25th Munich Dear MunEDA Friends & Users, We are pleased to announce the program for our next MunEDA User Group Meeting. MUGM 2011 will take place on November 24th &25th (Thu/Fri), 2011 at Westin Grand Munich, Germany. The goal of the event is an intensive exchange of knowledge by experienced industrial users. MUGM provides an open forum for all technologists interested in MunEDA´s EDA software tools. In addition to other contributions, one main focus of the MunEDA User Group Meeting 2011 is the special topic: Schematic Porting between Different Processes, Assessment & Sizing Flow Date: November 24 & 25 (Thu-Fri), 2011 Location: Westin Grand Munich Arabellastr. 6 81925 Munich - Germany Registration open at: www.muneda.com/registration Selection of Technical & Presentation Topics of MUGM & MTF Past MUGM 2011: & Future Forums: Ò Munich 2011 Ò SPT Schematic Porting Ò Taiwan 2011 Ò Handling Design Contraints & Sizing Rules Ò Seoul 2011 Ò IP Porting & Technology Migration Ò Munich 2010 Ò Yokohama 2010 Ò Design Performance & Specification Analysis Ò Munich 2009 Ò Response Surface Modelling & Model Generation Ò Yokohama 2009 Ò Circuit Design Optimization & Verification Ò Munich 2008 Ò Statistical Circuit Analysis & Optimization Ò Boston 2008 Ò Anaheim 2008 Ò Multi-Testbench Environment & Corner-Based Optimization Ò Taiwan 2007 Ò Worst-Case Distance Analysis & Optimization Ò Munich 2007 Ò Design Shrink & Nano-scale Circuit optimization Ò Munich 2006 Ò Industrial Design Cases Ò Erfurt 2004 Ò http://www.muneda.com/MUGM Ò and many more topics … MUGM 2011 Co-located Event MUGM 2011 (by special personal invitation only): (open for all audience): Silicon Saxony & Grenoble MunEDA User Group Meeting 2011 Semi Cluster Workshop 24-25 November 2011 23-24 November 2011 • Thu, Nov 24, 2011 - 10:00-18:00 • Onsite Welcome • Wed, Nov 23, 2011 - 13:30-18:00 • 3 Technical Sessions (D1.1, D1.2, D1.3) Registration & Technical Sessions • Evening Social Event Evening Social Event • Fri, Nov 25, 2011 - 9:45-17:45 • Thu, Nov 24, 2011 - 8:30-11:00 • 4 Technical Sessions (D2.1, D2.2, D2.3, D2.4) Workshop Round Table • Discussion, Hot Topic & Feedback Session Location: Westin Grand Hotel Munich Location: Westin Grand Hotel Munich www.westingrandmunich.com www.westingrandmunich.com In case of interest please contact Silicon Saxony If interested please visit MunEDA website [email protected] www.muneda.com/mugm Participation in MUGM 2011 is free but registering and reserving accommodations early are highly recommended as conference seats are limited. Please access www.muneda.com/User-Group-Meetings_Europe-2011_Accommodation © Copyright by MunEDA GmbH - All rights reserved. Product information is subject to change without notice. All trademarks and registered trademarks are property of their respective owners. Improve Design Performance & Yield Program Announcement - MUGM 2011 in Munich Thursday, 24th Nov Friday, 25th Nov Session D2.1 - 09:00 - 10:40 Co-located Event: MunEDA R&D Roadmap 08:30 09:00 F. Schenkel, VP Research & Development, 09:25 MunEDA GmbH, Germany Silicon Saxony & Grenoble STARC: STARCAD AMS Flow - Next Challenges Semiconductor Cluster 09:25 - K. Tsuboi, 09:50 STARC, Japan For futher information see also Agenda with: http://events.silicon-saxony.de/Details/eid/MjQx 09:50 ON Semi.: Methodologies for Mismatch Sizing and Corner Verification for Automotive Applications with WiCkeD (SMAC) Workshop Round Table 10:15 J. Daniels, ON Semiconductor, Belgium 11:00 (by special invitation only) 10:15 TU-Dresden/Globalfoundries: IP Porting and Resizing for High-Speed NoC 10:00 10:40 MUGM Registration & Welcome Coffee D. Walter, S. Höppner, R. Schüffny, 11:00 TU Dresden, Germany Session D1.1 - 11:00 - 12:30 Session D2.2 - 11:15 - 12:30 Welcome & Whats new MunEDA: SPT Special Session - Schematic 11:00 A. Ripp, VP Sales & Marketing, 11:15 Porting (Tool Presentation) 11:15 MunEDA GmbH, Germany 11:40 M. Pronath, VP Products & Solutions, MunEDA GmbH 11:15 IPGEN: Introduction - IC Design Acceleration 11:40 MunEDA: SPT Special Session - Schematic using 1Stone® Porting (Tool Demonstration) 11:30 H. Bothe, IPGEN, Germany 12:00 C. Roma, MunEDA GmbH, Germany 11:30 STM: Reducing Mismatch Impact by means of 12:00 MunEDA: Trends and Adoption WiCkeD use- Proper Biasing in Fully Differential CMOS Structures models for Special Tasks 12:00 A. Capasso, A. Colaci, STMicroelectronics, Italy 12:15 G. Strube, MunEDA GmbH, Germany 12:00 Silicon Saxony - Network Thinking - Growing 12:15 IMMS: Schematic Porting with Symbol Adaption Together and Initial Sizing as Pre-Process for WiCkeD 12:30 A. Brüning, Chairman Silicon Saxony Workgroup 12:30 Optimizations IC Design, ZMDI AG, Germany V. Boos, J. Nowak, IMMS GmbH, Germany Session D1.2 - 14:00 - 15:30 Session D2.3 - 14:00 - 15:30 14:00 What´s new in MunEDA WiCkeD 6.4 (Tool Demo) 14:00 Hynix: Design Optimization for Sensing Circuit M. Pronath, VP Products & Solutions, of Resistive Memory 14:30 MunEDA GmbH, Germany 14:25 B. Oh, Hynix Semiconductor, Korea 14:30 STMicroelectronics: AMS Design Flow and 14:25 Altera: Circuit Optimization with WiCkeD Standardization of Analog Design Intents design tools 15:00 P. Daglio, E. Raciti, STMicroelectronics, Italy 14:50 JJ Lew, Altera Corporation, Malaysia 15:00 Tohoku University: 14:50 TU-Dresden: Design Flow Integration of the Linearized Analog Design Optimization with gm/Id Lookup Operating Point Method for Fast Voltage Range Estimation 15:30 Table Method and WiCkeD 15:15 with WiCkeD (SyEnA), S. Höppner, S. Henker, J. S. Masui, Görner, R. Schüffny, TU Dresden, Germany Tohoku University, 15:15 STMicroelectronics : Optimization of a Japan 15:40 2.133GHz level shifter in 28nm (with WiCkeD) N. Seller, STMicroelectronics, France Session D1.3 - 16:15 - 18:00 Session D2.4 - 16:10 - 17:45 Toshiba: PLL Loop optimization by WiCkeD Infineon: Parameter Calibration and Cascaded 16:15 M. Kaneko, 16:10 Simulations 16:45 Toshiba Semiconductor Corp., Japan 16:35 R. Neubert, P. Rotter, Infineon Technologies, Germany 16:45 SyEnA: Synthesis based design of analog 16:35 University Rome/STM: Surrogate models for the analog circuit integrated circuits simulation based on a machine learning approach (Manon) 17:15 A. Graupner, ZMDI AG, Germany 17:00 A. Ciccazzo, C. Vicari, STM, V. Latorre, S. Ludici, University of Rome 17:15 TSMC: TSMC AMS Reference Flow & MunEDA 17:00 Survey & Hot Topic Session WiCkeD M. Pronath, VP Products & Solutions, 17:45 S. Chen, TSMC, Taiwan 17:30 MunEDA GmbH, Germany Hynix: Analysis Method for The Parasitic RC 17:30 Wrap-up (MUGM & Discussion) 17:45 Variation Problem by WiCkeD A. Ripp, VP Sales & Marketing, 18.00 S. Lee, 17:45 MunEDA GmbH, Germany Hynix Semiconductor, Korea © Copyright by MunEDA GmbH - All rights reserved. Product information is subject to change without notice. All trademarks and registered trademarks are property of their respective owners..
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