Hardware Implementation of Reversible Logic Gates in VHDL by Dibya Gautam Submitted in Partial Fulfillment of the Requirements F

Hardware implementation of Reversible Logic Gates in VHDL

Dibya Gautam

Submitted in Partial Fulfillment of the

Requirements For the Degree of

Master of Science

in the

Electrical and Computer Engineering

Program

YOUNGSTOWN STATE UNIVERSITY

August, 2020

Hardware implementation of Reversible Gates in VHDL

Dibya Gautam

I hereby release this thesis to the public. I understand that this thesis will be made available from the OhioLINK ETD Center and the Maag Library Circulation Desk for public access. I also authorize the University or other individuals to make copies of this thesis as needed for scholarly research.

Signature:

Dibya Gautam, Student Date

Approvals:

Dr. Frank X. Li, Thesis Advisor Date

Dr. Faramarz Mossayebi, Committee Member Date

Edward Burden, Committee Member Date

Dr. Salvatore A. Sanders, Dean of Graduate Studies Date

ABSTRACT

This research aims at hardware implementation of the reversible logic gate models and reversible logic circuit in VHDL. The application of the research pertains to the field of mathematics and cybersecurity. Furthermore, this research discusses the possibilities of changing the traditional digital logic gates, which allow the information to flow only in one direction, and successfully implementing a reverse information flow in hardware.

Reversible logic gates are designed in such a way that they deduce information based on the given state of inputs and outputs. VHDL codes and simulations for reversible logic gates are introduced in this study. After developing reversible logic gates, a reversible half adder digital circuit was constructed. This implementation can be very useful for designing other larger digital circuits in the near future as it presents a new model of reversibility. To better understand the necessity of internal core architecture while designing the system, a performance analysis of the reversible half adder circuit is given.

It discusses all the steps introduced inside the reversible digital architecture.

Based on the simulation results, we can conclude that reversible logic gates successfully deduce information. Thus, the hardware implementation of an algorithm written in Python (high-level language) to a VHDL (low-level language) was successful.

However, reversible half adder circuit simulation shows more information is needed for the reversible logic gates to become a feasible method aimed at designing complex circuits.

iii

ACKNOWLEDGEMENTS

I would like to express my sincere gratitude to my advisor Prof. Dr. Li for the constant guidance throughout my study and related research. To my mentor Patrick

Bollinger, I express my deepest appreciation for always giving me insights to solve the challenges faced during this research. I am also very grateful to my thesis committee members, Dr. Faramarz Mossayebi and Professor Edward Burden for their valuable suggestions and assistance. I would also like to thank the rest of the faculty of the Electrical and Computer Engineering department for their teachings and support which certainly helped me to excel in this phase of my life.

I would also take this opportunity to heartily thank my beloved father Arjun

Gautam and mother Reetu Gautam for their immense love and support. I am extremely grateful to my dearest friend Kapila Ghimire for always encouraging me and reviewing my paper as many times as needed. I would also like to thank all my friends for their constant support and inspiration.

Lastly, I would like to thank my life partner, Samy. I could not have accomplished in this endeavor without his constant motivation.

TABLE OF CONTENTS

ABSTRACT ...... iii TABLE OF CONTENTS ...... v LIST OF FIGURES ...... vii LIST OF TABLES ...... viii LIST OF ABBREVIATIONS ...... ix CHAPTER I ...... 1 INTRODUCTION ...... 1 1.1 Motivation and Background ...... 1 1.2 Purpose...... 2 1.3 Objectives ...... 2 1.4 Organization ...... 2 CHAPTER II ...... 3 LITERATURE REVIEW ...... 3 2.1 VHDL …Python…… ...... 3 2.1.1 Python/Sequential programming ...... 3 2.1.2 VHDL as programmatic representation of Hardware ...... 4 2.1.3 Application specific Integrated circuit (ASIC) ...... 4 2.2 Logic Gates and Digital circuits ...... 5 2.2.1 Logic Gates ...... 5 2.2.2 Digital Circuits ...... 7 2.3 Reversible Logic Gates ...... 8 CHAPTER III ...... 10 Hardware Design and Implementation of Reversible Logic gates ...... 10 3.1 Hardware Design of Reversible Logic Gates ...... 10 3.1.2 Reversible AND Gate ...... 11 3.1.2 Reversible OR Gate ...... 19 3.1.3 Reversible XOR Gate ...... 22 3.2 Reversible Digital Circuits ...... 26 3.2.1 Hardware implementation of Reversible Half Adder...... 27 3.2.1.1 Resolver ...... 28 CHAPTER IV: RESULTS AND DISCUSSIONS...... 34 4.1 Consideration of Reversible logic Gates model ...... 34 4.1.1 Bi-directional approach ...... 34 4.1.2 State table approach ...... 35

4.2 Analysis of Reversible Half adder ...... 37 4.2.1 Adding Resolvers ...... 37 4.2.2 Error tracker and Multiplexer ...... 37 4.2.2 Clocks and reset ...... 38 4.2.2.1 One clock, no reset...... 39 4.2.2.2 One clock, with reset...... 39 4.2.2.3 Two clocks, no reset ...... 40 4.2.2.4 Two clocks, with reset ...... 41 4.2.2.5 Comparison of all the above cases of adding clocks and reset ...... 42 CHAPTER V ...... 43 CONCLUSION ...... 43 References ...... 44 APPENDICES: ...... 45 APPENDICE 1: ACCESS VHDL CODES ...... 45 APPENDICE 2: Comparison Table in detail ...... 45 APPENDICE 2: RTL VIEW ...... 47

LIST OF FIGURES

Figure 1: AND Gate Graphical Representation ...... 5 Figure 2: OR Gate Graphical Representation ...... 6 Figure 3: XOR Gate Graphical Representation ...... 7 Figure 4: Half-Adder Digital Circuit ...... 8 Figure 5: Entity diagram of Reversible Logic Gate ...... 10 Figure 6: Block diagram of the working process in Reversible Logic Gate ...... 15 Figure 7: Code Snippet of Reversible AND Gate ...... 16 Figure 8: Testbench snippet of Reversible AND ...... 18 Figure 9: Code Snippet for Reversible OR Gate ...... 21 Figure 10: Testbench Snippet of Reversible OR Gate ...... 22 Figure 11: Code Snippet for Reversible XOR Gate...... 25 Figure 12: Testbench snippet of Reversible XOR ...... 26 Figure 13: Internal architecture of half-adder ...... 28 Figure 14: Code snippet of Resolver ...... 30 Figure 15: Code snippet of Reversible Half-Adder ...... 31 Figure 16: Testbench Snippet of Reversible Half-Adder ...... 32 Figure 17 : Bi-directional Reversible logic chip design ...... 35 Figure 18 : Simulation of Reversible AND Gate ...... 35 Figure 19 : Simulation of Reversible OR Gate ...... 36 Figure 20 : Simulation of Reversible XOR Gate ...... 36 Figure 21 : Simulation of Reversible Half Adder with one clock with no reset ...... 39 Figure 22: Simulation of Reversible Half Adder with one clock and reset ...... 40 Figure 23: Simulation of Reversible Half Adder with two clocks with no reset ...... 41 Figure 24: Simulation for Reversible Half Adder ...... 41 Figure 25: RTL diagram for Reversible AND Gate ...... 47 Figure 26: RTL diagram for Reversible OR Gate ...... 47 Figure 27: RTL diagram for Reversible XOR Gate ...... 48 Figure 28:RTL diagram for Reversible Half Adder ...... 48

vii

LIST OF TABLES

Table 1: AND Gate Truth Table ...... 6 Table 2: OR Gate Truth Table ...... 6 Table 3: XOR Gate Truth Table ...... 7 Table 4: Half Adder Truth Table ...... 8 Table 5: External inputs to map deduce state table for reversible AND gate ...... 13 Table 6:State map to predict output table for reversible AND gate ...... 14 Table 7: External inputs to state map table for reversible OR gate ...... 19 Table 8: current state to predicted output map table for reversible OR gate ...... 20 Table 9: External inputs to State mapping table of Reversible XOR Gate ...... 23 Table 10: External inputs to State mapping table of Reversible XOR Gate ...... 24 Table 11: Resolver ...... 29 Table 12: Comparison Table for four different case ...... 42 Table 13: Detailed Comparison table for reversible half adder ...... 45

viii

LIST OF ABBREVIATIONS

ASIC ...... Application Specific Integrated Circuit I/O ...... Inputs/Outputs VHDL ...... VHSIC Hardware Description Language HDL ...... Hardware Description Language VHSIC ...... Very High-Speed Integrated Circuit ALU ...... Airthmetic Logic Unit

CHAPTER I

INTRODUCTION

1.1 Motivation and Background

The rapidly developing software industry is facing complexities because of its model, which is why faster hardware is going to be in big demand in near future. The modern embedded computing industry needs to be more specific for the faster productivity of the built-in system. This thesis presents a design for hardware implementation of reversible logic gates, which are built in as Application Specific Integrated Circuit (ASIC) system. ASIC designs are used for reduced power consumption and faster output generation compared to the general-purpose processor [1].

This thesis is based on the previous master’s thesis [2] where, the author presented unique approach of factorizing prime numbers using reversible logic gates. The author designed reversible logic gates, which (unlike existing reversible logic gates such as Fredkin, Toffoli [3]) carries the message of reversibility by deducing the information based on given I/O, in python. In aforementioned thesis the reversible logic gates are python based. Whereas, in this thesis they are modeled in VHSIC Hardware Descriptive

Language (VHDL) for more productive reversible system. Information about reversible logic gates is given more in depth in chapter III.

1.2 Purpose

The purpose of this thesis is the hardware implementation of python designed reversible logic gates using VHDL. The algorithm represents the basic reversible gates that are analyzed, simulated, and then combined to develop a half adder circuit. This approach investigates the process of ASIC hardware design and discusses its advantages over general-purpose processor.

1.3 Objectives

The objectives of this thesis are as follows.

• Develop reversible logic gates using VHDL

• Develop Test benches for reversible logic gates

• Successfully simulate designed reversible logic gates

• Develop a half adder circuit by assembling the reversible logic gates

1.4 Organization

This thesis is organized into 5 chapters. Chapter II discusses more in depth about this research. Chapter III describes the design of this research. Chapter IV details the results and discussions of this research. Chapter V summarizes the content of this work and concludes the research.

CHAPTER II

LITERATURE REVIEW

2.1 VHDL versus Python

This section talks about why there is a need for Hardware Descriptive Language

(HDL) for the digital system design, and how traditional sequential programming is not suitable for hardware implementation. In addition, it also illustrates how ASIC implementation is compared to the general-purpose processor.

2.1.1 Python/Sequential programming

Python is a sequential programming language, which means the codes executes step by step, one at a time, to give the correct results. Python programs are designed for the general-purpose processor, to perform a set of instructions in a sequential manner. [4] In single core processor, a sequential program shares a single memory that means each thread of process shares the same portion of memory as the parent process. However, to run each thread of the process in a multi-core processor, the program needs to be modified which is only possible when it uses the python multiprocessing library. The process of taking a sequential program and breaking it into different processes is known as parallelization. It is complex to analyze data dependencies in a sequential program, and therefore, is difficult to parallelize efficiently. [5] The primary attributes of hardware is time and concurrencies, sequential programming is not able to provide any of those.

Concurrency and Parallelization have their own meaning in the world of computing. All the processes, inside the program, needs to execute at the same time for parallelization. Whereas, the concurrent process is interrupting in nature which means any process can be started and executed within the time. Therefore, HDL is the only

3 programming language designed to provide all necessary syntaxes and semantics explicitly for digital hardware design. [6]

2.1.2 VHDL as programmatic representation of Hardware

When it comes to hardware design implementation, HDLs such as Verilog and

VHDL are used for its design methodologies. Both languages can describe the complex functionality of digital system design. However, in this thesis VHDL has been used to for all the hardware modeling. VHDL is considered to be one of the appropriate languages to develop real-world applications. Traditional sequential languages, like Python, are not typically used for digital hardware modeling as they are primarily designed for general- purpose processors (which execute one operation at a time). VHDL is concurrent in itself which allows improvements in performance, scalability, and fault tolerance. Unlike sequential programs where operation needs to be executed one at a time, VHDL can execute the program concurrently allowing each operation an explicit amount of time. [6]

2.1.3 Application specific Integrated circuit (ASIC)

ASIC is basically a chip, designed for a particular purpose in a specific application.

The main reason for considering ASIC design is to minimize power consumption and hardware area. ASICs are 500 times more energy efficient than general-purpose processors

[1]. Reversible logic gates designed here are also an ASIC compatible implementation, as their only purpose is to deduce information at a given time based on the given inputs and outputs.

2.2 Logic Gates and Digital circuits

In the binary world of 0’s and 1’s; arithmetic operations like adding, and multiplying are performed by logic gates. These logic gates are, also, then combined to perform more complex multi-operations.

2.2.1 Logic Gates

Logic gates are basic building blocks to build an electronic system using binary functions. There are different types of logic gates but for this research, it will be more focused on AND, OR, and XOR. The review of the fundamental basic logic gates operations aids to better understand the thesis (as the core part of the thesis is based on it).

Logic gates can be represented as a truth table, in which it shows all the given binary inputs and produces a single binary output. Below are graphical representation and truth tables for the three logic gates that we will investigate more in this thesis. Among the various standards of graphical representation for logic gates, in this thesis will utilize IEEE

Std 91/91a-1991.

Figure 1: AND Gate Graphical Representation

Table 1: AND Gate Truth Table

INPUTS OUTPUT

A B A AND B

0 0 0

0 1 0

1 0 0

1 1 1

Figure 2: OR Gate Graphical Representation

Table 2: OR Gate Truth Table

INPUTS OUTPUT

A B A OR B

0 0 0

0 1 1

1 0 1

1 1 1

Figure 3: XOR Gate Graphical Representation

Table 3: XOR Gate Truth Table

INPUTS OUTPUT

A B A XOR B

0 0 0

0 1 1

1 0 1

1 1 0

2.2.2 Digital Circuits

Logic gates are combined to build different types of digital circuits. There can be various ways of using the same logic gates in the circuit to give different results. Binary

multiplication is typically implemented by repeated operations of addition. The circuit used

for performing such multiplication is sub-circuits used for addition.

The half adder is the foundation of other complex digital circuits. It consists of 2

inputs: Input A and Input B; and 2 outputs: Sum and Carry. Once you have the half adder

designed, other fully featured digital circuits like adders and multipliers can be easily built.

The relationship between the inputs of the half adder and its outputs is shown in the truth table 4. In addition, there is a circuit diagram to show how the logic gates discussed previously create this full adder.

Table 4: Half Adder Truth Table

INPUT OUTPUT

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Figure 4: Half-Adder Digital Circuit

2.3 Reversible Logic Gates

The irreversibility in compact computing circuits is one of the reasons for the energy dissipation in terms of KTlog2 (where K is Boltzmann’ constant and T is the temperature of the system) [7]. Later, in 1982 reversibility was defined as being both logically reversible and physically reversible. Since then, researchers have been investigating any possible ways to come up with a novel technique for the reversible hardware model. Later, two new logic gates named Toffoli and Fredkin gate (accepted as a universal reversible logic gate) were introduced in the field of reversible computing. [8]

These reversible logic gates are further used (many times) in different quantum research,

8 which uses them for energy efficient computing operations. [9] With emerging technology, there has been a lot of discovery where reversible logic gates are used to create new hardware models like ALU. Such models create zero power dissipation and zero information loss. [10]

However, this thesis introduces unique reversible logic gates, which deduces information based on given I/O arguments. These designed reversible logic gates have possible use in the field of mathematics and cybersecurity to find any missing information in the system. For instance, previous work’s [2] author tried to test the strength of the system with reversible logic gates for the cryptography algorithms. Another application with further research could be creating a digital gene system by using reversible logic gates

(if the conversion of the biological system into a digital logic system is possible).

CHAPTER III

Hardware Design and Implementation of Reversible Logic gates

3.1 Hardware Design of Reversible Logic Gates

As clarified before, the reversible gates designed here are the logic gates that define the meaning of reversibility as the ability to deduce what the inputs and outputs should be based on a given state of inputs and outputs. The designed reversible logic gates are faster and energy efficient compared to the general-purpose processors. However, by no means, this is comparable to other reversible logic gates used for quantum research which is only focused on conserving energy rather than deducing information. Designed gates are ASIC in nature as the sole purpose of the system is only to deduce information.

This section discusses how the reversible logic gates are designed and implemented in VHDL. Algorithms are created for reversible logic gates and they are assembled to create half adder. Furthermore, it also talks about how reversible logic gates/circuits are different than the traditional logic gates.

Figure 5: Entity diagram of Reversible Logic Gate

Figure 5 depicts the entity block representation of all reversible logic gates designed and discussed in this work. As it is clear from the figure, it has three primary inputs and three outputs where, EX_A, EX_B, and EX_C are external input arguments, and PRE_A,

PRE_B, and PRE_C are predicted outputs based on given inputs at a given time. The clock and resets are used to make the system synchronous and controllable. In particular, the clock in the reversible gate only operates when given input clock cycle transitions from low to high. Whereas, reset in the system returns the system into the beginning stage, which results in undefined predictions with error zero. Unlike the traditional logic gates, reversible gates need to have error tracked for being fully designed. Therefore, every reversible logic gate has an error state called E1 (where all the outputs are unknown) and which is determined by the output Error signal (either logic “1” or logic “0”).

3.1.2 Reversible AND Gate

The traditional AND gate, as we know, has two inputs and a single output. For example, if the output of an AND gate is 1 and two inputs are unknown (X), the only possible inputs that we can deduce are 1 and 1; resulting in a fully defined state of the AND gate.

In previous work [2], table 5 is represented in the traditional state table format in which deduced states, inputs, and outputs are a function of given states, inputs, and outputs.

However, in this thesis, the state tables are reformed in such a way that they are divided into two different processes: inputs mapping to deduce states and sate mapping to predict the output. Obviously, with this approach, it eliminates all the redundant states presented in previous work.

Table 5 given below shows how 27 different external inputs are mapped to the next state. There are only 11 different states defined for reversible AND gate, including one error state (whereas the previous research had 27 different states, because of no state mapping process).

Table 5: External inputs to map deduce state table for reversible AND gate

EXTERNAL INPUTS Next_ state # Ex_A Ex_B Ex_C

X X X S1 X X 0 S2 X X 1 S3 X 0 X S4 X 0 0 S4 X 0 1 E1 X 1 X S5 X 1 0 S6 X 1 1 S3 0 X X S7 0 X 0 S7 0 X 1 E1 0 0 X S8 0 0 0 S8 0 0 1 E1 0 1 X S6 0 1 0 S6 0 1 1 E1 1 X X S9 1 X 0 S10 1 X 1 S3 1 0 X S10 1 0 0 S10 1 0 1 E1 1 1 X S3 1 1 0 E1 1 1 1 S3

The table shows how the current state is mapped to predicted outputs and, also, gives the status of the error output. The idea of reformatting the table was to get rid of all the redundant states and make the table look explicitly clear to understand.

Table 6:State map to predict output table for reversible AND gate

Current_state Predicted Output Error # Pre_A Pre_B Pre_C Output

0 S1 X X X S2 X X 0 0 S3 1 1 1 0

0 S4 X 0 0 S5 X 1 X 0 0 S6 0 1 0 S7 0 X 0 0

S8 0 0 0 0

S9 1 X X 0

S10 1 0 0 0

E1 X X X 1

Table 5 & 6 illustrates the working process of the state machine, with which we create an algorithm to hardware implement the reversible AND gate. VHDL code of each gate is comprised of three different processes; the first process has a clock and a reset inside the sensitivity list, the second process has a current state inside the sensitivity list, and the third process has external I/O arguments. Every signal inside the sensitivity list is an assertion that the signal controlled by the process only changes when one of the signals is changed from the sensitivity list.

Now, based on the given information we can start building our reversible logic gates. The hardware implementation language used to design and test every reversible logic gate is VHDL whereas before it was only designed using python. VHDL codes are written using Xilinx Vivado software. The software is very useful as it allows to write a test bench code for simulation and gives RTL schematic diagram. The code is written in such a way that it provides every information, explicitly, to understand the functioning of the reversible logic gates.

Furthermore, to have the clear insight into the working process of VHDL code, a block diagram is presented below. It is clear from the figure that, there are three different processes, where process A helps to determine the next state from given external inputs.

Then, in the next process state only changes when it gets a rising edge clock and turns into state 1 when reset is high. In process C, it is able to deduce information based on the current state.

Figure 6: Block diagram of the working process in Reversible Logic Gate

A snippet of VHDL code is given below, to show how the reversible AND gate was implemented and tested successfully with the help of a test bench.

Figure 7: Code Snippet of Reversible AND Gate

From the snippet of reversible AND gate, we can see that input argument: ex_a, ex_b, and ex_c, are declared as inputs inside the entity. Here, ex_a, ex_b are the inputs to the AND gate and ex_c is the output of the AND gate. Whereas, pre_A,pre_B, and pre_C are declared as outputs inside the entity. To ensure the system is synchronous, clock and reset are given as an input. The code is written in such a way that, based on the given external input arguments, it predicts outputs of the gate.

Clearly, the architecture of the gate is defined as 10 different states and one error state (to keep the track of an erroneous state in order to operate fully). The code will match the three input arguments to a given state, in table 5, and returns the new state with the predicted outputs of the AND gate. For the core functionality of the circuit, it depends on three different processes (as shown in figure 6), in the code, we will find all three processes as from code snippet figure 7, first we see, process with the clock and reset are given inside the sensitivity list to make the system synchronous when the clock signal is changed from low to high. This means when the circuit is implemented, all the assigned values are saved in a clock register which is triggered by a rising edge of the clock signal within the scope of synchronization. Another process, we see, current_state inside the sensitivity list which changes for every new predicted output. The last process shows the changes in the external inputs, which are inside the sensitivity list, determine the next state. In the code, the error signal is declared as an output which results in ‘1’ only if there is an error.

Now that we have an implementation of the reversible AND gate, the OR gate, and XOR gate will follow the same route.

Figure 8: Testbench snippet of Reversible AND

3.1.2 Reversible OR Gate

The algorithm used for designing the reversible OR gate followed similar steps as used for the reversible AND gate. However, a state table for the reversible OR gate is different.

Table 7: External inputs to state map table for reversible OR gate

External Inputs Next_ state# Ex_A Ex_B Ex_C X X X S1 X X 0 S2 X X 1 S3 X 0 X S4 X 0 0 S2 X 0 1 S5 X 1 X S6 X 1 0 E1 X 1 1 S6 0 X X S7 0 X 0 S2 0 X 1 S8 0 0 X S2 0 0 0 S2 0 0 1 E1 0 1 X S8 0 1 0 E1 0 1 1 S8 1 X X S9 1 X 0 E1 1 X 1 S9 1 0 X S5 1 0 0 E1 1 0 1 S5 1 1 X S10 1 1 0 E1 1 1 1 S10

Table 8: current state to predicted output map table for reversible OR gate

Current_ Predicted O/P Error state # Pre_A Pre_B Pre_C O/P

S1 X X X 0

S2 0 0 0 0

0 S3 X X 1

S4 X 0 X 0

S5 1 0 1 0

S6 X 1 1 0

S7 0 X X 0

S8 0 1 1 0 0 S9 1 X 1 S10 1 1 1 0

E1 X X X 1

The states defined in the table are used for implementing the reversible OR gate in

VHDL. A snippet of Reversible OR gate’s code is shown below which gives a brief overview of the gate’s implementation. This follows the exact same steps as Reversible

AND gate, the only difference you may see is that predicted outputs are in different states

(as shown in the simulations figure 19 of Reversible OR gate).

Figure 9: Code Snippet for Reversible OR Gate

Figure 10: Testbench Snippet of Reversible OR Gate

3.1.3 Reversible XOR Gate

In a similar way, the reversible XOR gate also follows the same process as other designed logic gates. The state tables are very clear in allowing you to relate different states and input/outputs.

Table 9: External inputs to State mapping table of Reversible XOR Gate

External Inputs Next_ State # Ex_A Ex_B Ex_C

X X X S1 X X 0 S2 X X 1 S3 X 0 X S4 X 0 0 S5 X 0 1 S6 X 1 X S7 X 1 0 S8 X 1 1 S9 0 X X S10 0 X 0 S5 0 X 1 S9 0 0 X S5 0 0 0 S5 0 0 1 E1 0 1 X S9 0 1 0 E1 0 1 1 S9 1 X X S11 1 X 0 S8 1 X 1 S6 1 0 X S6 1 0 0 E1 1 0 1 S6 1 1 X S8 1 1 0 S8 1 1 1 E1

Table 10: External inputs to State mapping table of Reversible XOR Gate

Current_ Predicted Outputs Error State # Output Pre_A Pre_B Pre_C S1 X X X 0 0 S2 X X 0 S3 X X 1 0

S4 X 0 X 0

S5 0 0 0 0

S6 1 0 1 0

S7 X 1 X 0

S8 1 1 0 0

S9 0 1 1 0 0 S10 0 X X 0 S11 1 X X 1 E1 X X X

Similar to the previous two gates, the state table (9&10) representation can be written programmatically. The code snippet below shows the XOR gate implementation.

Figure 11: Code Snippet for Reversible XOR Gate

The following snippet (figure 12) is part of the test bench code. Unlike other reversible logic gates, we tried a new way of reducing the steps of the code. Input arguments of the gate were stimulated by individual processes; where each of these processes generates bits when the clock is running and turns X, 0, 1 according to different assigned time slots. This way, the code was much shorter compared to previous codes for

AND and OR gates.

Figure 12: Testbench snippet of Reversible XOR

3.2 Reversible Digital Circuits

In this section, with the help of fully defined reversible logic gates, a digital circuit is developed. It also contains further information about the complete design process of making a reversible digital circuit. A reversible half adder circuit is built as testing a simple digital circuit would be more effective than to design a complex digital circuit.

Implementation of reversible half adder gives the possibilities to design the complex reversible digital circuits, such as reversible full adder and multiplier, with relative ease.

3.2.1 Hardware implementation of Reversible Half Adder

After successful hardware implementation of reversible logic gates, we move forward with the reversible half adder circuit. Half adder is a basic digital circuit that we can build using the reversible logic gates. Once, we have fully defined reversible half adder we can easily implement the full adder by just combining two of the reversible half adders.

The only difference in half adder and full adder entities is full adder has one extra input of

Carry-In bit which reduces the complexity of the full-adder down to two inputs and two outputs. So, with four input/output arguments the total number of possible I/O combinations is 81. It has fewer I/O combinations if we compare it to reversible full adder which will result in 243 different I/O combination with 5 I/O arguments. The formula for calculating the number of possible I/O combinations of reversible half adder circuit is given below. The formula clearly illustrates how the number of I/O combinations will increase based on the number of inputs and outputs identified.

3((�� )+(�� ))

Hardware implementation of reversible half adder digital circuit in VHDL was challenging compared to designing it in python, as many new gates were introduced in the circuit to make the reversible half adder work. This thesis details the information on the hardware implementation of the reversible half-adder. VHDL test bench has been created to verify if the implemented reversible digital circuit is working accordingly or not by the simulation results. In the future, the implementation of complex reversible digital circuits will be much easier with help of fully designed reversible half-adder.

As shown in figure 13, half adder has four primary I/O including one error output.

For creating a reversible half adder, different new components were introduced like

resolver, multiplexer, and OR gate which made the system more complicated. From the figure, it is clear that each internal component has its own error fed to the OR gate (given by Er as an error output).

Figure 13: Internal architecture of half-adder

3.2.1.1 Resolver

At first, we created a newly designed gate called resolver whose function in is to select bits in different possible cases as shown in figure 13. The number of possible input arguments with output and error is shown in table 11. The importance of resolver will be discussed in chapter IV: Result and discussion in detail.

Table 11: Resolver

Input A Input B Output C Error

X X X 0 X 0 0 0

X 1 1 0

0 X 0 0 0 0 0 0 0 1 X 1

1 X 1 0 1 0 X 1

1 1 1 0

Table 11 is then implemented in VHDL for resolver, which serves as one of the components in the reversible half adder.

Figure 14: Code snippet of Resolver

From the code snippet (figure 14), it is clear that there are two inputs: A and B.

With every change in inputs, the output changes when the clock signal transitions to high.

In case if the system needs to start all over again, a reset is provided. At first, we imported the reversible logic gates that were defined in the previous section and Resolver defined above. Next, we created the reversible half-adder by importing reversible AND, XOR, and

Resolver gates. Below is the small portion of the code that was used to create the reversible half-adder.

Figure 15: Code snippet of Reversible Half-Adder It is very clear from the code snippet (figure 15), that there are two Clocks declared inside the entity block of the reversible half adder. The clocks are for the special purpose, which is explained more on the Result and discussion chapter (section 4.2). There are 4 input/output arguments of the traditional half adder, where e_A and e_B are the inputs, and e_sum and e_carry are the outputs. And, there are four outputs of reversible half adder: p_A, p_B, p_Sum, and p_carry. Furthermore, reversible AND, XOR, and Resolver are ported as a component inside the architecture. Similarly, in half adder there is an Error output declared as buffer E9 to keep the track of an erroneous state coming out from every component used to build the reversible half adder.

To verify that the designed circuit works accordingly, test benches are created. The test benches check whether the circuit is functioning as expected. Below is the test bench snippet (figure 16) of the reversible half adder.

Figure 16: Testbench Snippet of Reversible Half-Adder

As shown, different signals are created inside the architecture of the code for port mapping them to the entities of the reversible half adder. From the snippet (figure 16), it is clear that the output is checked without any given inputs only inside the stimulus process.

The link (Appendix I) to the test bench code illustrates there is other separate stimuli

process for each external input. Each stimuli process runs for all the possible combinations with only a few lines of code, instead of writing 81 times for each process. Similar to all reversible logic gates, the simulation of Reversible Half adder (figure 24) verifies all the

81 possible combinations of I/O and deduces information from them.

The link for all the VHDL codes for this thesis is given in the Appendix section.

CHAPTER IV

RESULTS AND DISCUSSIONS

This chapter presents all the observations and results from the hardware implementation of reversible logic circuits. The analysis of information generated by all the designed logic gates and circuits was conducted using the previous thesis [2] as a reference. This thesis focuses more on hardware implementation models and challenges we faced during the implementation.

4.1 Consideration of Reversible logic Gates model

For this thesis, there were two appropriate approaches: the bi-directional approach and state machine approach, to select a model for hardware implementation of the reversible logic gates. This section discusses and analyzes both of the approaches, and shows the successful simulation results of the selected model for hardware implementation of reversible logic Gates.

4.1.1 Bi-directional approach

In this approach, I/O pin are given either as an input or as an output for operation of the system. If we consider bi-directional signals, it is obvious that the system is more efficient. On the other hand, I/O pins considered to be as an input or as an output can be challenging to handle. Likewise, the system designed using bi-directional approach leads to asynchronous state machine, which is difficult to use for reversible logic gates. It needs more research on the bi-directional approach to be considered for designing reversible logic gates. Therefore, the state machine approach seems to be a good choice for this thesis, as it allows synchronous circuit design.

Bi-directional Reversible Gate

Figure 17 : Bi-directional Reversible logic chip design

4.1.2 State machine approach

The state tables given in section 3.2, is an appropriate method for the hardware design of reversible logic gates. As discussed earlier, this approach leads to synchronous state machines, where the change of the state depends on I/O arguments and the clock signals. The results obtained by implementing an algorithm from using the state table method are shown in the simulations (figure 18, 19 & 20).

Figure 18 : Simulation of Reversible AND Gate

Figure 19 : Simulation of Reversible OR Gate

Figure 20 : Simulation of Reversible XOR Gate

We may notice (from figure 18, 19 & 20), all the signals are on the left side starting from 3 external inputs, 3 predicted outputs followed by the clock and reset signal, Error signal, Boolean signal for stopping the clock, and total clock period. Additionally, all the

27 different possible input/output arguments combination effectively deduce output as intended. The track of an erroneous state is given by an error output signal, which is 1 at every error state (implying that all the predicted outputs turn to X’s).

4.2 Analysis of Reversible Half adder

This section shows how the reversible half adder was constructed and the challenges faced while writing the code. It also discusses the two different clock cycle with reset in order to generate accurate information.

4.2.1 Adding Resolvers

The performance of the reversible half adder circuit is dependent on the resolver. It is necessary to introduce a resolver inside the internal architecture of the reversible half adder (as shown in figure 13) is to select the bit. In the absence of resolvers, the deduction of information was inaccurate because of the conflicting bits. After adding resolver, conflicting bits issue was solved. However, it was noticed that the system was unable to deduce the desired result.

4.2.2 Error tracker and Multiplexer

After fixing the resolving issues of determining bits in the circuit and code, the system was still incomplete without an error tracker. First, in order to make the system fully operating, it needs an erroneous state tracker for which E9 is a buffer error signal

(which is declared in the code of the resolver gate). The system is comprised of various

gates, each gate produces its own error signals which is combined and given as a single buffer output by using an OR gate. The reversible half adder circuit started to operate fully by implementing the buffer output, however it did not deduce information successfully.

Second, after making an error tracking system, we were having some issues with managing an error for deducing the correct information from given input/outputs arguments. To mitigate the issues, multiplexers (driven by an error signal E9) were introduced to the circuit. The VHDL code of half adder circuit elucidates that multiplexer selects the output signal when E9 is 0 and selects X when E9 is 1. After the implementation of the error tracker and multiplexer in the code of the reversible half adder circuit, the code started deducing correct information based on given input/output arguments. However, the results shown by this implementation had some oscillation, and to get rid of the oscillations another solution was created. In the next topic, we will discuss how the oscillations were minimized by introducing two different clocks.

4.2.2 Clocks and reset

Adding resolvers to the system helped in resolving two conflicting bits. However, the system was still incomplete and unable to deduce correct information. In this section, the clock and reset come into play as we try different possible ways to make the system fully operating. It has been noticed from the code snippet (figure 15), that two clock cycles introduced as an entity for the reversible half adder. The purpose of adding two clocks is to give resolver, when given as feedback in the system, extra time for resolving conflicting bits. Here, we present 4 different case scenarios before finalizing two clocks and reset as the selected method for designing reversible half adder.

4.2.2.1 One clock, no reset

The half adder circuit, with one clock and no reset signal, could not properly deduce information. The figure below shows dark green spots that indicate unstable system with glitches. For instance, if you take 2000 ns (figure 21) and observe the outputs, you get different outputs for same inputs. Thus, the information generated by the circuit (figure 22) is inaccurate.

Figure 21 : Simulation of Reversible Half Adder with one clock with no reset

4.2.2.2 One clock with reset

The half adder circuit with one clock and reset signal deduces information more accurately compared to one without reset signal. As we can see from the figure 23, there are still dark green spots but only in some parts but with many glitches. Thus, the information generated by the circuit (figure 22) is also inaccurate.

Figure 22: Simulation of Reversible Half Adder with one clock and reset

4.2.2.3 Two clocks, no reset

The reason for adding two clock cycle in half adder circuit is for the reduction of the glitches produced by the unstable system (due to addition of resolver in feedback of reversible logic gates). It takes some time to resolve for its first input/output arguments.

Thus, the second clock is given to reversible AND gate that allows the gate to resolve conflicting bits. One clock with reset circuit deduces information more accurately compared to one without reset signal. As we may notice from the figure 23 that there are very few glitches, although, the amount of information deduced is heavily incorrect.

Figure 23: Simulation of Reversible Half Adder with two clocks with no reset

4.2.2.4 Two clocks with reset

The reset in the system (figure 24) is high for the first half of the 100ns and low for the second half of the 100ns to see how the system deduces information in every input signal given to it. In this way only we were able to hardware implement the reversible half adder circuit with the successful simulation of the circuit (figure 24).

Figure 24: Simulation for Reversible Half Adder

4.2.2.5 Comparison of all the above cases of adding clocks and reset

In four different cases discussed above, the appropriate result is deduced by the last case when we add two clocks and reset to the system. From the above simulations (figure

21, 22, 23, & 24), we know which case generates more accurate information. Thus, table

13 is created to show the detailed data for determining the correctness of information generated by all four cases (which is given in the appendix section, Table 13).

Table 13 shows that if given external inputs do not match with predicted outputs then the information generated by the reversible half adder is termed as incorrect. For example, if external inputs are X,0,1,1 then the predicted output should be X, X, X, X if not, then the system is generating false value termed as incorrect. Table 12 shows the percentage of the correctness of the system in terms of deducing information (based on the simulations and case scenario table).

Table 12: Comparison Table for four different case

Cases Type of the Case Correctness Percentage

Case 1 One clock, no reset 91.35%

Case 2 One clock with reset 90.12%

Case 3 Two clocks, no reset 91.35%

Case 4 Two clocks 97.53% with reset

CHAPTER V

CONCLUSION

This thesis introduces hardware implementation of novel reversible logic gates in

VHDL from which the information can be deduced at the given time with I/O argument.

The purpose of this thesis is, also, to understand the need for HDLs in the digital system design, and analyze the changes made during the hardware implementation of reversible logic gates. The reversible logic gates designed are based on the ASIC technique. Under which, each logic gate has a specific purpose of deducing information effectively with low power consumption and less area. The goal of designing reversible logic gates is to construct complex reversible digital circuits that can be further applied in the field of mathematics and cybersecurity. However, designed half adder digital circuit needs more analysis to be an appropriate method even though the circuit deduces information accurately. As the number of I/O increases, it gets difficult to hardware implement the reversible circuits. It is very challenging to handle all the I/O at once for deducing the information. Since the amount of information generated gets perplexing, a different method must be developed for designing complex reversible logic circuits. In the future, research should be more focused on the system with no reset to make a completely asynchronous system.

Therefore, from this study, it is observed that all the hardware designed logic gates are unique and specifically designed to deduce information. Additionally, the reversible logic design presented in this thesis holds the future of designing complex reversible circuits with higher efficiency, lower power consumption, and lesser area-utilization compared to a general-purpose processor. 43

References

[1] R. W. Q. M. W. O. A. A. S. B. C. L. S. R. C. K. a. M. H. Hameed, "Understanding Sources of Inefficiency in General-purpose Chips," in Proceedings of the 37th Annual International Symposium on Computer Architecture, 2010. [2] P. Bollinger, "Prime Factorization through reversible logic gates," Youngstown, 2019. [3] R. Garipelly, P. Kiran and A. Kumar, "A Review on Reversible Logic Gates and their Implementation," International Journal of Emerging Technology and Advanced Engineering, vol. 3, no. 3, pp. 417-423, March 2013. [4] G. v. Rossum, "Python tutorial,, Technical Report CS-R9526,," Centrum voor Wiskunde en Informatica (CWI), Amsterdam, May 1995. [5] S. Gill, " “Parallel Programming”," Computer Journal Vol. 1, 1958. [6] P. P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley-IEEE Press, 2006. [7] R. Landauer, "Irreversiblity and Heat Generation in the Computing Process," IBM Journal, 1961. [8] E. F. a. T. Toffoli, "Conservative Logic," International Journal of Theoretical Physics, 1982. [9] H. R. Bhagyalakshmi and M. K. Venkatesha, "An Improved Design of a Multiplier Using Reversible Logic Gates," International Journal of Engineering Science and Technology, vol. 2, no. 8, pp. 3838-3845, 2010. [10] M. P. K. S. a. J. S. K. Kamaraj Arunchalam, ""Design and implementation of areversible logic based *-bit arithmetic and logic unit"," International journal of computer and applications,Vol.36,No.2, 2014. [11] National Institute of Standards and Technology. [12] G. V. Rossum, ""An Introduction to Python for UNIX/C Programmers"," Amesterdam, 1993. [13] B. B., "Introduction to Digital Design with VHDL," in In: Application-Specific Hardware Architecture Design with VHDL. Signals and Communication, Springer, Cham, 2017.

APPENDICES:

APPENDICE 1: ACCESS VHDL CODES

All the codes for this thesis are available in following URL: https://github.com/dgautam03/MyMastersThesis

APPENDICE 2: COMPARISON TABLE IN DETAILS

Table 13: Detailed Comparison table for reversible half adder

Inputs Output Observation E_A E_B E_sum E_carry Case 1 Case 2 Case 3 Case 4 X X X X Correct Correct Correct Correct X X X 0 Correct Correct Correct Correct X X X 1 Correct Correct Correct Correct X X 0 X Correct Correct Incorrect Correct X X 0 0 Incorrect Incorrect Incorrect Incorrect X X 0 1 Correct Correct Correct Correct X X 1 X Incorrect Incorrect Incorrect Incorrect X X 1 0 Correct Correct Correct Correct X X 1 1 Correct Correct Correct Correct X 0 X X Incorrect Correct Correct Correct X 0 X 0 Incorrect Correct Correct Correct X 0 X 1 Correct Correct Correct Correct X 0 0 X Correct Correct Correct Correct X 0 0 0 Correct Correct Correct Correct X 0 0 1 Correct Correct Correct Correct X 0 1 X Correct Correct Correct Correct X 0 1 0 Correct Correct Correct Correct X 0 1 1 Correct Correct Correct Correct X 1 X X Incorrect Correct Incorrect Correct X 1 X 0 Correct Correct Correct Correct X 1 X 1 Correct Correct Correct Correct X 1 0 X Correct Correct Correct Correct X 1 0 0 Correct Incorrect Correct Correct X 1 0 1 Correct Correct Correct Correct X 1 1 X Correct Correct Correct Correct X 1 1 0 Correct Correct Correct Correct X 1 1 1 Correct Incorrect Correct Correct

0 X X X Incorrect Correct Incorrect Correct 0 X X 0 Incorrect Correct Incorrect Correct 0 X X 1 Correct Correct Correct Correct 0 X 0 X Correct Correct Correct Correct 0 X 0 0 Correct Correct Correct Correct 0 X 0 1 Correct Incorrect Correct Correct 0 X 1 X Correct Correct Correct Correct 0 X 1 0 Correct Correct Correct Correct 0 X 1 1 Correct Correct Correct Correct 0 0 X X Correct Correct Correct Correct 0 0 X 0 Correct Correct Correct Correct 0 0 X 1 Correct Correct Correct Correct 0 0 0 X Correct Correct Correct Correct 0 0 0 0 Correct Correct Correct Correct 0 0 0 1 Correct Correct Correct Correct 0 0 1 X Correct Correct Correct Correct 0 0 1 0 Correct Correct Correct Correct 0 0 1 1 Correct Correct Correct Correct 0 1 X X Correct Correct Correct Correct 0 1 X 0 Correct Correct Correct Correct 0 1 X 1 Correct Correct Correct Correct 0 1 0 X Correct Correct Correct Correct 0 1 0 0 Correct Correct Correct Correct 0 1 0 1 Correct Correct Correct Correct 0 1 1 X Correct Correct Correct Correct 0 1 1 0 Correct Correct Correct Correct 0 1 1 1 Correct Correct Correct Correct 1 X X X Incorrect Correct Incorrect Correct 1 X X 0 Correct Correct Correct Correct 1 X X 1 Correct Correct Correct Correct 1 X 0 X Correct Correct Correct Correct 1 X 0 0 Correct Incorrect Correct Correct 1 X 0 1 Correct Correct Correct Correct 1 X 1 X Correct Correct Correct Correct 1 X 1 0 Correct Correct Correct Correct 1 X 1 1 Correct Incorrect Correct Correct 1 0 X X Correct Correct Correct Correct 1 0 X 0 Correct Correct Correct Correct 1 0 X 1 Correct Correct Correct Correct 1 0 0 X Correct Correct Correct Correct

1 0 0 0 Correct Correct Correct Correct 1 0 0 1 Correct Correct Correct Correct 1 0 1 X Correct Correct Correct Correct 1 0 1 0 Correct Correct Correct Correct 1 0 1 1 Correct Correct Correct Correct 1 1 X X Correct Correct Correct Correct 1 1 X 0 Correct Correct Correct Correct 1 1 X 1 Correct Correct Correct Correct 1 1 0 X Correct Correct Correct Correct 1 1 0 0 Correct Correct Correct Correct 1 1 0 1 Correct Correct Correct Correct 1 1 1 X Correct Correct Correct Correct 1 1 1 0 Correct Correct Correct Correct 1 1 1 1 Correct Correct Correct Correct

APPENDICE 3: RTL VIEW

Figure 25: RTL diagram for Reversible AND Gate

Figure 26: RTL diagram for Reversible OR Gate

Figure 27: RTL diagram for Reversible XOR Gate

Figure 28:RTL diagram for Reversible Half Adder