Hardware implementation of Reversible Logic Gates in VHDL By Dibya Gautam Submitted in Partial Fulfillment of the Requirements For the Degree of Master of Science in the Electrical and Computer Engineering Program YOUNGSTOWN STATE UNIVERSITY August, 2020 Hardware implementation of Reversible Gates in VHDL Dibya Gautam I hereby release this thesis to the public. I understand that this thesis will be made available from the OhioLINK ETD Center and the Maag Library Circulation Desk for public access. I also authorize the University or other individuals to make copies of this thesis as needed for scholarly research. Signature: Dibya Gautam, Student Date Approvals: Dr. Frank X. Li, Thesis Advisor Date Dr. Faramarz Mossayebi, Committee Member Date Edward Burden, Committee Member Date Dr. Salvatore A. Sanders, Dean of Graduate Studies Date ABSTRACT This research aims at hardware implementation of the reversible logic gate models and reversible logic circuit in VHDL. The application of the research pertains to the field of mathematics and cybersecurity. Furthermore, this research discusses the possibilities of changing the traditional digital logic gates, which allow the information to flow only in one direction, and successfully implementing a reverse information flow in hardware. Reversible logic gates are designed in such a way that they deduce information based on the given state of inputs and outputs. VHDL codes and simulations for reversible logic gates are introduced in this study. After developing reversible logic gates, a reversible half adder digital circuit was constructed. This implementation can be very useful for designing other larger digital circuits in the near future as it presents a new model of reversibility. To better understand the necessity of internal core architecture while designing the system, a performance analysis of the reversible half adder circuit is given. It discusses all the steps introduced inside the reversible digital architecture. Based on the simulation results, we can conclude that reversible logic gates successfully deduce information. Thus, the hardware implementation of an algorithm written in Python (high-level language) to a VHDL (low-level language) was successful. However, reversible half adder circuit simulation shows more information is needed for the reversible logic gates to become a feasible method aimed at designing complex circuits. iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude to my advisor Prof. Dr. Li for the constant guidance throughout my study and related research. To my mentor Patrick Bollinger, I express my deepest appreciation for always giving me insights to solve the challenges faced during this research. I am also very grateful to my thesis committee members, Dr. Faramarz Mossayebi and Professor Edward Burden for their valuable suggestions and assistance. I would also like to thank the rest of the faculty of the Electrical and Computer Engineering department for their teachings and support which certainly helped me to excel in this phase of my life. I would also take this opportunity to heartily thank my beloved father Arjun Gautam and mother Reetu Gautam for their immense love and support. I am extremely grateful to my dearest friend Kapila Ghimire for always encouraging me and reviewing my paper as many times as needed. I would also like to thank all my friends for their constant support and inspiration. Lastly, I would like to thank my life partner, Samy. I could not have accomplished in this endeavor without his constant motivation. iv TABLE OF CONTENTS ABSTRACT ................................................................................................................. iii TABLE OF CONTENTS .................................................................................................. v LIST OF FIGURES ....................................................................................................... vii LIST OF TABLES ......................................................................................................... viii LIST OF ABBREVIATIONS ............................................................................................ ix CHAPTER I .................................................................................................................. 1 INTRODUCTION .......................................................................................................... 1 1.1 Motivation and Background ...................................................................................1 1.2 Purpose........................................................................................................................2 1.3 Objectives ....................................................................................................................2 1.4 Organization ................................................................................................................2 CHAPTER II ................................................................................................................. 3 LITERATURE REVIEW .................................................................................................. 3 2.1 VHDL …Python…… ........................................................................................................3 2.1.1 Python/Sequential programming ................................................................................................. 3 2.1.2 VHDL as programmatic representation of Hardware ................................................................... 4 2.1.3 Application specific Integrated circuit (ASIC) ................................................................................ 4 2.2 Logic Gates and Digital circuits ......................................................................................5 2.2.1 Logic Gates .................................................................................................................................... 5 2.2.2 Digital Circuits ............................................................................................................................... 7 2.3 Reversible Logic Gates ..................................................................................................8 CHAPTER III .............................................................................................................. 10 Hardware Design and Implementation of Reversible Logic gates ............................... 10 3.1 Hardware Design of Reversible Logic Gates ................................................................. 10 3.1.2 Reversible AND Gate ................................................................................................................... 11 3.1.2 Reversible OR Gate ..................................................................................................................... 19 3.1.3 Reversible XOR Gate ................................................................................................................... 22 3.2 Reversible Digital Circuits ........................................................................................... 26 3.2.1 Hardware implementation of Reversible Half Adder.................................................................. 27 3.2.1.1 Resolver ............................................................................................................................... 28 CHAPTER IV: RESULTS AND DISCUSSIONS.................................................................. 34 4.1 Consideration of Reversible logic Gates model ............................................................ 34 4.1.1 Bi-directional approach ............................................................................................................... 34 4.1.2 State table approach ................................................................................................................... 35 v 4.2 Analysis of Reversible Half adder ................................................................................ 37 4.2.1 Adding Resolvers ........................................................................................................................ 37 4.2.2 Error tracker and Multiplexer ..................................................................................................... 37 4.2.2 Clocks and reset ......................................................................................................................... 38 4.2.2.1 One clock, no reset.............................................................................................................. 39 4.2.2.2 One clock, with reset........................................................................................................... 39 4.2.2.3 Two clocks, no reset ............................................................................................................ 40 4.2.2.4 Two clocks, with reset ......................................................................................................... 41 4.2.2.5 Comparison of all the above cases of adding clocks and reset ........................................... 42 CHAPTER V ............................................................................................................... 43 CONCLUSION ............................................................................................................ 43 References ............................................................................................................... 44 APPENDICES: