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DRAM Terms and Glossary Rev 5A DIMM Dual In-Line Memory Module NF No Function, DNU, T 1T, 2T, 3T, Etc

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MindShare DRAM Quick Reference Guide (Rev 5a) DRAM Terms and Glossary Rev 5a DIMM Dual In-line Memory Module NF No Function, DNU, T 1T, 2T, 3T, etc. timing, By John Swindle, Precept Technologies, Inc. DM Data Mask connected on die as 1N, 2N, etc. Please report errors or additions to DNU Do Not Use, NF, connected on die OCD Off-Chip Driver tCK Time for one tick of CK [email protected] DQ Data ODT On-Die Termination t JEDEC timing spec XXX XXX T JEDEC Temperature spec XXX 3DS 3 Dimensional Silicon or Stack DQS Data Strobe OTF On The Fly XXX DRAM Dynamic Random Access Memory PASR Partial Array Self Refresh TDQS Termination DQS, not RDQS ab, AB All Banks (LPDDRs), ECC Error Checking and Correcting pb per bank TSOP Thin Small Outline Package AP in PC DDRs eMMC Embedded Multi-Media Card TSV Through Silicon Via ACT Active aka Activate command PC3 DDR3, informally EMRS Extended Mode Register Set TUF Temperature Update Flag AL Additive Latency, 0 to 5 for DDR2, PC4 DDR4, informally command PCH Intel Platform Controller Hub UDIMM Unbuffered DIMM 0, CL-1, or CL-2 for DDR3 & 4, FBDIMM Fully-Buffered DIMM PDA Per-DRAM Addressability UDM Upper Data Mask RL = AL + CL + PL FBGA Fine-pitch BGA UDQS Upper Data Strobe AMB Advanced Memory Buffer PEC SMB Packet Error Checking GDDR Graphics DDR, UFS Universal Flash Storage AMBA Advanced Microcontroller Bus PHY Physical Layer not JEDEC DDR1, 2, 3 PL Parity Latency UFSA Universal Flash Storage Association Architecture HBM High Bandwidth Memory PLL Phase-Locked Loop UI Unit Interval, AP Auto Precharge, Precharge All, A10 HSUL High Speed Unterminated Logic POD Pseudo Open Drain single half-clock bit time ASR Auto Self Refresh, auto temp., IDD I current PoP Package on Package V Power (not for DRAM) not Auto Refresh DD CC I2C Philips Inter-Integrated Circuit, PRE Precharge command V Core Power AXI Advanced eXtensible Interface DD I squared C RA Row Address V IO Power BA Bank Address DDQ ICH Intel IO Controller Hub RAS Row Address Strobe V Reference Voltage BC Burst Chop REF ISM Internal Stacked Module RAS Reliability, Availability, V Voltage Pump Replacement Power BC# Burst Chop pin, A12 PP JEDEC Solid State Technology Association, Servicability V Ground BC4 Burst Chop 4 SS was Joint Electron Device RCD RAS-to-CAS Delay V Termination Voltage BG Bank Group TT Engineering Council RCD Registering Clock Driver VLP Very Low Profile BGA Ball Grid Array LDM Lower Data Mask RDIMM Registered DIMM WCL Write Command Latency (not CWL) BL Burst Length LDQS Lower Data Strobe RDQS Redundant DQS Added to WL if both BL4 DDR2 Burst Length 4 UI, LP3 LPDDR3, informally REF Refresh command CRC & DM enabled inappropriate term for DDR3/4 BC4 LP4 LPDDR4, informally RFU Reserved for Future Use WL Write Latency BL8 Burst Length 8, 8 UI of DQ LPDDR Low-Power DDR, LPDDR1 RL Read Latency = CL + AL + PL 1 for DDR1; RL - 1 for DDR2; BL9 Inappropriate term for LPDDR2 Low-Power DDR2 RLDRAM Reduced-Latency DRAM variable for DDR3 & DDR4 BL8 + CRC x8,x16 LPDDR3 Low-Power DDR3 QERR# RCD parity error pin WL = CWL + AL + PL BL10 Inappropriate term for LPDDR4 Low-Power DDR4 S# CS# in 21C spec XDR Rambus DRAM, BL8 + CRC x4 LRDIMM Load-Reduced DIMM S3 Suspend to DRAM pwr mgmt state improperly ‘XDRAM’ C Chip ID, like CS# but for 3DS LVSTL Low Voltage Swing S4EC D4ED Single 4-bit Error Correction, ZQ Data Source Impedance: C Column Address (LPDDR3) Terminated Logic Double 4-bit Error Detection Q=data, Z=impedance CA Column Address (DDR3) MCH Intel Memory Controller Hub SA SMB hardwired DIMM addr., Numbering CA Command and Address (LPDDRs) MCP Multi-Chip Package not bused 1n, 2n, 4n, 8n Prefetch widths CAS Column Address Strobe MIPI Mobile Industry Processor Interface SCL SMB clock pin, DIMM pin 1T, 1N New command every clock CB Check Bit MO Microelectronic Outline SDA SMB address and data pin, 2T, 2N New command every other clock CDIMM Clocked 72-bit Mini DIMM MoBo Motherboard DIMM pin 4T, 6T SRAM (not SDRAM) CK Clock M-PHY MIPI PHY SDRAM Synchronous DRAM cell technology CKE Clock Enable MPR Multi Purpose Register, NOT a MR SECDED Single bit Error Correction, DDRn-mmm n=2,3,4 mmm=MT/s CL CAS Latency (in MR0) = RL – AL MR Mode Register Double bit Error Detection Example: DDR2-800 = 400MHz CK CRC Cyclic Redundancy Check MRR Mode Register Read command SIMM Single In-line Memory Module PC 97, PC 99 Microsoft PC requirements, CS# Chip Select, Rank, S# in 21C spec MRS Mode Register Set command SMB System Management Bus not DRAM CTT Center Tap Termination (set is verb) SMBus System Management Bus PC 100 Early SDRAM DIMM bandwidth CWL CAS Write Latency (in MR2) MRW Mode Register Write command SO-DIMM Small Outline DIMM PCn-xxxx xxxx=DIMM KB/sec bandwidth DBI# Data Bus Inverted n Width of device’s data bus SPD Serial Presence Device or Detect × DES Device Deselect (pseudo command) =MT/s DIMM data width / 8 (for prefetch) SPD ROM SPD ROM DLL Delay-Locked Loop x-x-x CL-tRCD-tRP (older standards) N 1N, 2N, 3N, etc. timing, 1T, 2T, etc. SRAM Static Random Access Memory DDR Double Data Rate, DDR1 CL-nRCD-nRP (newer standards) nCK One tick of CK as SRT Self Refresh Temperature, see ASR DDR1 Double Data Rate, DDR x-x-x-x CL-tRCD-tRP-tRAS dimensionless number SSTL Stub Series-Terminated Logic DDR2 Double Data Rate 2 n × n Device density × data width NC No Connect, not connected on die DDR3 Double Data Rate 3 n × n × n Array density × data width × #banks www.mindshare.com MindShare DRAM Quick Reference Guide (Rev 5a) Terms Commands Timings Specifications Access time CK to DQS. ACT Bank ACTive aka ACTivate tAA Time internal read to first data JESD8-8 SSTL_3 3.3 volt spec Formerly RAS# to valid data BST Burst Terminate, Burst STop tAC Time CK to DQS, access JESD8-9B SSTL_2 2.5 volt spec Activate ACT Active Command DES Device DESelect, CS# false tCH Time CK high JESD8-15A SSTL_18 1.8 volt spec Active ACT Active Command, Open DPD Deep Power Down entry tCK Time CK period JESD8-18A FBDIMM signals (not SSTL_18) Array One bank of the device DPDX Deep Power Down eXit tCL Time CK low, ? SSTL_15 1.5 volt spec Auto Precharge Precharge after read/write EMRS Extended Mode Register Set NOT CAS Latency CL JESD8-22 HSUL spec w/o explicit PRE cmd. MRR Mode Register Read tDQSCK Time CK to DQS JESD8-24 1.2v POD spec Auto Refresh Just Refresh, MRS Mode Register Set tFAW Time Four Activate Window JESD21C DIMM (and thus SPD) spec not ASR nor Self Refresh MRW Mode Register Write tMOD Time MRS to non-MRS command JESD79F DDR SDRAM standard Bank Formerly rank. NOP No Operation tMRD Time MRS to MRS command Delay JESD79-2F DDR2 SDRAM standard Internal to DRAM device. PD Power-Down entry tMRW Time MRW to any command JESD79-3F DDR3 SDRAM standard Bank Group Four banks in DDR4 PDE Power-Down Entry tRAS Time Active to Precharge, JESD79-3-1 DDR3L SDRAM standard Bit Line Several per column PDX Power-Down eXit ACT to PRE JESD79-3-2 DDR3U SDRAM standard Burst Sequential or interleaved PR Per-bank Precharge max 9 x tREFI, min by speed bin JESD79-4 DDR4 SDRAM standard Channel Interface between controller's PRA All-bank Precharge tRC Time ACT to ACT or ACT to REF, JESD209B LPDDR1 SDRAM standard PHY and a rank of DRAM; PRE Single-bank PREcharge no PRE in-between JESD209-2E LPDDR2 SDRAM standard SMB & SPD are not on the PREA PREcharge All banks tRCD Time RAS-to-CAS delay, JESD209-3B LPDDR3 SDRAM standard channel. RD ReaD fixed BL8 or BC4 ACT to RD/WR JESD229 Wide IO SDRAM standard Column In Read/Write command RDA RD w/Auto-precharge tREFI Time Refresh Interval MO-207 BGA package spec Command RAS#, CAS#, and WE# RDAS4 RDA BC4, OTF 1.95, 3.9, or 7.8uS MO-309A DDR4 DIMM spec Control CS#, CKE, and ODT RDAS8 RDA BL8, OTF tRFC Time Refresh Command Data Group DQ, DQS, DM/DBI RDS4 RD BC4, OTF 72 to 350nS Dynamic ODT ODT when written to. RDS8 RD BL8, OTF tRP Time Precharge, Recovery Period Fast CKE Power Down Power Down w/ DLL REF REFresh tRRD Time ACT to ACT, different banks, Enabled SRE Self-Refresh Entry no PRE between Signal Suffixes Idle Closed, Precharged SREF Self-REFresh entry tRTP Time Read to Precharge # asserted low, negative logic Open Active, Activated SREFX Self-REFresh eXit # complementary signal in Page Row SRX Self-Refresh eXit tXX as in tCK, time period, differential pair Page size Row size expressed as bytes WR WRite fixed BL8 or BC4 inconsistently used as in tCCD_S=5 _n asserted low, negative logic not bits WRA WR w/Auto-precharge which is 5 ticks, not 5ns. _t true signal in differential pair Postamble DQS after read/write WRAS4 WRA BC4, OTF _c complementary signal in Preactive NVM term, NOT DRAM WRAS8 WRA BL8, OTF nXX as in nRCD, number of CK ticks, differential pair Preamble DQS before read/write WRS4 WR BC4, OTF inconsistently used as in tAA+2nCK r rising Precharge PRE/PREA command WRS8 WR BL8, OTF which should be tAA+2tCK. f falling Prefetch width 1n, 2n, 4n, 8n, 16n ZQCL ZQ Calibration Long Rank CS# ZQCS ZQ Calibration Short CL = ticks for CAS Latency, Raw Card JESD21C DIMMs never shown as nCL.
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