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A New Era of Open-Source System-On-Chip Design

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A New Era of Open-Source System-On-Chip Design A New Era of Open-Source System-on-Chip Design Christopher Batten Computer Systems Laboratory Electrical and Computer Engineering, Cornell University On Sabbatical as a Visiting Scholar Computer Laboratory, University of Cambridge • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Motivating Trends in Computer Architecture 7 Hardware 10 Intel 48-Core Prototype Transistors (Thousands) Specialization AMD 4-Core Opteron 6 10 Data-Parallelism via Intel GPGPUs & Vector P4 5 10 ~15%/year SPECint Fine-Grain Task- DEC Performance Level Parallelism Alpha 4 21264 Instruction Set 10 ~9%/year Frequency Specialization MIPS (MHz) 3 R2K Subgraph 10 Specialization Typical 2 Application-Specific 10 Power (W) Accelerators Number 1 Domain-Specific 10 of Cores Accelerators 0 Coarse-Grain 10 Reconfig Arrays 1975 1980 1985 1990 1995 2000 2005 2010 2015 Field-Programmable Data collected by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, C. Batten Gate Arrays Cornell University Christopher Batten 2 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Hardware Specialization from Cloud to IoT Cloud Google TPU Computing I Training is done using the TensorFlow C++ framework I Training can take weeks I Google TPU is custom chip to accelerate training and inference Movidius Myriad 2 I Custom chip for ML on embedded IoT devices I Specifically focused on vision processing Internet I 12 specialized vector VLIW of processors Things Cornell University Christopher Batten 3 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH I Graphcore I Nervana I Cerebras I Wave Computing I Horizon Robotics I Cambricon How can we accelerate I DeePhi innovation in I Esperanto accelerator-centric I SambaNova system-on-chip design? I Eyeriss I Tenstorrent I Mythic I ThinkForce I Groq I Lightmatter Cornell University Christopher Batten 4 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Software Innovation Today Like climbing an iceberg – much is hidden! Your proprietary code • Instagram • $500K seed with 13 people → $1B Open-source software • Python • Django • Memcached • Postgres/SQL • Redis • nginx • Apache, Gnuicorn • Linux "What Powers Instagram: • GCC Hundreds of Instances, Dozens of Technologies" https://goo.gl/76fWrM Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16 Cornell University Christopher Batten 5 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Hardware Innovation Today Like climbing a mountain – nothing is hidden! What you have to build • New machine learning accelerator • Other unrelated components, anything you cannot afford to buy or for which COTS IP does not do Closed source • ARM A57, A7, M4, M0 • ARM on-chip interconnect • Standard cells, I/O pads, DDR Phy • SRAM memory compilers • VCS, Modelsim • DC, ICC, Formality, Primetime • Stratus, Innovus, Voltus • Calibre DRC/RCX/LVS, SPICE Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16 Cornell University Christopher Batten 6 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Chip Costs Are Skyrocketing $120M $500K Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16; original: International Business Strategies & T. Austin. Cornell University Christopher Batten 7 / 50 HW• Open-Source diversity HW • PyMTL Motivation PyMTLof v2 computingPyMTL v3 PyMTL&OSH Celerity devices Arch Celerity Case Study is Celerity&OSH dwindling… ASIC Starts Are Declining 12000 10000 8000 6000 4000 Total&ASIC&Starts 2000 0 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 Year Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16; original: Gartner Group & T. Austin Cornell University Christopher Batten the HW field in general? Source: Gartner Group, 8T. / 50 Austin 20 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Minimum Viable Product/Prototype $120M $5M $500K for 4x Performance Penalty (post-Dennard scaling) Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16; original: International Business Strategies & T. Austin. Cornell University Christopher Batten 9 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Minimum Viable Product/Prototype $120M Can we use open-source software/hardware to address remaining costs? Adapted from M. Taylor, “Open Source HW in 2030,” Arch 2030 Workshop @ ISCA’16; original: International Business Strategies & T. Austin. Cornell University Christopher Batten 9 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH How can HW design be more like SW design? Open-Source Software Hardware high-level Python, Ruby, R, Chisel, PyMTL, PyRTL, MyHDL, languages Javascript, Julia JHDL, Cλash libraries C++ STL, BaseJump Python std libs systems Linux, Apache, MySQL, Rocket, Pulp/Ariane, OpenPiton, memcached Boom, FabScalar, MIAOW, Nyuzi standards POSIX RISC-V ISA, RoCC, TileLink tools GCC, LLVM, CPython, Icarus Verilog, Verilator, qflow, MRI, PyPy, V8 Yosys, TimberWolf, qrouter, magic, klayout, ngspice methodologies agile software design agile hardware design cloud IaaS, elastic computing IaaS, elastic CAD Cornell University Christopher Batten 10 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH # Ubuntu Server 16.04 LTS (ami-43a15f3e) % sudo apt-get update % sudo apt-get -y install build-essential qflow % mkdir qflow && cd qflow % wget http://opencircuitdesign.com/qflow/example/map9v3.v % qflow synthesize place route map9v3 # yosys, graywolf, qrouter % wget http://opencircuitdesign.com/qflow/example/osu035_stdcells.gds2 % magic # design def/lef -> magic format >>> lef read /usr/share/qflow/tech/osu035/osu035_stdcells.lef >>> def read map9v3.def >>> writeall force map9v3 % magic # stdcell gds -> magic format >>> gds read osu035_stdcells.gds2 >>> writeall force % magic map9v3 >>> gds write map9v3 # design + stdcells magic format -> gds % sudo apt-get -y install libqt4-dev-bin libqt4-dev libz-dev % wget http://www.klayout.org/downloads/source/klayout-0.24.9.tar.gz % tar -xzvf klayout-0.24.9.tar.gz && cd klayout-0.24.9 % ./build.sh -noruby -nopython % wget http://www.csl.cornell.edu/~cbatten/scmos.lyp % ./bin.linux-64-gcc-release/klayout -l scmos.lyp ../map9v3.gds Cornell University Christopher Batten 11 / 50 • Open-Source HW • PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH “I’m doing a (free) operating system (just a hobby, won’t be big and professional like gnu) for 386(486) AT clones.” — Linus Torvalds, 1991 Cornell University Christopher Batten 12 / 50 Open-Source HW PyMTL Motivation • PyMTL v2 • PyMTL v3 PyMTL+OSH Celerity Arch Celerity Case Study Celerity+OSH Open-Source HW PyMTLPyMTL Motivation v2 SyntaxPyMTL and v2 PyMTL Semantics v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH 1 from pymtl import * 2 3 class RegIncrRTL( Model ): A New Era of 4 5 def __init__( s, dtype ): Open-Source SoC Design 6 s.in_ = InPort ( dtype ) 7 s.out = OutPort( dtype ) 8 s.tmp = Wire ( dtype ) 9 I The PyMTL Framework 10 @s.tick_rtl 11 def seq_logic(): . PyMTL Motivation 12 s.tmp.next = s.in_ 13 . PyMTL Version 2 14 @s.combinational 15 def comb_logic(): 16 s.out.value = s.tmp + 1 . PyMTL Version 3 (Mamba) . PyMTL & Open-Source Hardware Cornell University Christopher BattenI The Celerity SoC19 / 48 . Celerity Architecture . Celerity Case Study . Celerity & Open-Source Hardware I A Call to Action Cornell University Christopher Batten 13 / 50 Open-Source HW PyMTL Motivation PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH PyMTL PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research Derek Lockhart, Gary Zibrat, Christopher Batten 47th ACM/IEEE Int’l Symp. on Microarchitecture (MICRO) Cambridge, UK, Dec. 2014 Mamba: Closing the Performance Gap in Productive Hardware Development Frameworks Shunning Jiang, Berkin Ilbeyi, Christopher Batten 55th ACM/IEEE Design Automation Conf. (DAC) San Francisco, CA, June 2018 Cornell University Christopher Batten 14 / 50 Open-Source HW • PyMTL Motivation • PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Multi-Level Modeling Methodologies Functional-Level Modeling Applications – Behavior Algorithms Cycle-Level Modeling Compilers – Behavior – Cycle-Approximate Instruction Set Architecture – Analytical Area, Energy, Timing Microarchitecture Register-Transfer-Level Modeling VLSI – Behavior – Cycle-Accurate Timing Transistors – Gate-Level Area, Energy, Timing Cornell University Christopher Batten 15 / 50 Open-Source HW • PyMTL Motivation • PyMTL v2 PyMTL v3 PyMTL&OSH Celerity Arch Celerity Case Study Celerity&OSH Multi-Level Modeling Methodologies Multi-Level Modeling Functional-Level Modeling Challenge – Algorithm/ISA Development FL, CL, RTL modeling – MATLAB/Python, C++ ISA Sim use very different languages, patterns, Cycle-Level Modeling tools, and methodologies – Design-Space Exploration – C++ Simulation Framework SystemC is a good example – SW-Focused
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