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DRAM Fault Analysis and Test Generation DRAM Fault Analysis and Test Generation DRAM Fault Analysis and Test Generation Proefschrift ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof.dr.ir. J.T. Fokkema, voorzitter van het College voor Promoties, in het openbaar te verdedigen op maandag 27 juni 2005 om 15.30 uur door Zaid AL-ARS elektrotechnisch ingenieur geboren te Bagdad, Irak Dit proefschrift is goedgekeurd door de promotor: Prof.dr.ir. A.J. van de Goor Samenstelling promotiecommissie: Rector Magnificus, chair Delft University of Technology, Delft, The Netherlands Prof.dr.ir. A.J. van de Goor Delft University of Technology, Delft, The Netherlands Prof.dr.ing. E.J. Aas Norwegian Univ. of Sci. and Tech., Trondheim, Norway Prof.dr. C.I. Beenakker Delft University of Technology, Delft, The Netherlands Prof.dr. H. Corporaal Tech. Univ. of Eindhoven, Eindhoven, The Netherlands Dr. S. Mijalkovic Delft University of Technology, Delft, The Netherlands Dr. G. Muller¨ Infineon Technologies, Munich, Germany Prof.dr. L. Nanver Delft University of Technology, Delft, The Netherlands Prof.dr. J.R. Long Delft University of Technology, Delft, The Netherlands This work has been supported by Infineon Technologies, Munich, Germany, with a grant to the Delft University of Technology. Graphical cover illustration by ATOC Designs (http://www.atocdesigns.com/) ISBN-13: 978-90-9019612-1 ISBN-10: 90-9019612-9 NUR 959 Copyright c 2005 Zaid Al-Ars All rights reserved. No part of this publication, either text or image may be used for any purpose other than personal use. Reproduction, modification, storage in a retrieval system or retransmission, in any form or by any means, electronic, mechanical, or otherwise, for reasons other than personal use, is strictly prohibited without prior written permission from the author. To my father for teaching me how to have a dream, and to my mother for showing me how to make it a reality. DRAM Fault Analysis and Test Generation Abstract The dynamic random access memory (DRAM) is the most widely used type of memory in the market today, due to its important application as the main memory of the personal computer (PC). These memories are elaborately tested by their manufacturers to ensure a high quality product for the consumer. However, this testing process is responsible for a large portion of the cost of these memories, standing now at 40% and gradually rising with each new generation. Companies usually develop the required memory tests in an ad hoc manner, relying heavily on an expensive combination of experience and statistics to construct the best test approach, the price of which is ultimately paid by the end consumer. In this thesis, we propose a new alternative approach to the development of industrial memory testing that is more systematic and less expensive than the currently prevalent test approaches. The new approach is based on the introduction of a number of fault analysis algorithms that enable the application of electrical Spice simulations to develop effective memory tests in a short amount of time. The new approach makes it possible to enhance memory tests in many different manufacturing stages, starting from the initial test application stage where silicon is manufactured, through the memory ramp-up stage where products are shipped to the customer, and ending with the test adaptation stage, based on memory failures in the field. The new test development approach has been implemented and evaluated at Infineon Technologies, a leading DRAM manufacturer, to develop tests for their DRAM products. This thesis describes the details of the proposed test development algorithms, along with the way they are practically implemented for DRAM devices. Two different aspects necessary for DRAM tests are identified: test patterns and test stresses, then methods to generate and optimize both of them are proposed. In addition, the thesis discusses the results of applying the proposed approach to a large number of DRAM defects, modeled from known DRAM failures on the layout level. Finally, the thesis ends with an elaborate case study to generate and optimize tests for a specific DRAM problem for which the new test development approach has proven its effectiveness. Fout Analyseren en Test Genereren in DRAMs Samenvatting (Abstract in Dutch) Het dynamic random access memory (DRAM) is heden het meest gebruikte type geheugen, wegens zijn belangrijke toepassing als het werkgeheugen van de personal computer (PC). Geheugen chips worden door geheugen fabrikanten uit- voerig getest om de hoge kwaliteit van hun producten te garanderen. Dit testproces is verantwoordelijk voor een groot gedeelte van de kosten van een geheugen, die nu rond 40% is, en geleidelijk met elke nieuwe geheugen generatie toeneemt. In het algemeen ontwikkelen bedrijven de vereiste geheugentests op een ad hoc manier, gebaseerd op een dure combinatie van ervaring en statistieken, om de beste tests te construeren. De prijs daarvan wordt uiteindelijk door de consument betaald. In dit proefschrift, stellen wij een nieuwe en alternatieve benadering van indus- trieel test ontwikkeling voor, die systematischer en goedkoper is dan de huidige testmethoden. De nieuwe benadering is gebaseerd op de introductie van een aantal algoritmen om geheugenfouten door middel van elektronische Spice simulaties te analyseren. Dit maakt het mogelijk effici¨ente geheugentests op korte termijn te ontwikkelen en om de tests in vele verschillende productiestadia te verbeteren. De nieuwe testontwikkeling methoden zijn bij Infineon Technologies, een belangrijke DRAM fabrikant, uitgevoerd en gevalueerd om tests voor hun DRAM producten te ontwikkelen. Het proefschrift beschrijft de details van de voorgestelde testontwikkeling al- goritmen, samen met de manier waarop zij praktisch voor DRAMs worden uitge- voerd. Twee belangrijke DRAM testaspecten worden ge¨ıdentificeerd (testpatronen, en teststress), en methoden om beide testaspecten te produceren en te optimali- seren worden voorgesteld. Bovendien bespreekt het proefschrift de toepassings resultaten van de voorgestelde testmethoden op een groot aantal bekende DRAM defecten, die belangrijk zijn op het layout-niveau. Tot slot eindigt het profschrift met een gedetailleerde casestudy, om tests voor een specifiek DRAM probleem te produceren en te optimaliseren. Hierin wordt het nut van de nieuwe benadering van testontwikkeling bewezen. Preface From the bulky drum memory used in the early computer systems, through the relatively expensive core memory, to the semiconductor memory used extensively in most of today's integrated circuits (ICs), memory has played a vital, albeit quiet role in the history of computing. However, this important role is gradually becom- ing ever clearer, due to the exponentially increasing amount of memory used in ICs today, and because a constantly growing percentage of these ICs is being ded- icated to implement memory devices. According to the International Technology Roadmap for Semiconductors (ITRS), a leading authority in the field of semicon- ductors, memory occupied 20% of the area of an IC in 1999, 52% in 2002, and is forecast to occupy up to 90% of the area by the year 2011. Due to this consid- erable usage of memory in many ICs, improvements in the design and fabrication process of memory devices have a considerable impact on the overall IC charac- teristics. Therefore, reducing the energy consumption, increasing the reliability or, most importantly, reducing the price of memories has a similar impact on the overall systems that contain them. Furthermore, a large portion of the price of a memory today is incurred by the high costs of memory testing, which has to satisfy very high quality constraints ranging from 50 failing parts per million (ppm) for computer systems to less than 10 ppm for mission-critical applications (such as those in the automotive industry). Memory testing is expensive because of the high cost of the test equipment (a pro- duction memory tester costs more than $500; 000), a cost that has to be distributed over all of the produced chips, good and bad. As an example, a well-designed test of a typical 64 Mb DRAM comprises 39% of its total cost. The test cost of a 256 Mb DRAM is estimated to be more than 50% of the total cost, making the field of memory testing a rather significant and influential part of the whole memory production process. Despite the huge current and future growth potential of the filed of memory testing, not much research has been dedicated to this important aspect of the IC industry. This lack of research is mainly due to the fact that memory testing is a relatively new and developing field, and to the unorthodox mathematical techniques it employs for fault modeling and test generation. Moreover, only a limited number of research projects exist in this field in the form of a collaboration between the industry and the academic world, due to the company-confidential nature of the memory test information. xi xii PREFACE j A word on the project The work in this thesis describes the results of a joint research project titled \Fault Analysis of DRAMs Using Defect Injection and Simulation" between Infineon Tech- nologies, Munich, Germany, and the Delft University of Technology, Delft, The Netherlands, to analyze the faulty behavior of DRAMs produced by Infineon. It represents an example of a small number of projects between the memory indus- try and academia, meant to study the faulty behavior of memory devices and to suggest new, theoretically justified memory tests. The current project is a con- tinuation of a previous joint project between Siemens Semiconductors (presently Infineon Technologies) and the Delft University of Technology, which supplied the material for the masters thesis \Analysis of the Space of Functional Fault Models and Its Application to Embedded DRAMs", by Zaid Al-Ars. When we started out working on the project, the objective was to come up with a set of memory tests able to effectively detect the faults commonly encountered in DRAM chips.
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