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EEC 216 Lecture #2: Metrics and Logic Level Power Estimation

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EEC 216 Lecture #2: Metrics and Logic Level Power Estimation EEC 216 Lecture #2: Metrics and Logic Level Power Estimation Rajeevan Amirtharajah University of California, Davis Announcements • PS1 available online tonight R. Amirtharajah, EEC216 Winter 2008 2 Outline • Announcements • Aside: Environmental Impact of Electronics • Finish Lecture 1 Topics • Intersignal Correlations • Glitches • High Level Power Estimation • Behavioral Level Power Estimation • Architectural Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 3 Power Consumption at the System Level • 500 MHz Pentium III with 17 in. Monitor: 150-200 W • Server: 300 W • Mainframe: 10-20 kW • Author’s home office: 2 CPUs, 2 monitors, laptop, 3 printers, scanner, plus misc. peripherals – Nameplate rating: 2.4 kW – Max power (incl. peripherals): 700 W – Typical usage: 150-170 W – Average over 10 days: 77 W (9% of total consumption) From B. Hayes, “The Computer and the Dynamo”, American Scientist, Sep-Oct 2001 R. Amirtharajah, EEC216 Winter 2008 4 Power Consumption at the National Level • All office equipment consumes 74 TW-hours / year (about 2% US total) • Adding telecoms increases total to 3.2 % • Power down and sleep modes could save 23-40 TWh • Technology has dramatically improved power cost of computing – ENIAC (1940s): 18,000 vacuum tubes, 174 kW, roughly 10 W / tube – Today’s microprocessors: 100 M transistors, 100 W, roughly 1 μW / transistor (would draw 10 GW if no change from 1940s) From B. Hayes, “The Computer and the Dynamo”, American Scientist, Sep-Oct 2001 R. Amirtharajah, EEC216 Winter 2008 5 Outline • Announcements • Aside: Environmental Impact of Electronics • Finish Lecture 1 Topics • Intersignal Correlations • Glitches • High Level Power Estimation • Behavioral Level Power Estimation • Architectural Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 6 Outline • Announcements • Aside: Environmental Impact of Electronics • Finish Lecture 1 Topics • Intersignal Correlations • Glitches • High Level Power Estimation • Behavioral Level Power Estimation • Architectural Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 7 Permissions to Use Conditions & Acknowledgment • Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al." This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. • Slides 9-20, 22-5 Adapted from CSE477 VLSI Digital Circuits Lecture Slides by Vijay Narayanan and Mary Jane Irwin, Penn State University R. Amirtharajah, EEC216 Winter 2008 8 NOR Gate Transition Probabilities • Switching activity is a strong function of the input signal statistics –PA, PB are the probabilities that inputs A, B are 1 A B 0 A B CL P A 10 1 PB P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB) R. Amirtharajah, EEC216 Winter 2008 9 Transition Probabilities for Basic Gates P0→1 = Pout=0 x Pout=1 NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB) OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB)) NAND PAPB x (1 - PAPB) AND (1 - PAPB) x PAPB XOR (1 - (PA + PB-2PAPB)) x (PA + PB-2PAPB) X 0.5 A Z 0.5 B For X: P0→1 = For Z: P0→1 = R. Amirtharajah, EEC216 Winter 2008 10 Transition Probabilities for Basic Gates P0→1 = Pout=0 x Pout=1 NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB) OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB)) NAND PAPB x (1 - PAPB) AND (1 - PAPB) x PAPB XOR (1 - (PA + PB-2PAPB)) x (PA + PB-2PAPB) X 0.5 A Z 0.5 B For X: P0→1 = P0 x P1 = (1-PA) PA = 0.25 For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB = 3/16 R. Amirtharajah, EEC216 Winter 2008 11 Problems With Input-to-Output Evaluation • Signal and transition probabilities are progressively evaluated from input to output node – Straightforward approach determined by circuit topology – Does not deal with feedback (for example in sequential circuits) – Assumes input signal probabilities are independent X 0.5 A Z For X: P0→1 = For Z: P0→1 = R. Amirtharajah, EEC216 Winter 2008 12 Problems With Input-to-Output Evaluation • Signal and transition probabilities are progressively evaluated from input to output node – Straightforward approach determined by circuit topology – Does not deal with feedback (for example in sequential circuits) – Assumes input signal probabilities are independent X 0.5 A Z For X: P0→1 = P0 x P1 = (1-PA) PA = 0.25 For Z: P0→1 = P0 x P1 = (1-PXPA) PXPA = 3/16 ? R. Amirtharajah, EEC216 Winter 2008 13 Problems With Input-to-Output Evaluation • Signal and transition probabilities are progressively evaluated from input to output node – Straightforward approach determined by circuit topology – Does not deal with feedback (for example in sequential circuits) – Assumes input signal probabilities are independent X 0.5 A Z For X: P0→1 = P0 x P1 = (1-PA) PA = 0.25 For Z: P0→1 = P0 x P1 = (1-PXPA) PXPA = 0 ! Z = A• A = 0 R. Amirtharajah, EEC216 Winter 2008 14 Intersignal Correlations • Determining switching activity is complicated by the fact that signals exhibit correlation in space and time, e.g. by circuits with reconvergent fanout 0.5 A X 0.5 B Z Reconvergent fanout: R. Amirtharajah, EEC216 Winter 2008 15 Intersignal Correlations • Determining switching activity is complicated by the fact that signals exhibit correlation in space and time, e.g. by circuits with reconvergent fanout P(X=1) = (1-0.5)(1-0.5)x(1-(1-0.5)(1-0.5)) = 3/16 0.5 A X 0.5 B Z P(Z=1) = (1- 3/16 x 0.5) x (3/16 x 0.5) = 0.085 ? Reconvergent fanout: R. Amirtharajah, EEC216 Winter 2008 16 Intersignal Correlations • Determining switching activity is complicated by the fact that signals exhibit correlation in space and time, e.g. by circuits with reconvergent fanout P(X=1|B=1) = 1 0.5 A X 0.5 B Z P(Z=1) = P(X=1|B=1) x P(B=1) = 0.5 ! Reconvergent fanout: P(Z=1) = P(B=1) x P(X=1 | B=1) • Have to use conditional probabilities! R. Amirtharajah, EEC216 Winter 2008 17 Logic Restructuring • Logic restructuring: changing the topology of a logic network to reduce transitions AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB 3/16 0.5 0.5 (1-0.25)*0.25 = 3/16 A Y A W 7/64 0.5B 15/256 X B 15/256 0.5 F 0.5 C C 0.5 D F 0.5DZ 0.5 3/16 • Chain implementation has a lower overall switching activity than the tree implementation for random inputs • Ignores glitching effects R. Amirtharajah, EEC216 Winter 2008 18 Input Ordering Two alternate implementations with inputs reordered, same function so output stats identical 0.5 0.2 B A X X C B F 0.2 C F 0.1 A 0.1 0.5 Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5) R. Amirtharajah, EEC216 Winter 2008 19 Input Ordering Two alternate implementations with inputs reordered, same function so output stats identical (1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196 0.5 0.2 B A X X C B F 0.2 C F 0.1 A 0.1 0.5 Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5) R. Amirtharajah, EEC216 Winter 2008 20 Time Multiplexing Resources • Time multiplexing can conserve area at the expense of increased switched capacitance • Consider the case of parallel vs. serial data transmission: more transitions due to muxing P ≈ 0 A 0→1 p ≈1 C A L A A P0→1 ≈ 0.5 B C B P ≈ 0 L B 0→1 p 0 B ≈ CL R. Amirtharajah, EEC216 Winter 2008 21 Outline • Announcements • Aside: Environmental Impact of Electronics • Finish Lecture 1 Topics • Intersignal Correlations • Glitches • High Level Power Estimation • Behavioral Level Power Estimation • Architectural Level Power Estimation R. Amirtharajah, EEC216 Winter 2008 22 Glitching in Static CMOS Networks • Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) – Glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value A X B C Z ABC 101 000 X Z Unit Delay R. Amirtharajah, EEC216 Winter 2008 23 Glitching in Static CMOS Networks • Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards) – Glitch: node exhibits multiple transitions in a single cycle before settling to the correct logic value A X B C Z ABC 101 000 X Z Unit Delay R. Amirtharajah, EEC216 Winter 2008 24 Glitching In A Ripple Carry Adder Cin S1 S0 S153 S14 S2 2 S3 S4 S15 Cin S2 1 S5 S10 S Output Voltage (V) S1 S0 0 024681012 R. Amirtharajah, EEC216 Winter 2008Time (ps) 25 Balanced Delay Paths to Reduce Glitching • Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs 0 0 0 F 1 1 0 F1 1 0 F2 2 F 0 3 0 F3 1 0 F2 So equalize the lengths of timing paths through logic Example: F1 and F2 have unit delay R. Amirtharajah, EEC216 Winter 2008 26 Switching Activity in Sequential Circuits • Estimating activity more difficult for sequential than combinational circuits – Due to activity of state nodes typically being unknown at beginning of estimation process – Compute activity assuming steady state • Assume sequential circuits implement FSM where states follow Markov process – Solve for probabilities of states using state transition probabilities • Best implemented in CAD tools R.
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