Vinidhra Sivakumar https://www.linkedin.com/in/vinidhra-sivakumar

1217, University City Blvd, #S185 (901)-634-6365 Blacksburg, VA - 24060 [email protected]

OBJECTIVE

Seeking a full-time position in Computer Engineering.

EDUCATION

Virginia Polytechnic Institute & State University (Virginia Tech), Blacksburg, Virginia Expected May 2018 Master of Engineering in Electrical and Computer Engineering Relevant Coursework: Computer Architecture, Data Analytics, Testing and verification of VLSI Circuits, Data and algorithm analysis, Advanced VLSI design, Wearable and ubiquitous Computing Research Interest: Approximate computing for NoC architectures GPA-3.56/4

International Institute of Information Technology, Hyderabad, India July 2011 Master of Technology in VLSI and Embedded Systems GPA-9.14/10.0

Thiagarajar College of Engineering, Madurai affiliated to Anna University, Chennai, India April 2009 Bachelor of Engineering in Electronics and Communications Engineering First class with Distinction, GPA-9.21/10.0

COMPUTER SKILLS

Programming / Scripting Languages: C, C++, UNIX Shell, Perl and Python Hardware Languages: Verilog, VHDL and System Verilog Tools: MATLAB, Cadence and Synopsys EDA tools, Verigy 93K Smartest, MS Excel, Weka

PROFESSIONAL EXPERIENCE

Qualcomm CDMA Technologies, India June 2011-June 2015 Senior Engineer

Product Test Engineering Simulation Lead • Led the PTE Simulation team ensuring flawless gate-level simulation and ATE vector readiness. • Responsible for Silicon bring up and ATE phasing for Qualcomm’s Remora SoC . • Engaged with Program management and 6 cross functional teams across geographies to forecast, plan and address vector readiness and critical vector phasing issues. • Initiated and implemented process flows and methodologies to reduce ATE test and debug time. • Coordinated with CAD teams to significantly reduce compile/run time of complex SoC designs and expedite silicon debug. Relevant Standards: IEEE JTAG, AMBA TIC interface, AMBA AHB, AMBA AXI, IEEE BSDL

Automation and Tools • Developed tools in Perl and C shell to automatically qualify a functional or a structural vector based on various quality metrics, for the Production Test Engineering (PTE) team. The tools were integrated with the Vector Processing System to reduce the costly ATE test-and-debug cycle and device characterization. • Enhanced the Qualcomm Memory Failure Analysis (QMFAT) database flow to precisely map the failing memory bit cell to the physical co-ordinates of a chip, providing vital information for yield improvement and memory fault diagnosis. Developed in Perl. • Implemented a pre-silicon verification tool in Perl to validate the QMFAT database accuracy using Synopsys Camelot. The tool expedited fault diagnosis. • Worked on development of a tracking tool with web interface - Quest (Qualcomm Simulation and Vector Readiness tracking system) to accurately report simulation, vector and phasing status of any project, providing forecast, risk assessment, health of a project and further planning. Developed Perl modules to interface with MySQL and PHP scripts.

Low Power verification and Gate-Level Simulation • Expertise in Unified Power Format (UPF) based RTL power aware and gate-level power aware verification. • Worked on Gate-level verification and environment bring-up, vector processing, silicon bring-up and post silicon debug of Snapdragon family of SoCs for various functional and structural sub-systems. • Memory BIST verification and vector generation for embedded memories of 5 sub-systems.

ACADEMIC PROJECTS AND THESIS

ATPG based circuit equivalence checking 2016 Developed an ATPG (Automatic Test Pattern Generation) based equivalence checker for combinational circuits, by transforming the equivalence checking problem to a satisfiability problem. Implemented in Python.

House price prediction using Regression Techniques 2016 Built a Lasso prediction model for predicting the house prices of individual residential properties sold in Ames, Iowa from 2006 to 2010. Achieved RMLSE of 0.144 and developed in Python and Weka.

M.Tech Thesis - Low voltage, low current and high efficiency power supplies 2011 Investigated low-voltage, low-current power supply design for sub-threshold circuits. Designed a Buck converter with a novel clock generator circuit to enhance the peak efficiency, thus improving battery longevity. Simulated with Synopsys HSPICE.

Reporting short and open circuits in a VLSI chip 2010 Short and open circuit connections in a VLSI layout are reported using Interval tree data structure and graphs, implemented in C.

Peer care- challenging the monitoring approach through embedded sensors. 2009 Detects anomalies in the behavior of elderly, children and patients using embedded strain gauges and a MATLAB processing engine. A sudden fall or inactivity alerts the caretaker.

ACTIVITIES AND HONORS

• Won 13 Qualstars at Qualcomm as recognition for contributions to automation solutions, post-silicon 2011-2015 execution and partnering with various cross-functional teams. • Best poster award for poster, “Characterization Access point Identifier”, QBUZZ 2011- The National 2011 conference at Qualcomm, India. • Recipient of Dean’s list awards in M.Tech for consistent academic performance in all semesters 2009-2011 • Second place in Motorola scholar awards for the project “Peer care – monitoring using embedded 2009 sensors” • First rank in Chemistry in statewide higher secondary (12th) examinations. 2005