NO9300001
UNIVERSITY OF OSLO
Building A Verilog Model for Boundary-Scan Architecture
by '"A Bin Wu and Gisle Midttun ål Department or Physics University of Oslo, P.O.Box 1048 Blindern N-0316 Oslo 3, Norway
UiO PHYS 92-40 Received: 1992-12-10 5* ISSN-0332-5571 .2É,
DEPARTMENT OF PHYSICS REPORT SERIES
n .ii m imH*11 Building A Verilog Model for Boundary-Scan Architecture
by Bin Wu and Gisle Midttun
Department or Physics University of Oslo, P.O.Box 1048 Blindern N-0316 Oslo 3, Norway
UiO PHYS 92-40 Received: 1992-12-10 ISSN-0332-5571 • Department al Phy»ic•, Univ.riily ol O.Io •
Building A Verilog Model for Boundary-Scan Architecture
By Bin Wu and Gisle Midttun
Abstract This article presents a short introduction of ANSI/IEEE Std. 1149.1(1 ][2], Boundary-Scan technique, as well as a model designed by Verilog HDL to implement the Boundary-Scan architecture. The idea of Boundary-Scan architecture provides a non-contact method of accessing chip pins during testing. The model implemented by Verilog is simple, but expresses the spirit of the standard very well. This model is compatible with the IEEE 1149.1 standard, thus provides the possibility of implementing it in the real world.
Po« B0« '04a a*ttwn 03160UO] Norway Building A Verilog Modet for Boundary-Scan Architecture (preliminary}
1. Introduction
The more and more widely used VLSI technology makes lest of chips and circuits more and more difficult and expensive.
In order to guarantee that the circuit or chip will function electrically, one needs to do some forms of electrical test. The (wo most common electrical test techniques are functional testing and in-circuil testingl 10)[ 111.
The principle of functional testing is to use a scries of input signals as stimuli, and the output responses arc measured and compared against acceptance limits. The in-circuil testing! 10] docs not check the performance of Ihe board as a whole but rather each component individually. The board is accessed by a series of probes (called a bed-of-nails fixture) that make contacl with all circuit nodes such that more failures can be found simultaneously. Test signals (vectors) arc measured, and compared with the expected truth table for the component, device, eic.
We have more and more gates in smaller and smaller chips, reduced pin spacings. more and more used SMT and multi-chip modules. This causes the traditional testing methods to become less cost-effective. The solution is lo turn to more advanced methods, such as the IEEE Sid. 1149.1 - Boundary-Scan. The effort of establishing IEEE Sid. 1149.1 began in 1985 |4] and was first formalized al the Joint Test Action Group (JTAG) in 1986 11 ]. Laic in 1987, the group developed lo be an IEEE working group. It is approved by the IEEE committee in Feb. 1990.
The Boundary-Scan technology provides us with two major new advantages. . non-conlacl method of accessing chip pins during testing. . separating chip icsl from interconnect lest.
Boundary-Scan adds a specialized test circuitry lo an IC design between Ihc pin and the logic lo which il is connected.
In the following section, ihc structure of the Boundary-Scan is introduced. Section 3 describes Ihc Vcnlog model we simulated and provides a more detailed description of Boundary-Scan technique. Section 4 shows the lest strategy and results of the tests. Section 5 presents the existing problems and a short discussion. Section 6 gives ihe conclusions.
2. An Overview of Boundary-Scan Architecture
The basic architecture is shown in Figure I. It places shifl-register-based cells between each chip pin (called Component Boundaries) and the on-chip logic. These cells arc called Boundary-Scan cells, and the path lhai connects them is called ihe Boundary -Scan path.
The Tosi Access Port iTAP) contains 4 pins.
• Test Data Input (TDD is the serial input to ihe lest logic by which lot or instruction data arc luidcd:
• Test Data Ouiput (TDO) IN the serial output of icsi or instruction uala f mm ihc tcsl logic
PAGE?Of '8 Building A Verilog Model for Boundary-Scan Architecture (preliminary)
• Test ClocK (TCK) is an independent system clock for the chip so that the test operations can be synchronized between the various chips on a printed circuit board.
• Test Mode Select input (TMS) is used together with TCK to form a 16-state state machine. The reason to implement this 16-state state machine is described in later sections.
Data can flow directly through the Boundary-Scan cell from Data Input to Data Output when normal operation of the component is required. During the testing mode, each test pattern that would have been applied to the IC*s inputs is shifted into the Boundary-Scan path. When the pattern is in place, the chip(s) is clocked once by TCK. The test response is then captured into the Boundary-Scan cells at the IC's output pins and shifted out for examination. The test pattern is shifted into the cells by the TD1 pin and the readout of the response data is via TDO.
Register & Comrollci
TDI TCK TMS TDO
Serial Out
Dala Input _ Dala Oulpul
From Register s& Controller
FIGURE 1. A Chto Modal wilh Boundarv-Scan Architoctufft Building A Verilog Model for Boundary-Scan Architecture (preliminary)
3. Verilog Model
3.1 Verilog HDL
"For large systems, gate-level design is dead" -Ray Weiss from E.E.Times said. Today, hard ware is becoming so complex that the traditional schematic design can show only a web of connectivity, not the ftinctionalily of the design. Engineers are therefore moving towards Hard ware Description Languages (HDLs). Al present, there are two dominant hardware description languages. Verilog|9| and VHDL. Since a lot of large scale hardware products were designed in Verilog. and also because Dolphin Server Technology and CERN. two of our most important partners use Vcrilog to design complex hardware, we decided to use Vcrilog as our designing tool for the models. We hope Ihal the model will be moved to the large scale hardware designs very easily.
3.2 Boundary-Scan Architecture Model
The model for Boundary-Scan Tcsl Access Port consists of a TAP Controller, an instruction register, a bypass register. Boundary-Scan cells and an output buffer, as shown in Figure 2. We will describe them in detail in later sections. The lightest shadowed area corresponds to the Register & Controller in Figure I.
P*CE • o* •• Building A Verilog Model for Boundary-Scan Architecture f preliminary)
TAP Controller (16 state state machine) 3=F
FIGURE 2. Boundaiv-Scan ArchrlBdura Test LOOK:
3.3 Model for Boundary-Scan TAP Controller
A lot of IGs arc pin limiicd. rather than silicon limited. In order lo keep ihc number of pins in the TAP to a minimum. IEEE Sid. 1149.1 specifies a 16-siate finite slate machine which is controlled hy only iwopirw. TC'K and TMS. reducing the 4 control pins in two. The trade-off is ca. MO jiaiev In today's VLSI world. Ihe benefit of this choice is obvious
The stale diagram of this stale machine w shown in Appendix I Building A Verilog Model for Boundary-Scan Architecture (preliminary)
^ Select
TMS ^ Enable TAP ^ CLOCK. PR __^UPDATE_DR Controller ^_SMFT_DR TCK ^.CLOCKJR UPDATEJR ^ SHIFT. IR
FIWHE 3. Blprt Piagfam of me TAP Cqniwugr Figure 3 shows the logical functionality, not a chip witti 10 pins. This controller shouid be buill in every hardware chip that implements the IEEE Std. 1 (49.1.
The outputs of TAP Controller control the operation of the lest logic.
3,4 Model lor Boundary-Scan Cell
A Boundary-Scan cell is basically a 4-terminal switch based around a shift-register stage. To comply with IEEE Sid. 1149.1. an tC must contain Boundary-Scan cells at all off-chip system inputs and outputs, sec Figure I and Figure 4.
The Data In line should he connected lo the input pin of ihe chip or the output line from Ihc on- ci.ip logic. The Data Oul should be connected to the oulpui pin of the chip or the input fine from Ihe on-chip logic. This kind of connections may cause different designs of ihe cells for in put pins and output pins. Note that the cell mi Kiel in Figure S is for input puis or output pins only, wc might also need lo design a more complicated model lor both input and output of lesi dala. since some of Ihe pins might be bidirectional. Some examples ;ue given in |6|.
Trie Serial In and Serial Oul is functioned as the connections between i wo cells. They are ihc paths thai test data can be serial transferred to respective cells. If is uhvmusly thai the first cell's Serial In should be connected to the TDI pin and (he Senal Out to the TIX) pin (via mul tiplexer and buffer).
wee 8 o*'« Building A Veritog Model for Boundary-Scan Architecture (preliminary)
The other pins are driven by the TAP Controller. In the Figure 4. the Shift/Load is driven by SHIFT.DR. the Clock is driven by CLOCK_DR. and Ihc Update by UPDATE_DR.
FIGURE 4 A Simple Boundary-Scan Cell Model
One should notice thai this Boundary-Scan cell model is very simple ;md typical general-pur posed. We can design a simpler or more complicated cell for different purpose! 2|.
3.5 Instruction R tg Ister (IR) The instruction in IR determines the registers lo be selected and their usage. We only intend to implement a basic set of standard, so only a few instructions will be used. These are the three mandatory instructions. BYPASS. SAMPLE^RELOAD and EXTEST. Other optional instruc tions arc not implemented due to ihc lime constrains of this project. The instruclions arc listed in Table I. We decided to design a three-cell IR (Actually two IR cells arc enough for J instruc tions. Using tfucc is just preparation for the future expansion). Each cell KUIMSI.S of a Shift Register stage and a latch stage as shown in Figure V
Table I: Instructions
Ojx.odc Name Comment
III BYPASS Chtxisc Ihc Bypass register and do nothing.
IKll SAMPLE/ Boundary-Si an register sam PRELOAD ple* inputs and milpuls
IK») EXTEST Boundary-Stan register applies test to external inter- conncit and/of emuilrv Building A Verilog Model for Boundary-Scan Architecture (preliminary)
Upon coming in to the CaptureJR state in stale-machine, the CLOCK JR signal from the TAP controller will capture data into the D-flip-flops (see Appendix 2), ShiftRcgl (SRI) retains its previous value while SR2 and SR3 are loaded with "0" and "1" respectively. Upon receiving a SHIFT_DR, the value of TDI shifts into SRI. SRI lo SR2.and SR2 lo SR3 which is observa ble on TDO. The values of Shifl_Regs are latched in to the Latches on receiving of UPDATE_- DR from TAP Controller. The output of the Latches can be decoded lo control the Boundary- Scan cells, or just choose the bypass register (K = 000). or do EXTEST ShiflRcgl ShiftRcg2 ShiflRcgjI TDI "%0 Ulch 1 Ulch 2 Latch 3 1 1 ' 1 I DECODER To Test Data Register FIGURE 5. A Modal ol Instruction Register O-bitl Detailed design in gate level vs shown in Appendix 2. 3.6 Bypass Register A bypass register is a smglc-hil connection from TDI to TDO to allow test dala lo How through to other components with a single TCK pertixi delay. Il musi be included Ui conform lo IEEE Sid I Ml> I The benefit of using bypass register is obvious. Think that we have two ICs as in Figure X. all with Boundary-Scan cells connected. Wc of course arc not interested in shifting second IC's data through first IC, Wc are in ihc same situation when wc want lo shift data lo the second ICs text data out pin. we do not want Ihc dala in IC I go through IC 2's Boundary- Scan cells. By applying bypass rcgisier. wc save almo-it HW& shift odes The more ICs arc tonnet led, the much benefit wc gel. An example of bypass register is shown in Figure fv When the IK tt tn Bypass Mode (Code 111 > and in the Capture,DR state of ihc slate machine, receiving the signal CLOCK_DR from TAP Controller, a "0" is stored in Ihc flip-flop: upon receiving a SHUT DR from TAP Con troller, the value {mm TDI is stored in flip-flop and is consequently obscrvjblc on the TDO output, .i I PDATE DR has no effect °*G« so' •» Building A Verilog Model for Boundary-Scan Architecture (preliminary) .MUX TP° >CP Shift/Load* n Clock TDI FIGUHF 6. Model for Bypass Register 3.7 Example Model for A Simple Circuit Wc designed a very simple 3X8 decoder and a compliment of il, a simple 8X3 encoder, as in Figure 7. The complimcnl characteristic? of these two chips made il very easy for ihc test at inputs and outputs, (hey should logically be Ihc same (Il seems chat wc arc using functional testing in verify our Boundary-Scan TAP design). The function tables of the chips arc xs following: 3.7.1 chip 1 (74LS138 compatibly ••• appendix 3) 3.7.2 chip2(74LS14acomp«Hbl«, M« appandix 4) 3.7.3 Comment* This example is very simple, the most suitable tcsiing method is probably IUIK•nona] lest. Bul wc just want (o show and lest Ihe idea of the Boundary-Scan architecture, so using this circuit as the example is not loo bad. To make Ihings more clearly, we will not consider ihe enable pins in the examples and description* below **« »0* '« Building A Verihg Model for Boundary-Scan Architecture (preliminary) Input A Out A 3X8 8X3 Input B Decoder Encoder OutB Input C OutC I FIGURE 7. 3X8 Decoder Connected with 8X3 Encoder 3.7.4 IC With Boundary-Scan Cells After wc implemented Boundary-Scan cells to boih chips, us shown in Figure 8. wc finished our modeling. FIGURE 8, The Who!» Modal Wc implemented ihe minimal sci of ihe IEEE Std. Il«W. 1. Thai mean-, wc warn to keep with the standard, nul due m ihe limited man-pnwcr wc can pour in. wc can noi implement options such as add a device idcmtficulHNi wgwier. eic P»G5 -0O* tfl Building A Verilog Model for Boundary-Scan Architecture (preliminary) 4. Test Strategy and Results 4.1 Phase 1: testing chlpl The testing of chip 1 can be done by either reset mode = 0 (see Figure 3) and apply data to the three input pins and observe data at output pins. i.e. without using Boundary-Scan cells, or by using Boundary-Scan cells to shift in and shift out test data. The steps are as following: Step I. Go from "Reset state" lo "Shift_IR stale" (see Appendix I); Slcp 2. Use 6 cycles lo shift in instruction (SAMPLE/PRELOAD) lo chipl and chip2 respec tively and update the instructions; Slcp 3. Change stale to Shift_DR and shift in 22-bit data from TDl. the example data is I lOxxxxxxxxxxxxxxxxxxx and update the data: Step 4. Use 6 cycles to shift in iwo instructions (EXTEST. cause mode = 1) lo chip I and chip2 respectively and update the instructions: Slep 5. Wail enough cycles to lei Ihe on-chip logic perform its funclion; Step 6. Use -slate Shift.DR again lo shift ihc date out lo TDO on chip2. The corrcci daia ob servable at TDO should be xxxlllOllllxxxxxxxxxxx 4.2 Phase 2: testing chlp2 Using the steps from last section, but with different lest data input xxxxxxxxxxxlllOllllxxx and check die observable data at TDO is corrcci or not. The output should be xxxxxxxxxxxxxxxxxxxOfI 4.3 Phase 3: testing the links between the chip (the 8-bit path) By careful selection of lest pallcrns. the interconnections can be tested lor stuck-at. short- circuit, opcn-circuil. and olher fault types. PAGE 11 OF 16 Building A Verilog Model for Boundary-Scan Architecture (preliminary) Figure 9 shows a fault circuit, with a "short bridge" fault between pin 8 and pin 9 of 3X8decodcr and a "short to ground" fault at pin 11. FIGURE 9. Two Faults of the External Connections Table 2 shows the test vectors lo separate such failles. Table 2: Test Vectors for Faults Input Expected out Fault out xlOxOxxx xlOxOxxx xOOxOxxx xOlxIxxx xOlxlxxx xOOxOxxx 4.4 Verifying The Total Design The objective of Ihe decoder and encoder design is to send a 3-bii binary code to die inpul pins of 3x8 decoder and observe the same result, a 3-bii binary code at the output pins of the 8x3 encoder. Wc can send in the data HOxxxxxxxxxxxxxxxxxxx from TDI and observe at TDO the expected dala xxxxxxxxxxxxxxxxxxxOll. But after step 5 of Phase I. we have lo let chip2's mode = 0 so thai Ihc data from output pins of Ihc decoder can be transferred to the input of the encoder, then wc should wait again lo let Ihc encoder perform ihe function. By using normal mode (0) operation, wc can send data 11 PAGE i J OF iB Building A Verilog Model for Boundary-Scan Architecture (preliminary) combination of using data input, output pins with the test data input and output pins, can also be used (o perform a lot of tests. By now, we have used Verilog model to simulate the decoder-encoder logic as well as the Boundary-Scan architecture. 5. Problems and Discussions We can sec that Boundary-Scan technology is simple and cost effective in testing. It provides an effective way of testing high-density and poor-access ICs. While we benefits from Boundary-Scan icchnology, we also encounter some problems such as the cost of additional circuitry, additional pins. Normally for a 40 pins IC with minimal set of IEEE std. 1149.1 implementation, around 900 extra gates will be need. To ICs with more than 10 thousand gates, this overhead is tolerable from the gale-cost of view, and normally there will be free space on the chip for these extra gates. To some of the ICs mat arc pin limited, the penalty of 4 additional TAP pins is deadly. Other penalties include added delays because of extra lines and gales linked to the Boundary- Scan cells. This also means worse high frequency characteristics which might bother tomor row's high speed digital world. The lest speed that is much lower than ihe normal operational speed will lower the reliability of tests. The Boundary-Scan technology focuses on digital chips only, but somt. methods that using Boundary-Scan technology lo lest the mixed analog/digital circuit is explored in|71|8|. After all. we found that in order to implement Boundary-Scan technology to complicated 1C testing, one still has to be very familiar with the details such as slate-diagram of (he TAP Con troller and some efforts need lo be done lo lind the best test strategy. But we can minimize the users involvement by user-friendly interface on the computer terminal, such as window inter faces clc. It will be very effective if these interfaces can provide users with transparence of state diagram in the TAP Controller and different information of ihc rcgi.sicrs and controllers. 6. Conclusions Boundary-Scan architecture provides us with a cost-effect ivc and simple way lo solve parts of Ihc testing and proofing problems of the electronic design. It giv -.. a 100% sluck-al and bridging fault coverage of board interconnections. The standardization nf the idea (IEEE std. 1149.1) made it more flexible and cheaper. One can gel a wide choices from ;i bulk of vendors. From this article, one can sec Ihc advantages of the Boundary-Scan technique over the traditional in-circuit tcsl or functional lest. A small Vcrilog model showed the possibility of implementing Boundary-Scan architecture in very simple way. MOE 13 OF >8 Building A Verilog Model for Boundary-Scan Architecture (preliminary} 7. Notes This paper is very preliminary. A lol of work needs to be done. The purpose is just to start the work of the Boundary-Scan Architecture research in Ihe Department of Physics at the Univer sity of Oslo. This project is related lo the course FYS-323 in the Department of Physics. University of Oslo. Il takes one man-month's job to fulfill the Verilog code and this article. A ckno wtedgment The administration work of Bernhard Skaali is greatly appreciated. References 1. IEEESTD. 1149.1 Working Group. lEEEStd. 1149.1 The Test Access Port and Boundary- Scan Air hitecture.1 2. The Joint Test Action Group, A Standard Boundary-Scan Architecture-Draft J. September 198o. 3. A.T. Dahhura. M.U. Uyar, C.W. Yau. An Optimal Test Sequence for the JTAGHEEE PI 149 I Test Access Port Controller IEEE Proceedings 1989 International Test Confer ence. Pages 55-62. 4. CM. Maunder. R.E. Tulloss. The Test Access Port and Boundary-Scan Architecture. IEEE Computer Society Press. 1990. 5. CM. Maunder Testability standards Euro ASIC-92 Tutorials A-B-C.Sunc 1.1992 6. F.P.M. Bccnkcr, Systematic and Structured Methods far Digital Board Testing IEEE 1985 International Test Conference Proceedings. Page 380-385. 7. P.P. Fasang, Design for Testability for Mixed Analog/Digital ASICs Proceedings of the I98H IEEE Custom Integrala! Circuit Conference. May 1988. Rochester. NY. K. P.P. Fasang. Boundary-Scan and its Application to Analog-Digital ASK' Testing in a Board! .S'vsirm Environment. Proceedings o(the 19R9 IEEE Custom Integrated Circuit Conference, page 22.4.1-22.4.4 9. E. Slcmhcim. R. Singh, Y. Tnvedt. Digital Design »ith Venlog HDL. Automata Publishing Company. 1990 10.Faction Schlumbcrgcr. The Primer of High-Performance In-Cmuit h:\ttnit. Faciron Sch- lumhcrgcr. Wimhomc. Dnncl. UK. 19H5 II. J. Max Conner. Digital Test Engineering. Jirfui Wiley & Sons. Inc.. 1987 I Cupie-mf I he %t jndjf d mjy te ohtjiix-tl Irom IEEE Slun PACE '« OF '8 Building A Verilog Model for Boundary-Scan Architecture (preliminary) R r\ 9:r~\ X Si 6 ,! ~\ ULI •**. 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