NO9300001 UNIVERSITY OF OSLO Building A Verilog Model for Boundary-Scan Architecture by '"A Bin Wu and Gisle Midttun ål Department or Physics University of Oslo, P.O.Box 1048 Blindern N-0316 Oslo 3, Norway UiO PHYS 92-40 Received: 1992-12-10 5* ISSN-0332-5571 .2É, DEPARTMENT OF PHYSICS REPORT SERIES n .ii m imH*11 Building A Verilog Model for Boundary-Scan Architecture by Bin Wu and Gisle Midttun Department or Physics University of Oslo, P.O.Box 1048 Blindern N-0316 Oslo 3, Norway UiO PHYS 92-40 Received: 1992-12-10 ISSN-0332-5571 • Department al Phy»ic•, Univ.riily ol O.Io • Building A Verilog Model for Boundary-Scan Architecture By Bin Wu and Gisle Midttun Abstract This article presents a short introduction of ANSI/IEEE Std. 1149.1(1 ][2], Boundary-Scan technique, as well as a model designed by Verilog HDL to implement the Boundary-Scan architecture. The idea of Boundary-Scan architecture provides a non-contact method of accessing chip pins during testing. The model implemented by Verilog is simple, but expresses the spirit of the standard very well. This model is compatible with the IEEE 1149.1 standard, thus provides the possibility of implementing it in the real world. Po« B0« '04a a*ttwn 03160UO] Norway Building A Verilog Modet for Boundary-Scan Architecture (preliminary} 1. Introduction The more and more widely used VLSI technology makes lest of chips and circuits more and more difficult and expensive. In order to guarantee that the circuit or chip will function electrically, one needs to do some forms of electrical test. The (wo most common electrical test techniques are functional testing and in-circuil testingl 10)[ 111. The principle of functional testing is to use a scries of input signals as stimuli, and the output responses arc measured and compared against acceptance limits. The in-circuil testing! 10] docs not check the performance of Ihe board as a whole but rather each component individually. The board is accessed by a series of probes (called a bed-of-nails fixture) that make contacl with all circuit nodes such that more failures can be found simultaneously. Test signals (vectors) arc measured, and compared with the expected truth table for the component, device, eic. We have more and more gates in smaller and smaller chips, reduced pin spacings. more and more used SMT and multi-chip modules. This causes the traditional testing methods to become less cost-effective. The solution is lo turn to more advanced methods, such as the IEEE Sid. 1149.1 - Boundary-Scan. The effort of establishing IEEE Sid. 1149.1 began in 1985 |4] and was first formalized al the Joint Test Action Group (JTAG) in 1986 11 ]. Laic in 1987, the group developed lo be an IEEE working group. It is approved by the IEEE committee in Feb. 1990. The Boundary-Scan technology provides us with two major new advantages. non-conlacl method of accessing chip pins during testing. separating chip icsl from interconnect lest. Boundary-Scan adds a specialized test circuitry lo an IC design between Ihc pin and the logic lo which il is connected. In the following section, ihc structure of the Boundary-Scan is introduced. Section 3 describes Ihc Vcnlog model we simulated and provides a more detailed description of Boundary-Scan technique. Section 4 shows the lest strategy and results of the tests. Section 5 presents the existing problems and a short discussion. Section 6 gives ihe conclusions. 2. An Overview of Boundary-Scan Architecture The basic architecture is shown in Figure I. It places shifl-register-based cells between each chip pin (called Component Boundaries) and the on-chip logic. These cells arc called Boundary-Scan cells, and the path lhai connects them is called ihe Boundary -Scan path. The Tosi Access Port iTAP) contains 4 pins. • Test Data Input (TDD is the serial input to ihe lest logic by which lot or instruction data arc luidcd: • Test Data Ouiput (TDO) IN the serial output of icsi or instruction uala f mm ihc tcsl logic PAGE?Of '8 Building A Verilog Model for Boundary-Scan Architecture (preliminary) • Test ClocK (TCK) is an independent system clock for the chip so that the test operations can be synchronized between the various chips on a printed circuit board. • Test Mode Select input (TMS) is used together with TCK to form a 16-state state machine. The reason to implement this 16-state state machine is described in later sections. Data can flow directly through the Boundary-Scan cell from Data Input to Data Output when normal operation of the component is required. During the testing mode, each test pattern that would have been applied to the IC*s inputs is shifted into the Boundary-Scan path. When the pattern is in place, the chip(s) is clocked once by TCK. The test response is then captured into the Boundary-Scan cells at the IC's output pins and shifted out for examination. The test pattern is shifted into the cells by the TD1 pin and the readout of the response data is via TDO. Register & Comrollci TDI TCK TMS TDO Serial Out Dala Input _ Dala Oulpul From Register s& Controller FIGURE 1. A Chto Modal wilh Boundarv-Scan Architoctufft Building A Verilog Model for Boundary-Scan Architecture (preliminary) 3. Verilog Model 3.1 Verilog HDL "For large systems, gate-level design is dead" -Ray Weiss from E.E.Times said. Today, hard­ ware is becoming so complex that the traditional schematic design can show only a web of connectivity, not the ftinctionalily of the design. Engineers are therefore moving towards Hard­ ware Description Languages (HDLs). Al present, there are two dominant hardware description languages. Verilog|9| and VHDL. Since a lot of large scale hardware products were designed in Verilog. and also because Dolphin Server Technology and CERN. two of our most important partners use Vcrilog to design complex hardware, we decided to use Vcrilog as our designing tool for the models. We hope Ihal the model will be moved to the large scale hardware designs very easily. 3.2 Boundary-Scan Architecture Model The model for Boundary-Scan Tcsl Access Port consists of a TAP Controller, an instruction register, a bypass register. Boundary-Scan cells and an output buffer, as shown in Figure 2. We will describe them in detail in later sections. The lightest shadowed area corresponds to the Register & Controller in Figure I. P*CE • o* •• Building A Verilog Model for Boundary-Scan Architecture f preliminary) TAP Controller (16 state state machine) 3=F FIGURE 2. Boundaiv-Scan ArchrlBdura Test LOOK: 3.3 Model for Boundary-Scan TAP Controller A lot of IGs arc pin limiicd. rather than silicon limited. In order lo keep ihc number of pins in the TAP to a minimum. IEEE Sid. 1149.1 specifies a 16-siate finite slate machine which is controlled hy only iwopirw. TC'K and TMS. reducing the 4 control pins in two. The trade-off is ca. MO jiaiev In today's VLSI world. Ihe benefit of this choice is obvious The stale diagram of this stale machine w shown in Appendix I Building A Verilog Model for Boundary-Scan Architecture (preliminary) ^ Select TMS ^ Enable TAP ^ CLOCK. PR __^UPDATE_DR Controller ^_SMFT_DR TCK ^.CLOCKJR UPDATEJR ^ SHIFT. IR FIWHE 3. Blprt Piagfam of me TAP Cqniwugr Figure 3 shows the logical functionality, not a chip witti 10 pins. This controller shouid be buill in every hardware chip that implements the IEEE Std. 1 (49.1. The outputs of TAP Controller control the operation of the lest logic. 3,4 Model lor Boundary-Scan Cell A Boundary-Scan cell is basically a 4-terminal switch based around a shift-register stage. To comply with IEEE Sid. 1149.1. an tC must contain Boundary-Scan cells at all off-chip system inputs and outputs, sec Figure I and Figure 4. The Data In line should he connected lo the input pin of ihe chip or the output line from Ihc on- ci.ip logic. The Data Oul should be connected to the oulpui pin of the chip or the input fine from Ihe on-chip logic. This kind of connections may cause different designs of ihe cells for in­ put pins and output pins. Note that the cell mi Kiel in Figure S is for input puis or output pins only, wc might also need lo design a more complicated model lor both input and output of lesi dala. since some of Ihe pins might be bidirectional. Some examples ;ue given in |6|. Trie Serial In and Serial Oul is functioned as the connections between i wo cells. They are ihc paths thai test data can be serial transferred to respective cells. If is uhvmusly thai the first cell's Serial In should be connected to the TDI pin and (he Senal Out to the TIX) pin (via mul­ tiplexer and buffer). wee 8 o*'« Building A Veritog Model for Boundary-Scan Architecture (preliminary) The other pins are driven by the TAP Controller. In the Figure 4. the Shift/Load is driven by SHIFT.DR. the Clock is driven by CLOCK_DR. and Ihc Update by UPDATE_DR. FIGURE 4 A Simple Boundary-Scan Cell Model One should notice thai this Boundary-Scan cell model is very simple ;md typical general-pur­ posed. We can design a simpler or more complicated cell for different purpose! 2|. 3.5 Instruction R tg Ister (IR) The instruction in IR determines the registers lo be selected and their usage. We only intend to implement a basic set of standard, so only a few instructions will be used.