Ultra-Compact Uc1394a-1 Multi Chip Module Overview

ultra-compact UC1394a-1 multi chip module overview

Ultra-compact UC1394a-1 single device IEEE1394a / DSP / FPGA solution

Key features

Plug and play: · Various interfaces like UART, 3x McBSP, · Highly integrated embedded plug and play ® USB1.1 (slave), I2C, 4 channel ADC etc. to IEEE1394 (FireWire ) multi chip module connect further peripheral devices · Enabling virtually any device to · Real time clock (RTC) communicate via IEEE1394 with only one · 27 free FPGA I/O pins, user configurable component internal FPGA logic · No detailed knowledge necessary about · Ultra-compact UC1394a-x multi chip IEEE1394 to run a fully standard compliant module pinning, though upward pin- embedded IEEE1394 network compatible with the entire family · No IEEE1394 software development · Extreme highly integrated multi chip module necessary due to available IEEE1394 (MCM) technology, dimensions only 30 x 36 Bridging Kit x 7 mm (1.18 x 1.41 x 0.28 in) · Capable to work like a “IEEE1394-tunnel” · Several EVM kits available which either that bridges application raw data from a focus on generic data streaming, camera user accessible hardware transmit FIFO to applications or harddisk storage another bus member´s hardware receive

FIFO within the IEEE1394 network · Excellent real time behavior Software: · Fully IEEE1394a standard compliant, · Shipped with installed IEEE1394 Bridging therefore compatible to other existing software if desired, ready-to-use IEEE1394 networks and components · Simple network setup by PC configuration tool over RS232 possible Hardware: · PC-side software API for IEEE 1394 Bridging available · 2-port 400 Mbit/s IEEE 1394a (FireWire®) · Various Board Support Packages (BSP) communication / repeater - interface allow further module operations (e.g. Bi-directional (half duplex) IEEE1394a · McBSP to IEEE1394 interfacing, camera to operation IEEE1394 interfacing, digital image · 16 bit external hardware streaming processing, digital signal processing, etc.) interface with 4 kbyte FIFO buffering · EVM kits include embedded IEEE1394 · 50 kGate Xilinx FPGA enables sustained software drivers (API) for several protocols (isochronous) raw data streaming up to 32 like Generic Streaming API, DCAM Frame Mbyte/s Capture API or DCAM Camera API · 16 bit high performance Texas Instruments · Complete FPGA and software development DSP TMS320C5509a-200 MHz tool packages available · 8 Mbyte SDRAM, 512 kbyte Flash EPROM

Multiple operation modes · The ultra-compact UC1394a-1 offers a wide Applications range of operation modes · High speed real time networking · Can be used as a turnkey IEEE 1394a · High speed real time data broadcasting (FireWire®) solution for high speed real time · High speed real time interface bridging data streaming or data bridging · CCD to IEEE1394 interfacing · In combination with the corresponding · Frame grabber for IEEE1394 cameras Bridging BSP, the module is a direct · Harddisk interfacing Interface between an IEEE 1394 network · Industrial automation and control and several local hardware interfaces like · Industrial imaging parallel bus, RS232, I/O pins etc · High level IEEE1394 protocol · In combination with the corresponding implementation such as DCAM or SBP-2 DCAM Frame Capture BSP, the module · Real time DSP and FPGA data processing can directly be used as an intelligent frame grabber for standard IEEE1394 digital cameras · In combination with the corresponding DCAM Camera BSP, the module can make an IEEE1394 camera out of a CCD sensor or a non-IEEE1394 camera · In combination with the corresponding DSP Development BSP, the module can be used as a general purpose DSP, FPGA, IEEE1394 hardware platform which allows individual software programming, FPGA configuration and external I/O component expansion

Customer benefits · The ultra-compact UC1394a-1 device offers the opportunity to directly reduce time to market · It dramatically reduces development costs · It maximizes customer system creativity and minimizes highly sensitive subsystem design · It enables a single component ultra small size IEEE1394 network

· No IEEE1394 software development

necessary due to available IEEE1394

Bridging Kit

· DSP and FPGA reloadable for application

specific software/hardware needs

· Directly solderable PLCC component allows cost efficient machine series production

without the need of expensive plug-in

connectors

· Produced according to ISO 9001:2000 · CE-qualification ensures first-class product performance and industrial quality · Attractive OEM quantity pricing · Ultra-compact UC1394a-x devices are the perfect target hardware for system development, prototyping and volume production

General description The ultra-compact UC1394a-1 represents the first member of a product family which basically enables the user to run an ultra fast real time IEEE1394 (FireWire®) network without the need of detailed IEEE1394 hardware or software knowledge. This allows the application engineer to quickly realize fast 400 Mbit/s IEEE1394 network connections between his application and other IEEE1394 platforms like PC´s, cameras, harddisks, other embedded systems, etc. If for example IEEE1394-camera high protocol level interfacing is needed, then higher level protocols like DCAM (digital IEEE1394 camera specification) can be implemented. This is possible by adding a specific board support package (BSP) which includes the necessary software and FPGA variant for the specific application. With this philosophy a large number of application specific needs can be solved due to the growing number of BSP solutions in the future. Possible examples are: McBSP to IEEE1394 interfacing, various CCD to IEEE1394 interfacing, digital image processing, digital signal processing etc. The ultra-compact UC1394a-1 onboard software can furthermore completely be deactivated and individually be replaced by a customer specific software. This is possible by connecting complete software development tools as well as FPGA design tools to the UC1394a-1. Implementing, debugging and storing alternative software and FPGA versions is fully supported by download- and boot- handling tools. The ultra-compact UC1394a-1 device is highly performance- and size- optimized by using modern silicon and multi chip module (MCM) technology. Mechanically it is designed as a PLCC component which enables the device to be assembled by a standard reflow soldering process. Thus there are no additional connectors required and no assembly post-processes necessary.

The TMS320VC5509a DSP The TMS320VC5509a is a new member of the Texas Instruments C55xx DSP family and is available with a clock speed up to 200 MHz. It combines low power, high performance signal processing and various interfaces with low costs. It is based on the 16 bit wide C55xx fixed point processing core and provides an internal 256 kbyte memory. The 16 bit wide external memory interface is able to address up to 16 Mbytes of various RAM types Furthermore, the TMS320VC5509a provides various interfaces like 3 McBSPs, I2C, USB, RTC, Timers, ADC or JTAG emulation interface.

The Xilinx SPARTAN II FPGA The 50 kGate Xilinx SPARTAN II FPGA with its integrated high speed memory basically provides up to 4 kbyte IEEE1394 FIFO, as well as IEEE1394 data path logic to ensure a sustained isochronous IEEE1394 bandwidth up to 32 Mbyte/s. The external hardware streaming interface is directly handled by the FPGA without the need of processor software overhead. Additionally the UC1394a-1 UART is a soft UART inside the FPGA. If application specific hardware functionality is required, there are 27 free configurable FPGA user I/O lines which can, in combination with a huge amount of remaining internal FPGA resources, be fitted to nearly any application.

Software support The ultra-compact UC1394a-1 is available with installed Orsys Bridging software that enables plug and play operation of IEEE1394 isochronous raw data streaming. If further operation is required, then several BSPs are available which allow the device to enlarge off the shelf solutions for different user requirements. If even BSPs do not fit into the user´s requirements then it is possible for the user to build completely project specific software and FPGA versions with only parts or without the use of existing Orsys firmware. In this case, complete software and FPGA development tool packages, including Xilinx VHDL tools, TI Code Composer Studio and emulation hardware, are available. Additionally the provided download tools guarantee optimum individual software and FPGA downloading and handling.

Block diagram

Pin connectors (3.3 Volt) Reset: 2 lines Power: 16 lines Power Reset Manager Generator I2C bus: 2 lines UART: 4 lines RTC clock: 2 lines User I/O: 27 lines AD-Converter: 4 lines McBSP 0, 1, 2: 18 lines Streaming interface: 16 data, 5 control lines

TMS320C5509 SDRAM Xilinx FPGA JTAG up to 200 MHz 8 Mbyte 50 Kgates I/F EMIF (BUS)

FLASH 512 kbyte

JTAG USB1.1 mC I/F DM I/F 1394 port 0 I/F slave Link Layer PHY Layer TSB12LV32 TSB41AB2 1394 port 1

Ultra-compact UC1394a-1

The ultra-compact UC1394a-1 mainly consists of the TMS320C5509a DSP, the Xilinx SPARTAN II FPGA and the IEEE1394a chipset, combined of the Link Layer Controller and the Physical Layer Controller. There are several additional features implemented like a 8 Mbyte SDRAM and a 512 kbyte Flash memory. Both enable a huge amount of program or data to be stored on the device which allows a wide field of applications like image processing, algorithm processing, etc. Several environment functions like a power manager or a reset generator complete the device to a fully stand alone system.

The TMS320C5509a processor has a number of onboard interfaces like USB, McBSP, I2C, etc. which are directly wired to PLCC pin connectors of the device. The FPGA has also a number of lines which are directly connected to external PLCC pin connectors such as the isochronous streaming interface, the 4 UART lines or the 27 free user I/O lines.

UC1394a-1 top view

PCBV1.0 07/02 35.81 C1 C32 A1 B1 29.72

A26 B26 D1 D32 top view all dimensions in millimeters

UC1394a-1 bottom view

PCBV1.0 07/02 R34

bottom view

Pin A B C D 1 +3.3V +3.3V McBSP1_DR 1394_PORT1_TPB- (PWR) (PWR) (I/O) (DIFF I/O) 2 GND GND McBSP1_DX 1394_PORT1_TPB+ (PWR) (PWR) (OUT) (DIFF I/O) 3 McBSP0_DR STREAMING_D0 McBSP1_CLKR 1394_PORT1_TPA- (IN) (I/O) (I/O) (DIFF I/O) 4 McBSP0_DX STREAMING_D1 McBSP1_CLKX 1394_PORT1_TPA+ (OUT) (I/O) (I/O) (DIFF I/O) 5 McBSP0_CLKR STREAMING_D2 McBSP1_FSR GND (I/O) (I/O) (I/O) (PWR) 6 McBSP0_CLKX STREAMING_D3 McBSP1_FSX FPGA_I/O_5 (I/O) (I/O) (I/O) (I/O) 7 McBSP0_FSR STREAMING_D4 GND FPGA_I/O_6 (I/O) (I/O) (PWR) (I/O) 8 McBSP0_FSX STREAMING_D5 McBSP2_DR FPGA_I/O_7 (I/O) (I/O) (I/O) (I/O) 9 /RESET_OUT STREAMING_D6 McBSP2_DX FPGA_I/O_8 (OUT) (I/O) (OUT) (I/O) 10 /RESET_IN STREAMING_D7 McBSP2_CLKR FPGA_I/O_9 (OC I/O) (I/O) (I/O) (I/O) 11 GND GND McBSP2_CLKX FPGA_I/O_10 (PWR) (PWR) (I/O) (I/O) 12 FPGA_I/O_0 STREAMING_D8 McBSP2_FSR FPGA_I/O_11 (I/O) (I/O) (I/O) (I/O) 13 FPGA_I/O_1 STREAMING_D9 McBSP2_FSX FPGA_I/O_12 (I/O) (I/O) (I/O) (I/O) 14 FPGA_I/O_2 STREAMING_D10 GND FPGA_I/O_13 (I/O) (I/O) (PWR) (I/O) 15 FPGA-I/O_3 STREAMING_D11 JTAG_DSP_EMU1 FPGA_I/O_14 (I/O) (I/O) (IN) (I/O) 16 FPGA_I/O_4 STREAMING_D12 JTAG_DSP_EMU0 FPGA_I/O_15 (I/O) (I/O) (IN) (I/O) 17 UART_TxD STREAMING_D13 /JTAG_DSP_TRST FPGA_I/O_16 (OUT) (I/O) (IN) (I/O) 18 UART_RxD STREAMING_D14 JTAG_DSP_TCK GND (IN) (I/O) (IN) (PWR) 19 /UART_RTS STREAMING_D15 JTAG_DSP_TDO FPGA_I/O_17 / RTC (OUT) (I/O) (OUT) (I/O) 20 /UART_CTS GND JTAG_DSP_TDI FPGA_I/O_18 / RTC (IN) (PWR) (IN) (I/O) 21 GND /STREAMING_WE JTAG_DSP_TMS FPGA_I/O_19 / RTC (PWR) (IN) (IN) (I/O) 22 1394_PORT0_TPA+ /STREAMING_RE JTAG_FPGA_TCK FPGA_I/O_20 (DIFF I/O) (IN) (IN) (I/O) 23 1394_PORT0_TPA- STREAMING_CLK JTAG_FPGA_TDO FPGA_I/O_21 (DIFF I/O) (IN) (OUT) (I/O) 24 1394_PORT0_TPB+ /STREAMING_AEF JTAG_FPGA_TDI FPGA_I/O_22 (DIFF I/O) (OUT) (IN) (I/O) 25 1394_PORT0_TPB- /STREAMING_AFF JTAG_FPGA_TMS FPGA_I/O_23 (DIFF I/O) (OUT) (IN) (I/O) 26 +3.3V +3.3V DSP_XF1 FPGA_I/O_24 (PWR) (PWR) (OUT) (I/O) 27 - - FPGA_I/O_26 FPGA_I/O_25 (I/O) (I/O) 28 - - GND GND (PWR) (PWR) 29 - - AIN_0 USB_DP (ANALOG IN) (DIFF I/O) 30 - - AIN_1 USB_DN (ANALOG IN) (DIFF I/O) 31 - - AIN_2 I2C_SDA (ANALOG IN) (OC I/O) 32 - - AIN_3 I2C_SCL (ANALOG IN) (OC I/O)

ultra-compact pinout scheme

Pin row A: This pin row is part of the ultra compact standard pinning and is pin compatible through all devices.

Pin row A includes 6 basic types of signals: 1. One McBSP synchronous serial interface 2. One UART asynchronous serial interface 1. One differential 1394 port 2. Reset in / out lines 3. Five auxiliary I/O lines 4. Power supply

+3.3V: Power Supply +3.3V

GND: Ground

McBSP0_DR: Data receive input line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP0_DX: Data transmit output line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP0_CLKR: Clock receive input/output line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP0_CLKX: Clock transmit input/output line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP0_FSR: Frame sync receive input/output line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP0_FSX: Frame sync transmit input/output line of the first McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

/RESET_OUT: Active low reset output line of the onboard reset logic.

/RESET_IN: Active low reset input line of the onboard reset logic. This line can also become open collector output when an onboard reset trigger occurs. External reset drivers to this pin should always be open collector, not push-pull drivers. External signals to this pin do not need to be de-bounced.

FPGA_I/O_0 to 4: FPGA I/O lines 0 to 4. These lines are directly connected to the onboard FPGA. They can be configured to be either digital input or output. To ensure compatibility to other ultra-compact products it is recommended to use them as software programmable general purpose digital input/output lines only. However, they can be used as digital I/O lines for application specific FPGA logic as well. In this case, compatibility to other ultra-compact products can not be guaranteed.

UART_TxD: UART transmit data output line. This pin is directly connected to the FPGA. The UART is realized as a soft component inside the FPGA. There is no RS232 line driver onboard. An external RS232 line driver is required when communication to another RS232 system (like a PC) is needed.

UART_RxD: UART receive data input line. This pin is directly connected to the FPGA. The UART is realized as a soft component inside the FPGA. There are no RS232 line drivers onboard. An external RS232 line driver is required when communication to another RS232 system (like a PC) is needed.

UART_RTS: UART ready to send output line. This pin is directly connected to the FPGA. The UART is realized as a soft component inside the FPGA. There are no RS232 line drivers onboard. An external RS232 line driver is required when communication to another RS232 system (like a PC) is needed.

UART_CTS: UART clear to send input line. This pin is directly connected to the FPGA. The UART is realized as a soft component inside the FPGA. There are no RS232 line drivers onboard. An external RS232 line driver is required when communication to another RS232 system (like a PC) is needed.

1394_PORT0_TPA+: 1394_PORT0_TPA- 1394_PORT0_TPB+ 1394_PORT0_TPB- These are the four differential I/O lines of the IEEE1394 port 0. These lines have to be wired to external IEEE1394 standard (4 pin or 6 pin) connectors. Differential signal optimized PCB routing of each +/– signal between the UC1394a-1 device and the external connectors are necessarily required.

© Orsys GmbH 02/2005 8 ultra-compact UC1394a-1 multi chip module overview Pin row B: This pin row is part of the ultra-compact standard pinning and is pin compatible through all ultra- compact devices.

Pin row B includes 2 basic types of signals: 1. Power supply 2. 16 bit streaming interface and its control signals

+3.3V: Power Supply +3.3V

GND: Ground

Streaming_D0 to D15: These are usually the 16 bidirectional data lines of the parallel 16 bit wide streaming interface. They are used to connect the device to external data sources or destinations which can be either parallel processor I/O interfaces (preferably with DMA support) or pure hardware logic solutions like FPGA to reach the full possible bandwidth (up to approx. 32 Mbyte/s). The streaming interface lines are directly connected to the onboard FPGA and can alternatively be used for other purposes at several BSPs.

/STREAMING_WE: This is the write enable input line for the parallel streaming interface. It is directly connected to the onboard FPGA.

/STREAMING_RE: This is the read enable input line for the parallel streaming interface. It is directly connected to the onboard FPGA.

/STREAMING_CLK: This is the clock input line for the parallel streaming interface. It is directly connected to the onboard FPGA.

/STREAMING_AEF: This is the almost empty flag output line for the parallel streaming interface. It is directly connected to the onboard FPGA.

/STREAMING_AEF: This is the almost full flag output line for the parallel streaming interface. It is directly connected to the onboard FPGA.

© Orsys GmbH 02/2005 9 ultra-compact UC1394a-1 multi chip module overview Pin row C: This pin row is part of the ultra-compact expansion pinning and may be different or unused at other ultra-compact devices. If maximum future compatibility is desired, pin row C should be used carefully.

Pin row C includes 7 basic types of signals:

1. Two McBSP synchronous serial interfaces 2. One DSP external flag signal XF1 3. One auxiliary I/O line 4. Four AD converter analog input lines 5. A JTAG DSP debugging interface 6. A JTAG FPGA download interface 7. Several ground pins

McBSP1_DR: Data receive input/output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP1_DX: Data transmit output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP1_CLKR: Clock receive input/output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP1_CLKX: Clock transmit input/output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP1_FSR: Frame sync receive input/output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP1_FSX: Frame sync transmit input/output line of the second McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

GND: Ground

McBSP2_DR: Data receive input/output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP2_DX: Data transmit output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

© Orsys GmbH 02/2005 10 ultra-compact UC1394a-1 multi chip module overview McBSP2_CLKR: Clock receive input/output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP2_CLKX: Clock transmit input/output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP2_FSR: Frame sync receive input/output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

McBSP2_FSX: Frame sync transmit input/output line of the third McBSP serial interface. This line is directly connected to the corresponding TMS320VC5509a pin.

JTAG_DSP_EMU1: JTAG_DSP_EMU0: /JTAG_DSP_TRST: JTAG_DSP_TCK: JTAG_DSP_TDO: JTAG_DSP_TDI: JTAG_DSP_TMS: Control input/output lines for the DSP JTAG emulator. These lines can be used for application specific software debugging during the development phase (if necessary).These lines are directly connected to the corresponding TMS320VC5509a pins.

JTAG_FPGA_TCK: JTAG_ FPGA _TDO: JTAG_ FPGA _TDI: JTAG_ FPGA _TMS: Control input/output lines for the external FPGA JTAG download environment. These lines can be used to download application specific hardware configurations into the FPGA during the development phase (if necessary). They are directly connected to the corresponding FPGA pins.

DSP_XF1: External flag output line of the TMS320VC5509a processor. This line is directly connected to the corresponding TMS320VC5509a pin.

FPGA_I/O_26: FPGA I/O line 26. It can be used as a free digital I/O resource for application specific FPGA logic. This line is directly connected to the FPGA.

AIN_0: AIN_1: AIN_2: AIN_3: These are four analog input lines which enable analog to digital conversion. These lines are directly connected to the corresponding TMS320VC5509a pins.

© Orsys GmbH 02/2005 11 ultra-compact UC1394a-1 multi chip module overview Pin row D: This pin row is part of the ultra-compact expansion pinning and may be different or unused at other ultra-compact devices. If maximum future compatibility is desired, pin row D should be used carefully.

Pin row D includes 6 basic types of signals:

1. One differential 1394 port 2. Twenty-one auxiliary FPGA I/O lines 3. One I2C serial interface 4. One serial USB1.1 (slave) bus 5. Real time clock (RTC) clock pins 6. Several ground pins

1394_PORT1_TPA+: 1394_PORT1_TPA- 1394_PORT1_TPB+ 1394_PORT1_TPB- These are the four differential I/O lines of the IEEE1394 port 1. These lines have to be wired to external IEEE1394 standard (4 pin or 6 pin) connectors. Differential signal optimized PCB routing of each +/– signal between the UC1394a-1 device and the external connectors are necessarily required.

GND: Ground

FPGA_I/O_5 till FPGA_I/O_25: These are the FPGA I/O lines 5 till 25. They can be used as free digital I/O resources for application specific FPGA logic. These lines are directly connected to the FPGA.

USB_DP: USB_DN: These are the two differential I/O lines of the USB1.1 port. They are directly connected to the corresponding TMS320VC5509a pins.

I2C_SDA: I2C_SCL: These are the two open collector I/O lines of the I2C interface. They are directly connected to the corresponding TMS320VC5509a pins.

PCB Footprint ultra-compact UC1394a family incl. future compatible “square pinout”

36.47 (standard pinout)

30.38 (square pinout **) 30.38

1,02 ** for future compatibility all dimensions in millimeters

Specification overview

Board definition Ultra-compact UC1394a-1 Plug and play IEEE1394a multi chip module CPU TMS320C5509a (high performance fixed point)

Maximum CPU 400 MIPS (Million Instruction Operations Per Second) performance

FPGA Xilinx SPARTAN II with 50 Kgates

Available RAM SDRAM (100 MHz), 8 Mbytes

Available Boot Flash 512 kbytes

Common ultra-compact RS232 without line drivers for communication with PC and for Interfaces other application purposes, up to 115200 baud (Pin Row A + B) multi-channel Buffered Serial Ports (McBSP) Synchronous Serial Interface, up to 50 Mbps @ 200 MHz

5 digital user I/O lines

16 bit wide 32 Mbyte/s isochronous streaming interface

400 Mbit/s IEEE 1394a serial bus port

Specific ultra-compact 2 additional multi-channel Buffered Serial Ports (McBSP) UC1394a Interfaces Synchronous Serial Interface, up to 50 Mbps @ 200 MHz (Pin Row C + D) 22 free configurable FPGA digital I/O lines

USB1.1 (slave) port

I2C Interface

4 channel 10 bit analog input

DSP external flag XF0

JTAG emulator interface for debugging and downloading purposes

Real Time Clock (RTC) Clock interface and power backup

400 Mbit/s IEEE 1394a serial bus port

Dimensions 30mm x 36mm x 7(TBC)mm / 1.18in x 1.41in x 0.28(TBC)in

Common ultra-compact Plug and play 400Mbit/s IEEE1394 network solution, thus no features detailed IEEE1394 knowledge necessary to run standard compliant IEEE1394

Only one component necessary to enable virtually any device to communicate via IEEE1394

Various, universal hardware and software interfaces for many custom specific applications

Please note:

This document is subject to changes. Please contact Orsys GmbH or your local Orsys distributor for further technical details.

Orsys GmbH Am Stadtgraben 25 88677 Markdorf Germany

Phone: +49-7544-9561-0 Fax: +49-7544-9561-29

Web-site: www.orsys.de Email: [email protected]