Cpe 252 Computer Organization & Design

CpE 252 Computer Organization & Design

 Register Transfer Language

 Register Transfer

 Bus Transfer

 Memory Transfer

 Microoperations

 Arithmetic Microoperations

 Logic Microoperations

 Shift Microoperations

 Arithmetic Logic Shift Unit

Dr. T. Eldos 2 Microoperations

 An elementary operation performed during one clock pulse, on the information stored in one or more registers

 Processor datapath is where data is processes; registers, buses and arithmetic and logic unit

 General: Ri F (Rj, Rk) , where F is some function like shift, add, ...

R3 1st operand, source 1 2nd operand, source 2 3rd operand, destination Rn

A B F Select Operation

Dr. T. Eldos 3 Register Transfer Language

 Definition of the internal organization of a computer

 Set of Registers and their functions

 Set of Microoperations, possible microoperations provided by the organization of the computer

 Control Signals, that initiate the sequence of microoperations

 Example: Operation ADD R1, R2

 Registers R1 and R2 act as data registers, holding numbers

 ADD instruction adding two registers

 Control signals

 Copies R1 to BUS A and R2 to BUS B of the ALU

 Commands the ALU to perform addition

 Moves output of ALU back to R1

 Register Transfer Language (RTL) is a symbolic notation used to describe the microoperation transfers among registers and memory locations

Dr. T. Eldos 4 Register Block Diagram

 Designation of a register:

 A register

 A portion of a register

 A bit of a register

 Common ways of drawing the block diagram of a register

Numbering of bits 15 R1 0

Subfields R1 (H) R1(L)

Dr. T. Eldos 5 Register Transfer

 Representation of a transfer R2 R1

 A simultaneous copy of all bits of the source to the destination register, during one clock pulse

 Representation of a controlled (Conditional) transfer P: R2 R1

 A binary condition (P=1) which determines when the transfer is to occur If (P=1) then (R2 R1)

Dr. T. Eldos 6 Hardware Implementation of Controlled Transfer

 Implementation of the statement P: R2 R1

 Block Diagram

 Timing Diagram

P Load Clock Control Circuit R2 Clock

n bits

t t+1 Clock

Load

Transfer occurs here

Dr. T. Eldos 7 Basic Symbols for RTL

 Capital Alpha Numerals

 Denotes registers like MAR and R2

 Parenthesis ( )

 Denotes part of registers like R1(3:0)

 Arrow 

 Denotes transfer of information

 Colon :

 Terminates control function like P:

 Comma ,

 Separates parallel microoperations like A B, C A

Dr. T. Eldos 8 Bus Based Transfer

 Bus is a path (a group of wires) over which information is transferred, from any of several sources to any of several destinations

 Bus is a shared media, used instead of the costly but high- performance 1-to-1 connection of registers and memory

 This is cheaper and less space consuming but less in performance, as only two parties can be involved at one time

 Bus to Register and Register to Bus below

Bus lines

Reg. A Reg. B Reg. C Reg. D

Bus lines

Dr. T. Eldos 9 Bus to Register Transfer

 All registers listen to the BUS all the time

 Select lines enables only one of the registers to pick up the data

 LD is a load enabling signal that enables one register to pick the data, but the actual clocking occur when a clock signal rise up

BUS Lines

LD LD LD LD 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 REG A REG B REG C REG D

DEC Y0

A Y1

B Y2

Dr. T. Eldos 10 Register to Bus Transfer Logic - MUX

 Register to bus has the form BUS Ri based on Select Lines

 Select Lines 00 causes all bits of REG A to be switched to BUS

 Using MUX is just one way to do this

3 2 1 0 REG D

3 2 1 0 REG C

3 2 1 0 REG B

3 2 1 0 REG A

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 MUX MUX MUX MUX Select Lines BUS Lines

Dr. T. Eldos 11 Register to Bus Transfer Logic: Tri-State

 Tri-state buffers can be used in register to bus interface

 If C=1 Then Y is connected to A

 If C=0 Then Y is disconnected from A

 Actually connected and disconnected correspond to very low (10’s ) and very high impedance (10’s M)

A Y A Y C A Y Control = 1 C 0 0 Z Tri-State Buffer 0 1 Z 1 0 0 1 1 1 A Y Control = 0

Dr. T. Eldos 12 Register to Bus Transfer Logic: Tri-State

3 2 1 0 REG D

3 2 1 0 REG C Y0

3 2 1 0 REG B Y1A

DEC Select Lines 3 2 1 0 REG A Y2B

BUS Lines

Dr. T. Eldos 13 Memory Transfer

 Memory needs address information to specify where to read or write in the memory

 Typically comes from Address Register AR

 Also needs control input to specify the data flow direction, Read (RD) and Write (WE)

 Data read from memory or to be written to memory is in the Data Register DR

 If the system has many memory modules, then a control input called Chip Select (CS) is to be used to pick one out of many

 Memory read microoperation DR M[AR]

 Memory write microoperation AR

M[AR] DR RD WE MEM CS

Dr. T. Eldos 14 Register Transfer Microoperations

 Copy content of reg. Rj into reg. Ri Ri Rj

 Copy the address portion of reg. DR into reg. AR AR DR

 Copy a binary constant (C) into reg. Ri Ri C

 Copy content of Ri into bus A and, at the same time copy content of bus A into Rj (equivalent to Rj  Ri) ABUS Ri, Rj ABUS

 Memory Read DR M[AR]

 Memory Write M[AR] DR

Dr. T. Eldos 15 Arithmetic Microoperations

 Arithmetic microoperations

 Add

 Subtract

 Increment

 Decrement

 Negate (2’s complement)

 Logic microoperations

 AND

 OR

 NOT (Complement)

 Shift microoperations

 Shift: Left & Right, Logical and Arithmetic

 Rotate or Circulate

 Register transfer microoperations

 Pass content through

Dr. T. Eldos 16 Arithmetic Microoperations

 Contents of Ri plus Rj copied to Rk Rk Ri + Rj

 Contents of Ri minus Rj copied to Rk Rk Ri – Rj or Rk Ri + Rj’+ 1

 Complement the contents of Ri Ri Ri’

 2's complement the contents of Ri (negate) Ri Ri’+ 1

 Increment the content of Ri by 1 Ri Ri + 1

 Decrement the content of Ri by 1 Ri Ri - 1

Dr. T. Eldos 17 4-bit Adder Using set of Full Adders (FA)

 This is called ripple carry adder

 Time to deliver the sum is proportional to the size

 If B’s are inverted, giving the 1’s complement of the number, then we get the difference minus 1

 If we manage to add 1, we get the difference

 We’ll do just that later

B3 A3 B2 A2 B1 A1 B0 A0

Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin Carry In

S3 S2 S1 S0

Dr. T. Eldos 18 Incrementer Using set of Half Adders (HA)

 When adding 1, we are adding 0001 (in case of 4 bit numbers)

 This means that we never need the second input except for the first bit

 So, HA suffices, and we use the carry out of each stage as input to the next

 Actually, we don’t do this in a processor; the logic used for addition add or subtract 1 to increment or decrement

A3 A2 A1 A0 1

Carry Out Cout HA Cout HA Cout HA Cout HA

S3 S2 S1 S0

Dr. T. Eldos 19 4-bit Adder/Subtractor Using set of Full Adders

 There are two cases

 If M=0 then C0=0 and the XOR passes the B’s as are, i.e. ADD

 If M=1 then C0=1 and the XOR complement the B’s, i.e. SUBTRACT

B3 A3 B2 A2 B1 A1 B0 A0

A*/S

Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin

S3 S2 S1 S0

Dr. T. Eldos 20 XOR & MUX: Same Logic

Bi Ai Bi Ai

M M M MUX

Yi Yi

Ci Ci-1 Ci Ci-1 Cout FA Cin Cout FA Cin

Si Si

Dr. T. Eldos 21 Add, Subtract, Inclement, Decrement and Transfer

Select 00 Add Y = B, S = A + B + Cin Select 01 Subtract Y = B’, S = A - B – Cin’ Select 10, Cin=0 Transfer S = A Select 10, Cin=1 Increment S = A + 1 Select 11, Cin=0 Decrement S = A - 1 Select 11, Cin=1 Transfer S = A

B3 A3 B2 A2 B1 A1 B0 A0

1 0 1 0 1 0 1 0

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Select MUX MUX MUX MUX Y X

Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin Carry In

S3 S2 S1 S0

Dr. T. Eldos 22 Logic Microoperations

 Binary operations on strings of bits in registers

 Useful for bit manipulations on binary data AND Mask out certain group of bits OR Merge binary or character data NOT Invert Data or Mask

 Useful for making logical decisions based on the bit value Selective-set A  B Selective-clear A  B Selective-complement A  B

 Examples: A 1 0 1 1 0 0 1 0 B 0 1 0 1 0 0 1 1 A’ 0 1 0 1 1 1 0 1 A  B 1 1 1 1 0 0 1 1 A  B 0 0 0 1 0 0 1 0 A  B 1 1 1 0 0 0 0 1

Dr. T. Eldos 23 Possible Logic Microoperations 2 binary variables imply 22=4, and 24=16 different logic functions

X 0 0 1 1 Boolean Microoperation Name Y 0 1 0 1 Function 0 0 0 0 F00=0 F  0 Clear 0 0 0 1 F01=XY F  AB AND 0 0 1 0 F02=XY’ F  AB’ 0 0 1 1 F03=X F  A Transfer A 0 1 0 0 F04=X’Y F  A’B 0 1 0 1 F05=Y F  B Transfer B 0 1 1 0 F06=XY F  AB XOR 0 1 1 1 F07=X+Y F  AB OR 1 0 0 0 F08=(X+Y)’ F  (AY)’ NOR 1 0 0 1 F09=(XY)’ F  (AB)’ XNOR 1 0 1 0 F10=Y’ F  B’ Complement B 1 0 1 1 F11=X+Y’ F  AB’ 1 1 0 0 F12=X’ F  A’ Complement A 1 1 0 1 F13=X’+Y F  AB’ 1 1 1 0 F14=(XY)’ F  (AB)’ NAND 1 1 1 1 F15=1 F  1 Set to all 1’s

Dr. T. Eldos 24 Implementation of Logic Microoperations

A S1 S0 Operation Function i 0 0 0 F = A • B AND Bi 0 1 F = A + B OR 1 1 0 F = A  B XOR MUX F 1 1 F = A’ Complement i 2

3 Select

S0 S1

A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0

S0 S1

F7 F6 F5 F4 F3 F2 F1 F0

Dr. T. Eldos 25 Shift Microoperations

 Shift

 Logical: shift in zero at one end and drop bit from he other end

 Arithmetic: like logical shift except that sign bit is copied instead of inserting zero (Right) and sign bit change sets the Overflow flag (Left)

 Circular shift : Like shift except that the bit dropped out at one end is inserted into the other end

 Left Shift is equivalent to multiplying by 2

 Right Shift equivalent to diving by 2

Symbol Description R  shl R Shift-left register R R  shr R Shift-right register R R  cil R Circular shift-left register R R  cir R Circular right-shift register R R  ashl R Arithmetic shift-left register R R  ashr R Arithmetic shift-right register R

Dr. T. Eldos 26 Shift & Circulate – Logic & Arithmetic

E 15 14 1 0 0 0 1514 1 0 E Logical Shift Left Logical Shift Right

E 15 14 1 0 0 15 15 14 1 0 E Arithmetic Shift Left Arithmetic Shift Right Sign Change Overflow Flag Preserve Sign, BIT 15 fixed

E 15 14 1 0 15 14 1 0 E Circulate Left Circulate Right

E 15 14 1 0 15 14 1 0 E Circulate Left Through E Circulate Right Through E

Dr. T. Eldos 27 Shift Right & Shift Left Mechanism

A7 A6 A5 A4 A3 A2 A1 A0

SI SO

Ai+1 Ai-1

H7 H6 H5 H4 H3 H2 H1 H0

S MUX

A7 A6 A5 A4 A3 A2 A1 A0

Hi SO SI

H7 H6 H5 H4 H3 H2 H1 H0

Dr. T. Eldos 28 Shift Unit – Sift Left & Shift Right

 Shift Right inserts 0 in the left most bit thought SRin=0, and drops the content of the left most bit

 Shift Light inserts 0 in the right most bit thought SLin=0, and drops the content of the right most bit

 Typically, dropped bits get copied to a flag for testing

A7 A6 A5 A4 A3 A2 A1 A0

SRin SLin

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MUX MUX MUX MUX MUX MUX MUX MUX S

F7 F6 F5 F4 F3 F2 F1 F0

Dr. T. Eldos 29 Shift Unit – Circulate

 Instead of inserting at one end and dropping from the other, the end bits are connected to close the circle

 Circulation typically copies the dropped bits onto some flag for testing

A7 A6 A5 A4 A3 A2 A1 A0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MUX MUX MUX MUX MUX MUX MUX MUX S

F7 F6 F5 F4 F3 F2 F1 F0

Dr. T. Eldos 30 Arithmetic Logic Shift Unit (ALSU)

 1-bit ALSU, performs arithmetic, logic and shift operations on bit I of numbers or strings A and B th  For shifting the i bit of string A, the left and right bits are used

Ai+1 Ai Ai-1 Bi

S0 Arithmetic Logic S1 Unit Unit

Di Ei

S 2 MUX S3

Fi Dr. T. Eldos 31 Arithmetic Logic Shift Unit (ALSU)

 S1 and S0 selects an operations within the AU and the LU

 S3 and S2 selects the output of the AU, LU or one of the other two inputs that map the bits of the input string A, to shift left or right

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F = A Transfer 0 0 0 0 1 F = A + 1 Increment 0 0 0 1 0 F = A – 1 Decrement 0 0 0 1 1 F = A Transfer

0 0 1 0 X F = A + B + Cin Add with Carry 0 0 1 1 X F = A + B’ + Cin Subtract with Borrow

0 1 0 0 X F = A • B And 0 1 0 1 X F = A + B Or 0 1 1 0 X F = A  B Xor 0 1 1 1 X F = A’ Not or Complement

1 0 X X X F = shr A Shift Right 1 1 X X X F = shl A Shift Left

Dr. T. Eldos 32