CpE 252 Computer Organization & Design Register Transfer & Microoperations Register Transfer & Microoperations Register Transfer Language Register Transfer Bus Transfer Memory Transfer Microoperations Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift Unit Dr. T. Eldos 2 Microoperations An elementary operation performed during one clock pulse, on the information stored in one or more registers Processor datapath is where data is processes; registers, buses and arithmetic and logic unit General: Ri F (Rj, Rk) , where F is some function like shift, add, ... R1 R2 R3 1st operand, source 1 2nd operand, source 2 3rd operand, destination Rn A B F Select Operation Dr. T. Eldos 3 Register Transfer Language Definition of the internal organization of a computer Set of Registers and their functions Set of Microoperations, possible microoperations provided by the organization of the computer Control Signals, that initiate the sequence of microoperations Example: Operation ADD R1, R2 Registers R1 and R2 act as data registers, holding numbers ADD instruction adding two registers Control signals Copies R1 to BUS A and R2 to BUS B of the ALU Commands the ALU to perform addition Moves output of ALU back to R1 Register Transfer Language (RTL) is a symbolic notation used to describe the microoperation transfers among registers and memory locations Dr. T. Eldos 4 Register Block Diagram Designation of a register: A register A portion of a register A bit of a register Common ways of drawing the block diagram of a register Register R1 Numbering of bits 15 R1 0 Subfields R1 (H) R1(L) Dr. T. Eldos 5 Register Transfer Representation of a transfer R2 R1 A simultaneous copy of all bits of the source to the destination register, during one clock pulse Representation of a controlled (Conditional) transfer P: R2 R1 A binary condition (P=1) which determines when the transfer is to occur If (P=1) then (R2 R1) Dr. T. Eldos 6 Hardware Implementation of Controlled Transfer Implementation of the statement P: R2 R1 Block Diagram Timing Diagram P Load Clock Control Circuit R2 Clock n bits R1 t t+1 Clock Load Transfer occurs here Dr. T. Eldos 7 Basic Symbols for RTL Capital Alpha Numerals Denotes registers like MAR and R2 Parenthesis ( ) Denotes part of registers like R1(3:0) Arrow Denotes transfer of information Colon : Terminates control function like P: Comma , Separates parallel microoperations like A B, C A Dr. T. Eldos 8 Bus Based Transfer Bus is a path (a group of wires) over which information is transferred, from any of several sources to any of several destinations Bus is a shared media, used instead of the costly but high- performance 1-to-1 connection of registers and memory This is cheaper and less space consuming but less in performance, as only two parties can be involved at one time Bus to Register and Register to Bus below Bus lines Reg. A Reg. B Reg. C Reg. D Reg. A Reg. B Reg. C Reg. D Bus lines Dr. T. Eldos 9 Bus to Register Transfer All registers listen to the BUS all the time Select lines enables only one of the registers to pick up the data LD is a load enabling signal that enables one register to pick the data, but the actual clocking occur when a clock signal rise up BUS Lines LD LD LD LD 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 REG A REG B REG C REG D DEC Y0 A Y1 B Y2 Y3 Dr. T. Eldos 10 Register to Bus Transfer Logic - MUX Register to bus has the form BUS Ri based on Select Lines Select Lines 00 causes all bits of REG A to be switched to BUS Using MUX is just one way to do this 3 2 1 0 REG D 3 2 1 0 REG C 3 2 1 0 REG B 3 2 1 0 REG A 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 MUX MUX MUX MUX Select Lines BUS Lines Dr. T. Eldos 11 Register to Bus Transfer Logic: Tri-State Tri-state buffers can be used in register to bus interface If C=1 Then Y is connected to A If C=0 Then Y is disconnected from A Actually connected and disconnected correspond to very low (10’s ) and very high impedance (10’s M) A Y A Y C A Y Control = 1 C 0 0 Z Tri-State Buffer 0 1 Z 1 0 0 1 1 1 A Y Control = 0 Dr. T. Eldos 12 Register to Bus Transfer Logic: Tri-State 3 2 1 0 REG D 3 2 1 0 REG C Y0 3 2 1 0 REG B Y1A DEC Select Lines 3 2 1 0 REG A Y2B Y3 BUS Lines Dr. T. Eldos 13 Memory Transfer Memory needs address information to specify where to read or write in the memory Typically comes from Address Register AR Also needs control input to specify the data flow direction, Read (RD) and Write (WE) Data read from memory or to be written to memory is in the Data Register DR If the system has many memory modules, then a control input called Chip Select (CS) is to be used to pick one out of many Memory read microoperation DR M[AR] Memory write microoperation AR M[AR] DR RD WE MEM CS DR Dr. T. Eldos 14 Register Transfer Microoperations Copy content of reg. Rj into reg. Ri Ri Rj Copy the address portion of reg. DR into reg. AR AR DR Copy a binary constant (C) into reg. Ri Ri C Copy content of Ri into bus A and, at the same time copy content of bus A into Rj (equivalent to Rj Ri) ABUS Ri, Rj ABUS Memory Read DR M[AR] Memory Write M[AR] DR Dr. T. Eldos 15 Arithmetic Microoperations Arithmetic microoperations Add Subtract Increment Decrement Negate (2’s complement) Logic microoperations AND OR NOT (Complement) Shift microoperations Shift: Left & Right, Logical and Arithmetic Rotate or Circulate Register transfer microoperations Pass content through Dr. T. Eldos 16 Arithmetic Microoperations Contents of Ri plus Rj copied to Rk Rk Ri + Rj Contents of Ri minus Rj copied to Rk Rk Ri – Rj or Rk Ri + Rj’+ 1 Complement the contents of Ri Ri Ri’ 2's complement the contents of Ri (negate) Ri Ri’+ 1 Increment the content of Ri by 1 Ri Ri + 1 Decrement the content of Ri by 1 Ri Ri - 1 Dr. T. Eldos 17 4-bit Adder Using set of Full Adders (FA) This is called ripple carry adder Time to deliver the sum is proportional to the size If B’s are inverted, giving the 1’s complement of the number, then we get the difference minus 1 If we manage to add 1, we get the difference We’ll do just that later B3 A3 B2 A2 B1 A1 B0 A0 Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin Carry In S3 S2 S1 S0 Dr. T. Eldos 18 Incrementer Using set of Half Adders (HA) When adding 1, we are adding 0001 (in case of 4 bit numbers) This means that we never need the second input except for the first bit So, HA suffices, and we use the carry out of each stage as input to the next Actually, we don’t do this in a processor; the logic used for addition add or subtract 1 to increment or decrement A3 A2 A1 A0 1 Carry Out Cout HA Cout HA Cout HA Cout HA S3 S2 S1 S0 Dr. T. Eldos 19 4-bit Adder/Subtractor Using set of Full Adders There are two cases If M=0 then C0=0 and the XOR passes the B’s as are, i.e. ADD If M=1 then C0=1 and the XOR complement the B’s, i.e. SUBTRACT B3 A3 B2 A2 B1 A1 B0 A0 A*/S Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S3 S2 S1 S0 Dr. T. Eldos 20 XOR & MUX: Same Logic Bi Bi Ai Bi Ai M M M MUX Yi Yi Ci Ci-1 Ci Ci-1 Cout FA Cin Cout FA Cin Si Si Yi Dr. T. Eldos 21 Add, Subtract, Inclement, Decrement and Transfer Select 00 Add Y = B, S = A + B + Cin Select 01 Subtract Y = B’, S = A - B – Cin’ Select 10, Cin=0 Transfer S = A Select 10, Cin=1 Increment S = A + 1 Select 11, Cin=0 Decrement S = A - 1 Select 11, Cin=1 Transfer S = A B3 A3 B2 A2 B1 A1 B0 A0 1 0 1 0 1 0 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Select MUX MUX MUX MUX Y X Carry Out Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin Carry In S3 S2 S1 S0 Dr. T. Eldos 22 Logic Microoperations Binary operations on strings of bits in registers Useful for bit manipulations on binary data AND Mask out certain group of bits OR Merge binary or character data NOT Invert Data or Mask Useful for making logical decisions based on the bit value Selective-set A B Selective-clear A B Selective-complement A B Examples: A 1 0 1 1 0 0 1 0 B 0 1 0 1 0 0 1 1 A’ 0 1 0 1 1 1 0 1 A B 1 1 1 1 0 0 1 1 A B 0 0 0 1 0 0 1 0 A B 1 1 1 0 0 0 0 1 Dr.