Arithmetic Shift Operations

Computer Science 210 s1c Computer Systems 1 2013 Semester 1 Lecture Notes

Lecture 22, 3May13: Real Processors: MIPS, Alpha & the X86 James Goodman! Why am I Talking about the ALPHA? The processor you never heard of

1. It’s real Well, it once was 2. “A design to last 25 years” Introduced in 1992… 3. It’s the best/fastest/cleanest Really!

1-May-13 CS210 658 The MIPS Architecture Millions of Instructions Per Second References

Good starting point for the MIPS architecture: http://en.wikipedia.org/wiki/MIPS_architecture ! Very nice summary of architecture ! Lots of pointers to other material

Read (more) about the MIPS architecture ! http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html • MIPS Instruction reference ! http://www.xs4all.nl/~vhouten/mipsel/r3000-isa.html • Student paper summarizing MIPS Instruction Set ! http://www.langens.eu/tim/ea/mips_en.php • Lots of MIPS documentation: ! http://chortle.ccsu.edu/AssemblyTutorial/TutorialContents.html • Tutorial on MIPS Assembly Language: ! http://www.cs.wisc.edu/~larus/HP_AppA.pdf • Patterson&Hennessy (CS 313 textbook) Appendix A: SPIM, a MIPS simulator (pdf)

1-May-13 CS215s2c 660 The MIPS Computer

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1-May-13 CS215s2c 661 Registers

! 32 general registers • $0 - $31; also names • $0 is special – when read, gives zero – writing has no effect • $31 sometimes implicit in instruction ! 16/32 floating-point registers • $fgr0-$fgr31 32-bit floating-point registers • Can be configured as 16 64-bit registers ! Special-purpose registers • Hi/Lo (multiplication/division) • Floating-point control/status registers

1-May-13 CS215s2c 662 Pseudoinstructions

Some “instructions” are not implemented in the hardware, but are synthesised from two or more real instructions. These instructions are recognized by the assembler and automatically synthesised.

1-May-13 CS215s2c 663 Categories of Instructions

1. Arithmetic/Logical [LC-3: Operate Instructions] a. Arithmetic b. Logical c. Shift d. Compare [LC-3 equivalent?] 2. Control a. Branch on condition b. Jump c. Special (trap, rfi) 3. Data transfer a. Load b. Store c. Move(copy) d. Load address

2-May-13 CS215s2c 664 1a. Arithmetic Instructions

ADD, SUB, MUL, DIV, REM, Two sources, one destination (can be common)

! Form: add D,S1,S2 D ← S1 + S2 • D, S1 are registers. • S2 can be a register or an immediate, i.e., value contained in the instruction. ! Multiple operand sizes (8, 16, 32, 64 bits) ! Signed and unsigned arithmetic • add (signed) • addu (unsigned) • Difference: signed generates exception on overflow ! Overflow • Addition & subtraction: only one bit • Multiplication: none because result is twice as big

1-May-13 CS215s2c 665 1b. Logical Instructions

Instructions: AND, OR, XOR, NOR, NOT Two sources (one for NOT), one destination

Form: and D,S1,S2 D ← S1 AND S2

! D, S1 are registers.

! S2 can be a register or an immediate, i.e., value contained in the instruction. Multiple operand sizes (8, 16, 32, 64 bits) Overflow: none

1-May-13 CS215s2c 666 LC-3 Logical Operations

NOT AND

A B Possible Functions of A, B 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1-May-13 CS215s2c 667 LC-3MIPS Logical Logical Operations Operations

NOT AND

A B Possible Functions of A, B 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

NOR XOR OR

2-May-13 CS215s2c 668 Categories of Instructions

1-May-13 CS215s2c 669 1c. Shift Operations

Form: sll D,S,AMT AMT is a count, equivalent to AMT shifts by 1 place. There are three types of Shift Operations ! logical (srl, sll) ! arithmetic (sra, sll) ! rotate (rr)

1-May-13 CS215s2c 670 Shift Operations

Right Rotate Operation:

msb lsb

No information lost For N-bit word, rotate right N positions has no effect Rotate right i positions is same as rotate left N – i positions Not implemented in MIPS (why not?)

1-May-13 CS215s2c 673 Logical Shift Operations

Right Logical Shift Operation:

msb lsb

discard

MIPS instruction: srl Java equivalent: >>>

1-May-13 CS215s2c 674 Logical Shift Operations

Left Logical Shift Operation:

msb lsb

Discard 0

MIPS instruction: sll Java equivalent: <<

1-May-13 CS215s2c 675 Arithmetic Shift Operations

Right Arithmetic Shift Operation ! Unsigned integer division by power of 2

Round down (toward negative infinity) MIPS instruction: sra Java equivalent: >> ! same as integer division by power of 2???

1-May-13 CS215s2c 676 Arithmetic Shift Operations

Left Arithmetic Shift Operation ! Unsigned integer multiplication by power of 2

msb lsb

Discard? 0 Overflow if MSB changes !"#$%"&%'()*+"'%'$,-%&.*,-/0 MIPS instruction: sll (no sla) Java equivalent: ‘* 2i’

1-May-13 CS215s2c 677 Categories of Instructions

2-May-13 CS215s2c 678 2a. Control Instructions

Basic instruction for choosing alternate instruction path:

! Branch on condition: bne R1,R2,L1

• True if R1,R2 are unequal ! Possible tests

• beq : R1 = R2 are equal ?

• bne : R1 ! R2 ?

• bgt : R1 > R2 ?

• blt : R1 < R2 ?

• bge : R1 " R2 ?

• ble : R1 # R2 ? • b : Unconditional

1-May-13 CS215s2c 679 Categories of Instructions

2-May-13 CS215s2c 681 Ideas Same in LC-3 & MIPS & Alpha

• von Neumann computer ! Implemented with finite-state machines ! Performs same basic fetch/execute cycle

• Fixed-length instructions (16/32-bits)[see X-86] • General-purpose registers ! 2n registers

! Load/Store architecture[see X-86] • JSR/RET

• TRAP (CALLSYS[Alpha], SYSCALL[MIPS])

1-May-13 CS210 683 History of Digital Equipment Corporation (DEC)

• Founded in 1957 • PDP-8 (1964) 12-bit computer • PDP-11 (1970) 16-bit computer • VAX (1976) 32-bit computer • Alpha ! EV4: 1992; 192MHz ! EV5: 1995; 333MHz ! EV6: 1998; 450MHz (eventually 1.25GHz) ! EV7: 2003; 1.15GHz • DEC bought by Compaq (later bought by HP): 1998 • Alpha IP sold to Intel: 2001 • Intel phased out Alpha in favour of Itanium: 2004 Itanium?

2-May-13 CS210 684 Alpha: Beyond a Byte • The Alpha is a 64-bit computer • Registers (32) are 64 bits wide • Instructions are 32 bits • Addresses can be up to 55 bits (!254 = 18 quadrillion bytes of memory) • Operate instructions exist for ! Bytes (8 bits) ! Words (16 bits) ! Longwords (32 bits) ! Quadwords (64 bits) • Load/store instructions exist for different sized operands ! lb/stb (byte) ! lw/sw (word) ! ll/stl (longword) ! lq/stq (quadword) ! Smaller operands go into least significant bits of register • Floating point: 64 more registers; more operations

1-May-13 CS210 685 Alpha Instruction Format

1-May-13 CS210 686 LC-3: 4 Load Instructions

Really 4 addressing modes: • LEA Rd, Label ; Rd = PC + SEXT(PCoffset9) • LD Rd, Label ; Rd = mem[PC + SEXT(PCoffset9)] • LDI Rd, Label ; Rd = mem[ mem[PC + SEXT(PCoffset9)]] • LDR Rd, Rb, offset6 ; Rd = mem[Rb + SEXT( offset6)]

MIPS: 1 Load Instruction (others are synthesized)

• LW Rd, (Rb)offset16 ; Rd = mem[Rb + SEXT( offset16)] • LUI Rd, constant ; Rd = constant<<16

2013.05.02 CS210 687 Alpha: Load Reg, Disp(Base)

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Effective address: (Base) + Displacement Base specifies the content of a register Displacement is a 16-bit signed constant, sign-extended Displacement defines position relative to Base

1-May-13 CS215s2c 688 The LC-3 Instructions

2-May-13 CS210 691 The Alpha Instructions

2-May-13 CS210 692 The Alpha Instructions

2-May-13 CS210 693