A Methodology to Adapt Data Path Architectures to a MIPS-1 Model

A methodology to adapt data path architectures to a MIPS-1 model Leonardo Augusto Casillo Ivan Saraiva Silva Depart. of Exact and Natural Science Depart. of Informatics and Statistics Federal Rural University of the Semi-Arid Federal University of Piauí Mossoró – RN – Brazil Teresina – PI – Brazil [email protected] [email protected] Abstract — MIPS (Microprocessor without Interlocked Pipeline Pipeline Stages) standard [3]. MIPS microprocessors are used Stages) is an Instruction Set Architecture used in applications in applications such as computers, routers, game consoles (like such as computers, routers, game consoles and various embedded PlayStation) and embedded systems. systems. Among the advantages of this pattern, it could be cited the variety of free software such as compilers and simulators. In academic terms, the implementation of a known ISA as This paper shows a methodology required to adapt other the MIPS-1 ISA in a data path where the main requirement is architectures to use a MIPS-1 instruction set without significant the architectural simplicity makes the student think about the increase in chip area and power dissipation. This methodology tradeoffs between performance, chip area and power was applied in two case studies, which architectures at different dissipation. The experiment shown in this paper also considers complexity levels data paths will be adapted to a new model. the implementation of homogeneous ISA and heterogeneous MPSoCs data path. Key words-MIPS, ISA, didactic processors Such systems can better balance the requirements of I. INTRODUCTION performance, chip area and power dissipation in future The Reconfigurable computing [1] and the growing consumer electronics devices tuning better the relationship popularity of reconfigurable devices like FPGAs and hardware between applications and process, system scheduler and description languages allow the design of a single circuit with a processors features in booth, design time or run time. few logic gates or more complex as processors used to a Another benefit involving academic studies about ISA complex system in a single device like a System on Chip (SoC) standards is the possibility of using this technology in activities technology, such as ASIC devices, embedded systems or even of several didactic courses, such as digital circuits, computer for academic purposes. architecture, operating systems, compilers, microprocessors, These processors are usually called soft-cores and are basic software, automation and control, as well as in research, embedded in the FPGAs together with software and other cores while it becomes possible to use as basic software editors, required by an application. This model allows designers to compilers and simulators previously developed for this pattern. create new functional units and change the existing ones[2]. This paper presents a methodology for the migration The process of creating these new architectures does not process of two different data path architectures processors with need to follow a particular methodology or ISA (Instruction Set core to MIPS-1 Instruction Set Architecture, keeping the Architecture) standard. Although this feature allows a greater complexity data path. In both cases, it was used didactic creative freedom and provides new circuits like unconventional processors described in micro controlled form containing an architectures, on the other hand, the use of these digital systems FSM (Finite State Machine) responsible to all functional become restricted in such MPSoCs (Multiprocessor SoC) or instruction cycle including fetch, decoder and execution embedded systems due to its compatibility constraints with process. This paper shows the minimal necessary data path other systems architectures. modifications to support the formats specified by the MIPS-1 standard, and the strategy used to avoid the addition of new To solve the communication compatibility between functional units, responsible for the increased chip area and the devices, it is possible to create wrappers to establish a form of power dissipation. communication between different architectural patterns. These wrappers can follow certain rules, such as standard OCP, or The following sections provide a view of the proposed also be described by the designer using HDL to adjust its design. Section II describes the fundamental aspects of the structure directly to the required standard. MIPS pattern and the MIPS-1 instruction set. Section III describes the two architectures data path before the migration Some elements of this system should provide the same process proposed. Section IV shows the new data paths after standard as the instruction set to ensure compatibility between the methodology application in these architectures, comparing the programs in parallel applications. Among the ISA pattern chip area and power dissipation results in both versions. existents stands the MIPS (Microprocessor without Interlocked Finally, section VI presents the conclusions and proposals. II. MIPS ARCHITECTURE available from [7]. This processor has a higher level of MIPS (Microprocessor without Interlocked Pipeline Stages) hardware compl exity, including a two or three- stage pipeline. is an Instruction Set Architecture pattern developed by MIPS These processors are considered native architectures, Computer Systems Inc [3]. It’s based architecture provides the because their data paths were developed specifically to support evaluation of simulators, such as MARS, SPIM, among oth ers, the instructions of MIPS-1 ISA. The objective of this work is and other basic softwares like free compilers, which makes its not the development of a new or better architecture for the use popular [4][5]. MIPS-1 ISA. This work aims to study the development of data There are several features / restrictions regarding the format paths with different levels of complexity to the same ISA. of MIPS instruct ions. One of those is that all instructions are Different complexities levels imply different performances, 32-bit length. In other words, no instruction uses only two or chip area and power dissipation. For now this work focuses on three bytes on memory and no instruction can be larger than 4 the adaptation of architectures that were not developed for the bytes. MIPS-1 ISA. This adaptation can be done with a minimum of MIPS instructions can be classified according to their modification and/or functional units addition. Thereby it is format: possible to find a data path where chip area and pow er dissipation remain stable. • R-Type: contains all instructions that do not require an immediate value or memory address to specify an III. TARGET ARCHITECTURES operand. This includes arithmetic and logical To prove the effectivenes s of this methodology, two micro instructions. controlled processors without default set ISA will be used as case studies . This session will present the original form of these • I-Type: contains the instructions that must operate with processors. a 16-bit immediate operand. A. Achitecture 1 • J-Type: composed of two direct jump instructions . The first architecture is a single-tasking low complexity These instructions require a 26-bit memory address to soft-core processor, whose main feature is showing the Von specify their operands. Neumann model in a theoretical and practical way, through its The MIPS microprocessor h as 32 G eneral Purpose VHDL descri ption and FPGA implementation. This Registers (GPR), all 32-bit length. There is a convention for architecture was original ly proposed in [8 ] as a laboratory names and functionality of each one [3]. Table 1 shows all exercise for digital logic disciplines and modified in [9] for the registers related to their number and function . In addition, there current data path. are two specific registers, HI and LO , used to store It is a 32-bit processor , designed to demonstrate Von multiplication and division results. Neumann architecture from a very simple data path and supporting reconfiguration of the instruction s like a RISP TABLE I. MIPS REGISTERS (Reconfigurable Instruction Set processors) . Figure 1 shows the Number Name Function architecture overview. 0 $0 Constant 0 1 $at Assembly temporary 2-3 $v0 - $v1 Function result registers 4-7 $a0 – $a3 Function Arguments 8-15 $t0 - $t7 Tempor ary registers 16-23 $s0 - $s7 Saved registers to use freely 24-25 $t8 - $t9 Tempor ary registers Reserved for operating system 26-27 $k0 - $k1 kernel and for exception return 28 $gp Global pointer 29 $sp Stack pointer 30 $fp Frame pointer 31 $ra Return address Patterson [6] describes the probable most widespread academic version of the MIPS-1 processor. It is a simple 32-bit RISC architecture in which three data paths propose Figure 1. First processor architecture overview implementations for single-cycle, multi-clcyes and pipeline solutions, but include only a sub-set of the MIPS instruction. This processor has 12 general -purpose registers (R0 to R11), a program counter (register R12), an Arithmetic and An example of a MIPS-1 HDL de scription, used also for Logic Unit (ALU), an Accumulator Register (A) and an ALU academic purpose, is the PLASMA processor. This is a 32-bit Result Register (G). Communication with the memory is done soft-core public domain processor , which implements most of using the channels DIN (Data In) and DOUT (Data Out), the the MIPS-1 instruction set. The Plasma project overview is address ADDR and the control signals W (Write) and R (Read). The IR register stores the current instruction , being executed by Control Unit. The final element is a multiplexer to choose what goes on the bus. Its inputs are: all the registers (R0 – R12), DIN, G and Mask. Mask is a 32 bits signal. The Control Unit can use it to send constants to the bus. The available operations in ALU are: addition, subtraction, and, or, xor, nor, not A, left and right 1-bit shifts (logical and arithmetic) , increment A and first operator (G <= A) . The number of operations requires 4 bits operation select. The ALU also performs logic operations and generates 3 flags (Z, S and CY) to indicate the occurrence of Zero, Signal or Carry conditions in the last arithmetic operation.

Load more