類比電路設計(3349) - 2004
Stability and Frequency Compensation
Ching-Yuan Yang
National Chung-Hsing University Department of Electrical Engineering
Overview z Reading B. Razavi Chapter 10. z Introduction In this lecture, we deal with the stability and frequency compensation of linear feedback systems to the extent necessary to understand design issues of analog feedback circuits. Beginning with a review of stability criteria and the concept of phase margin, we study frequency compensation, introducing various techniques suited to different op amp topologies. We also analyze the impact of frequency compensation on the slew rate of two- stage op amps.
Analog-Circuit Design 10-1 Ching-Yuan Yang / EE, NCHU
1 Basic negative-feedback system z General considerations
Y H (s) ()s = Close-loop transfer function: X 1+ βH (s) if βH(s = jω1) = −1, the gain goes to infinity, and the circuit can amplify is own noise until it eventually begins to oscillate at frequency ω1.
Barkhausen’s Criteria: |βH(s = jω1)| = 1 ∠βH(s = jω1) = −180o . o The total phase shift around the loop at ω1 is 360 because negative feedback itself introduces 180o of phase shift. The 360o phase shift is necessary for oscillation since the feedback must add in phase to the original noise to allow oscillation buildup. By the same token, a loop gain of unity (or greater) is also required to enable growth of the oscillation amplitude.
Analog-Circuit Design 10-2 Ching-Yuan Yang / EE, NCHU
Bode diagram of loop gain z A negative feedback system may oscillate at ω1 if (1) the phase shift around the loop at this frequency is so much that the feedback becomes positive. (2) the loop gain is still enough to allow signal buildup.
Unstable system Stable system
Analog-Circuit Design 10-3 Ching-Yuan Yang / EE, NCHU
2 Time-domain response
Root locus: Pole frequency sP = jωP + σP
σP > 0, unstable with growing (a) amplitude
σP = 0, unstable with constant- amplitude oscillation (b)
σP < 0, stable
(c)
Analog-Circuit Design 10-4 Ching-Yuan Yang / EE, NCHU
Bode plots of one-pole system z Assuming H(s) = A0/(1 + s/ω0), β is less than or equal to unity and does not depend on the frequency, we have A0 Y H (s) 1+ βA ()s = = 0 s X 1+ βH (s) 1+ ω0 ()1+ βA0 z Bode plots of loop gain: Root locus: sP = −ω0(1 + βA0)
20dB/dec
A single pole cannot contribute a
0.1ω0 10ω0 phase shift greater than 90o and the system is unconditionally stable for all non-negative valuesof β.
Analog-Circuit Design 10-5 Ching-Yuan Yang / EE, NCHU
3 Bodes plots of two-pole system z Assuming the open-loop transfer function A H (s) = 0 s s 1+ 1+ ω p1 ω p2 z Bode plots of loop gain:
The system is stable because |βH| drops to below unity at a frequency for which ∠βH < −180o. To reduce the amount of feedback, we decrease β, obtaining the gray magnitude plot in the figure. For a logarithmic vertical axis, a change in β translates the magnitude plot vertically. Note that the phase plot does not change. The stability is obtained at the cost of weaker feedback.
Analog-Circuit Design 10-6 Ching-Yuan Yang / EE, NCHU
Bodes plots of three-pole system z Assuming the open-loop transfer function A H(s) = 0 s s s 1+ 1+ 1+ ω p1 ω p2 ω p3 z Bode plots of loop gain:
If the feedback factor β decreases, the circuit becomes more stable because the gain crossover moves toward the origin while the phase crossover remains constant.
Analog-Circuit Design 10-7 Ching-Yuan Yang / EE, NCHU
4 Phase margin z Close-loop frequency and time response
Small margin Large margin
Analog-Circuit Design 10-8 Ching-Yuan Yang / EE, NCHU
Phase margin (cont’d)
z Phase margin (PM) is defined as o PM = 180 + ∠βH(ω = ω1)
where ω1 is the gain crossover frequency.
z Example
A two-pole feedback system is designed such that | βH(ω = ωP2)| = 1 and
| ωP1| << | ωP2|.
Since ∠βH reaches −135o at
ω = ωP2, the phase margin is equal to 45o.
Analog-Circuit Design 10-9 Ching-Yuan Yang / EE, NCHU
5 How much phase margin is adequate?
o o z For PM = 45 , at the gain crossover frequency ∠βH(ω1) = −135 and Y H ( jω ) H ( jω ) |βH(ω1)| = 1, yielding = 1 = 1 X 1+1⋅exp()− j135° 0.29 − 0.71j
Y 1 1 1.3 = ⋅ ≈ It follows that X β 0.29 − 0.71 j β
The frequency response of the feedback
system suffers from a 30% peak at ω = ω1. z Close-loop frequency response for 45o phase margin:
Analog-Circuit Design 10-10 Ching-Yuan Yang / EE, NCHU
How much phase margin is adequate? (cont’d) z Close-loop time response for 45o, 60o, and 90o phase margin:
o z For PM = 60 , Y(jω1)/X(jω1) = 1/β, suggesting a negligible frequency peaking. This typically means that the step response of the feedback system exhibits little ringing, providing a fast settling. For greater phase margins, the system is more stable but the time response slows down. Thus, PM = 60o is typically considered the optimum value. z The concept of phase margin is well-suited to the design of circuits that process small signals. In practice, the large-signal step response of feedback amplifiers does not follow the illustration of the above figure. For large-signal applications, time-domain simulations of the close-loop system prove more relevant and useful than small-signal ac computations of the open-loop amplifier.
Analog-Circuit Design 10-11 Ching-Yuan Yang / EE, NCHU
6 How much phase margin is adequate? (cont’d) z Example: Unity-gain buffer: PM ≈ 65o, unity-gain frequency = 150 MHz. However, the large-signal step response suffers from significant ringing.
z The large-signal step response of feedback amplifiers is not only due to slewing but also because of the nonlinear behavior resulting from large excursions in the bias voltages and currents of the amplifier. Such excursions in fact cause the pole and zero frequencies to vary during the transient, leading to a complicated time response. Thus, for large-signal applications, time-domain simulations of the close-loop system prove more relevant and useful than small-signal ac computations of the open-loop amplifier.
Analog-Circuit Design 10-12 Ching-Yuan Yang / EE, NCHU
Frequency compensation
z Typical op amp circuits contain many poles. For this reason, op amps must usually be “compensated,” that is, the open-loop transfer function must be modified such that the closed-loop circuit is stable and the time response is well-behaved. z Stability can be achieved by minimizing the overall phase shift, thus pushing the phase crossover out. Moving PX out Discussion: This approach requires that we attempt to minimize the number of poles in the signal path by proper design. Since each additional stage contributes at least one pole, this means the number of stages must be minimized, a remedy that yields low voltage gain and/or limited output swings.
Analog-Circuit Design 10-13 Ching-Yuan Yang / EE, NCHU
7 Frequency compensation (cont’d)
z Stability can be achieved by dropping Moving GX in the gain thereby pushing the gain crossover in. Discussion:
This approach retains the low frequency gain and the output swings but it reduces the bandwidth by forcing the gain to fall at lower frequencies.
Analog-Circuit Design 10-14 Ching-Yuan Yang / EE, NCHU
Telescopic op amp with single-ended output z Determine the poles of the circuit: We identify a number of poles in the signal paths: path 1 contains a high-frequency pole at the source
of M3, a mirror pole at node A, and another
high-frequency pole at the source of M7, whereas path 2 contains a high-frequency pole at the source
of M4. The two paths share a pole at the output. Dominant pole: the closest to the origin.
ωp,out = 1/(RoutCL), usually sets the open-loop 3-dB bandwidth. Nondominant poles:
ωp,A = gm5/CA, the closest pole to the origin after ωp,out. Pole locations: (mirror pole) where CA = CGS5 + CGS6 + CDB5 + 2CGD6 + CDB3 + CGD3.
ωp,N = gm7/CN, ωp,X = gm3/CX = gm4/CY = ωp,Y.
Since gm = 2ID/|VGS − VTH|, if M4 and M7 are designed to have the same overdrive, they exhibit the same transconductance. From square-law characteristics, we have
W4/W7 = µp/µn ≈ 1/3. Thus, nodes N and X(Y) see roughly equal small-signal resistances but node N suffers from much more capacitance.
Analog-Circuit Design 10-15 Ching-Yuan Yang / EE, NCHU
8 Telescopic op amp with single-ended output (cont’d) z Bode plots of loop gain for op amp: using β = 1 for the worst case.
The mirror pole ωp,A typically limits the phase margin because its phase contribution occurs at lower frequencies than that other nondominant poles.
Analog-Circuit Design 10-16 Ching-Yuan Yang / EE, NCHU
Telescopic op amp with single-ended output (cont’d) z Translating the dominant pole toward origin to compensate the op amp:
Assuming ωp,A > 10ω p,out, we must force the loop gain crossover point moves toward the origin. We can simply lower the frequency of the dominant pole
(ω p,out) by increasing the load capacitance. The key point is that the phase contribution of the dominant pole in the vicinity of the gain or phase crossover points is close to 90o and relatively independent of the location of the pole. That is, translating the dominant pole toward the origin affects the magnitude plot but not the critical part of the phase plot.
Analog-Circuit Design 10-17 Ching-Yuan Yang / EE, NCHU
9 Telescopic op amp with single-ended output (cont’d) z How much the dominant pole must be shift down? Assume (1) the 2nd nondominant pole (ωp,N) is quite higher than the mirror pole so that the phase shift at ω = ωp,A is equal to −135o, and (2) PM = 45o.
CL → (ωp,out/ω’p,out)CL. The load capacitance must be increased by a factor of ωp,out/ω’p,out. The unity-gain bandwidth of the compensated op amp is equal to the frequency of the nondominant pole. To achieve a wideband in a feedback system employing an op amp, the first nondominant pole must be as far as possible. −1 z Although ωp,out = (RoutCL) , increasing Rout does not compensate the op amp. A higher Rout results in a greater gain, only affecting the low-frequency portion of the characteristics.
Analog-Circuit Design 10-18 Ching-Yuan Yang / EE, NCHU
Fully differential telescopic op amp
z CN = CGS5 + CSB5 + + CGD7 + CDB7 −1 ZN = ro7 || (CN s) , where body effect is neglected. We have 1 1+ g r r ro7 ( m5 o5 ) o7 Z = ()1+ g r Z + r ≈ ()1+ g r Zout = out m5 o5 N o5 m5 o5 C s 1+ g r r C + r C s +1 ro7CN s +1 ,and L []()m5 o5 o7 L o7 N z A pole with τ = (1 + gm5ro5)ro7CL + ro7CN, where (1 + gm5ro5)ro7CL is simply due to the low-frequency output resistance of the cascode. The pole in the PMOS cascode is merged with the output pole, thus creating no addition pole. It merely lowers the dominant pole by a slight amount. z For gmro >> 1 and CL > CN, then τ ≈ gm5ro5ro7CL.
Analog-Circuit Design 10-19 Ching-Yuan Yang / EE, NCHU
10 Compensation of two-stage op amps
z We identify three poles at X(orY), E(orF) and A(orB). A pole at X(orY) lies at relatively high frequencies. Since the small-signal resistance seen at E is quite high, even the capacitances of M3, M5 and M9 can create a pole relatively close to the origin. At node A, the small-signal resistance is lower but the value of CL may be quite high. Consequently, the circuit exhibits two dominant poles. z One of the dominant poles must be moved toward the origin so as to place the gain crossover well below the phase crossover. If the magnitude of ωp,E is to be reduced, the available bandwidth is limited to approximately ωp,A, a low value. Furthermore, this required dominant pole translates to a very large compensation capacitor.
Analog-Circuit Design 10-20 Ching-Yuan Yang / EE, NCHU
Miller compensation of a two-stage op amp
z In a two-stage amp as shown in Fig.(a), the first stage exhibits a high output impedance and the second stage provides a moderate gain, thereby providing a suitable environment for Miller multiplication of capacitors.
1 z In Fig.(b), we create a large capacitance at E, the pole is ω p,E = Rout1[]CE + ()1+ Av2 CC As a result, a low-frequency pole can be established with a moderate capacitor value, saving considerable chip area. z In addition to lowering the required capacitor value, Miller compensation entails a very important property: it moves the output pole away from the origin. (pole splitting)
Analog-Circuit Design 10-21 Ching-Yuan Yang / EE, NCHU
11 Miller compensation of a two-stage op amp (cont’d) z Pole splitting as a result of Miller compensation.
z Discussion z Two poles: (based on the assumption |ωp,1| << |ωp,2|) 1 Simplified circuit of a two-stage op amp: ω p1 ≈ RS []()()1+ gm9RL CC + CGD9 + CE + RL ()CC + CGD9 + CL st RS = the output resistance of 1 stage.
RS [(1+ gm9RL )(CC + CGD9 ) + CE ]+ RL (CC + CGD9 + CL ) R = r || r ω p2 ≈ L o9 o11 RS RL []()()CC + CGD9 CE + CC + CGD9 CL + CECL z For CC = 0 and relatively large CL, ωp,2 ≈ 1/(RLCL).
For CC ≠ 0 and CC + CGD9 >> CE, ωp,2 ≈ gm9/(CE + CL).
Typically CE << CL, we conclude that Miller compensation increases the magnitude of the output
pole (ωp,2) by a factor of gm9RL, a relatively large value. z Miller compensation moves the interstage pole toward the origin and the output pole away from the origin, allowing a much greater bandwidth than that obtained by merely connect the compensation capacitor from one node to ground.
Analog-Circuit Design 10-22 Ching-Yuan Yang / EE, NCHU
Miller compensation of a two-stage op amp (cont’d) z Effect of right half plane zero The circuit contains a right-half-plane zero at
ωz = gm9/(CC + CGD9) because CC + CGD9 forms a “parasitic” signal path from the input to the output. A zero in the right hand plane contributes more phase shift, thus moving the phase crossover toward the origin. Furthermore, from Bode approximations, the zero slows down the drop of the magnitude, thereby pushing the gain crossover away from the origin. As a result, the stability degrades considerably.
For two-stage op amps, typically |ωp1| < |ωz| < |ωp2|, the zero introduces significant phase shift while preventing the gain from falling sufficiently. The right-half-plane zero is a serious issue
because gm is relatively small and CC is chosen large enough to position the dominant pole properly.
Analog-Circuit Design 10-23 Ching-Yuan Yang / EE, NCHU
12 Miller compensation of a two-stage op amp (cont’d)
z Addition of Rz to move the right hand plane zero.
The zero is given by . −1 If Rz ≥ gm9 , then ωz ≤ 0.
We may move the zero well into the left plane so as to cancel the first nondominant pole. That is
1 − gm9 CL + CE + CC CL + CC −1 = ⇒ Rz = ≈ , because CE << CL + CC . CC (gm9 − Rz ) CL + CE gm9CC gm9CC • Drawbacks: 1. It is difficult to guarantee the relationship of the above equation,
especially if CL is unknown or variable. 2. The actual implementation of Rz is variable. Rz is typically realized by a MOS transistor in the triode region.
Analog-Circuit Design 10-24 Ching-Yuan Yang / EE, NCHU
Miller compensation of a two-stage op amp (cont’d) z Generation of Vb for proper temperature and process tracking.
If I1 is chosen with respect to ID9 such that
VGS13 = VGS9, then VGS15 = VGS14.
Since gm14 = µpCox(W/L)14(VGS14 − VTH14) −1 and Ron15 = [µpCox(W/L)15(VGS15 − VTH15)] ,
(W / L)14 we have Ron15 = gm14 (W / L)15
(W / L) C + C 14 = L C For pole-zero cancellation to occur, gm14 (W / L)15 gm9CC
I D9 CC and hence (W / L)15 = (W / L)14 (W / L)9 I D14 CC + CL
If CL is constant, it can be established with reasonable accuracy because it contains only the ratio of quantities.
Analog-Circuit Design 10-25 Ching-Yuan Yang / EE, NCHU
13 Miller compensation of a two-stage op amp (cont’d) z Method of defining gm9 with respect to RS.
C L + CC Goal: Rz = ⋅⋅⋅⋅⋅⋅⋅⋅ (A) g m9CC
The technique incorporates Mb1-Mb4
−2 along with RS to generate Ib ∝ RS
−1 Thus, gm9 ∝ I D9 ∝ I D11 ∝ RS
Proper ratioing of RZ and RS therefore ensures (A) is valid even with temperature and process variations
Analog-Circuit Design 10-26 Ching-Yuan Yang / EE, NCHU
Effect of increased load capacitance on step response
One-stage op amps: Two-stage op amps:
z In one-stage op amps, a higher load capacitance brings the dominant pole closer to the origin, improving the phase margin (albeit making the feedback system more overdamped). z In two-stage op amps, since Miller compensation establishes the dominant pole at the output of the first stage, a higher load capacitance presented to the second stage moves the second pole toward the origin, degrading the phase margin. z Illustrated in the figure is the step response of a unity-gain feedback amplifier, suggesting that the response approaches an oscillatory behavior if the load capacitance seen by the two-stage op amp increases.
Analog-Circuit Design 10-27 Ching-Yuan Yang / EE, NCHU
14 Slewing in two-stage op amps
Positive slewing: negative slewing:
z The positive slew rate equals ISS /CC. During slewing, M5 must provide two currents: ISS and I1. If M5 is not wide enough to sustain ISS + I1 in saturation, then VX drops significantly, possibly driving M1 into the triode region. z During negative slew rate, I1 must support both ISS and ID5. For example,
if I1 = ISS, then VX rises so as to turn off M5. If I1 < ISS, then M3 enters the
triode region and the slew rate is given by ID3 /CC.
Analog-Circuit Design 10-28 Ching-Yuan Yang / EE, NCHU
Compensation technique using a source follower z Two-stage op amp with right half plane zero due to CC:
z Addition of a source follower to remove zero:
Since CGS of M2 is typically much less than CC, we expect the right frequencies.
−1 −Vout − gm1V1 = Vout (RL + CLs) Ö V1 = ()1 + RLCLs gm1RL V −V V and out 1 + I = 1 , then 1 1 in + RS Equivalent circuit: Zero in the left hand plane gm2 CCs
Source follower Vout − gm1RLRS(gm2 +CCs) = 2 Vin RLCLCC(1+ gm2RS )s + [](1+ gm1gm2RLRS )CC + gm2RLCL s + gm2
Assume ωp1 << ωp2, since typically 1 + gm2RS >> 1, (1 + gm1gm2RLRS)CC >> gm2RLCL, we have 1 gm1 1 gm1 ω p1 ≈ and ω ≈ (Note ω :)→ g R R C p2 p2 R C C m1 L S C CL L L L
Analog-Circuit Design 10-29 Ching-Yuan Yang / EE, NCHU
15 Compensation technique using a CG stage
Equivalent circuit:
z The primary issue is that the source follower limits the lower end of the
output voltage to VGS2 + VI2. In the CG topology, CC and the CG stage M2 convert the output voltage swing to a current, returning the result to the
gate of M1. 1 V1 gm2V2 I g V z V + = −V , gm1V1 +Vout + CLs = gm2V2 and in = + m2 2 , we obtain out 2 R R CC s L S
Vout − gm1RS RL (gm2 + CS s) = 2 Iin RLCLCC s + []()1+ gm1RS gm2RLCC + CC + gm2RLCL s + gm2
1 gm2RS gm1 Using approximations, ω p1 ≈ andω p2 ≈ . gm1RL RSCC CL
Analog-Circuit Design 10-30 Ching-Yuan Yang / EE, NCHU
Compensation technique using a CG stage (cont’d)
Positive slewing:
z For positive slewing, M2 and I1 must support ISS,
requiring I1 ≥ ISS + ID1. If I1 is less, then VP drops,
turning M1 off, and if I1 < ISS, M0 and its tail current source must enter the triode region,
yielding a slew rate equal to I1/CC.
z For negative slewing, I2 must support both ISS
and ID2. As ISS flows into node P, VP tends to rise, increasing I . Thus, M absorbs the current Negative slewing: D1 1 produced by I3 through CC, tuning off M2 and
opposing the increase in VP. We can therefore consider P a virtual ground node.
z For equal positive and negative slew rates, I3
(and hence I2) must be as large as ISS, raising the power dissipation.
Analog-Circuit Design 10-31 Ching-Yuan Yang / EE, NCHU
16 Alternative method of compensation two-stage op amps
Analog-Circuit Design 10-32 Ching-Yuan Yang / EE, NCHU
17