The TL431 in the Control of Switching Power Supplies Agenda

Vout is permanently compared to a reference voltage Vref. The reference voltage Vref is precise and stable over temperature.

The error,ε =−VVrefα out , is amplified and sent to the control input. The power stage reacts to reduce ε as much as it can. Power stage - H

Vout

Control d variable Error amplifier - G

Rupper + -

Vin -

- α

+ +

Vp Modulator - G V PWM ref Rlower How is Regulation Performed? Text books only describe op amps in compensators…

Vout

Verr

The market reality is different: the TL431 rules! V I’m the out law! Verr

TL431 optocoupler How do we Stabilize a Converter? We need a high gain at dc for a low static error We want a sufficiently high crossover frequency for response speed ¾ Shape the compensator G(s) to build phase and gain margins!

Ts( )

fc = 6.5 kHz 0° -0 dB

∠Ts( ) -88° GM = 67 dB

ϕm = 92° -180° Ts( ) =−67 dB

10 100 1k 10k 100k 1Meg How Much Phase Margin to Chose?

a Q factor of 0.5 (critical response) implies a ϕm of 76° a 45° ϕm corresponds to a Q of 1.2: oscillatory response!

10 Q < 0.5 over damping 1.80 Q = 5 Q = 0.5 critical damping Q = 1 Q > 0.5 under damping 7.5 Q 1.40 Q = 0.707 Asymptotically stable 1.00 5 ϕm

600m Q = 0.5 Fast response 2.5 76° and no overshoot! 200m Q = 0.5 Q = 0.1 0 5.00u 15.0u 25.0u 35.0u 45.0u 0 255075100

phase margin depends on the needed response: fast, no overshoot…

good practice is to shoot for 60° and make sure ϕm always > 45° Which Crossover Frequency to Select? crossover frequency selection depends on several factors:

switching frequency: theoretical limit is Fsw 2

¾ in practice, stay below 1/5 of Fsw for noise concerns output ripple: if ripple pollutes feedback, «tail chasing» can occur. ¾ crossover frequency rolloff is mandatory, e.g. in PFC circuits presence of a Right-Half Plane Zero (RHPZ): ¾ you cannot cross over beyond 30% of the lowest RHPZ position output undershoot specification: ¾ select crossover frequency based on undershoot specs

ΔIout Vp ≈ 2π fcC out Vout(t) What Compensator Types do we Need?

There are basically 3 compensator types: ¾ type 1, 1 pole at the origin, no phase boost ¾ type 2, 1 pole at the origin, 1 zero, 1 pole. Phase boost up to 90° ¾ type 3, 1 pole at the origin, 1 zero pair, 1 pole pair. Boost up to 180°

Gs() Gs( ) Gs( ) boost boost

−270° ∠=−°Gs() 270 −270° ∠Gs( ) ∠Gs( ) 1 2 5 10 20 50 100 200 500 1k 10 100 1k 10k 100k 10 100 1k 10k 100k Type 1 Type 2 Type 3 Agenda

Feedback generalities The TL431 in a compensator Small-signal analysis of the return chain A type 1 implementation with the TL431 A type 2 implementation with the TL431 A type 3 implementation with the TL431 Design examples Conclusion The TL431 Programmable Zener The TL431 is the most popular choice in nowadays designs It associates an open-collector op amp and a reference voltage The internal circuitry is self-supplied from the cathode current When the R node exceeds 2.5 V, it sinks current from its cathode

K R K

TL431A R

A 2.5V R A K A

The TL431 is a shunt regulator The TL431 Programmable Zener The TL431 lends itself very well to optocoupler control Fast lane Slow lane Vdd Vout Vout

RLED Rpullup RLED R1

I1 VFB 1V ILED Ibias = Rbias Rbias Rbias VVf ≈1 I C2 C1 1

TL431 Rlower VVmin = 2.5 dc representation

RLED must leave enough headroom over the TL431: upper limit! The TL431 Programmable Zener This LED resistor is a design limiting factor in low output voltages:

VVVout− f− TL431,min RRLED,max≤ pullupCTR min VVdd−+ CE,min sat I biasCTR R pullup

When the capacitor C1 is a short-circuit, RLED fixes the fast lane gain

Vsout ( ) R LED R1 Vdd VsFB()= −⋅ CTR R pullup ⋅ I1 I1 Vs() R out pullup I1 = 0 V RLED in ac Ic Vs() FB Vs() R FB =−CTR pullup Rlower Vsout() R LED

This resistor plays a role in dc too! The TL431 – the Static Gain Limit Let us assume the following design: 512.5− − VV= 5 RLED,max ≤××20k 0.3 out 4.8−+×× 0.3 1mk 0.3 20 VVf = 1

VVTL431,min = 2.5

VVdd = 4.8

VmVCE, sat = 300 RLED,max ≤Ω857

ImAbias = 1

CTRmin = 0.3

Rkpullup =Ω20 Rpullup 20 GordB0 >>>≈CTR 0.3 7 17 RLED 0.857

In designs where RLED fixes the gain, G0 cannot be below 17 dB You cannot “amplify” by less than 17 dB The TL431 – the Static Gain Limit You must identify the areas where compensation is possible

dB ° 40.0 180 Not ok Requires f > 500 Hz less c 20.0 90.0 Hs ( ) than 17 dB of gain

0 0

-17 dB -20.0 -90.0 arg H (s) Requires 17 dB -40.0 -180 ok or more

10 100500 1k 10k 100k TL431 – Injecting Bias Current A TL431 must be biased above 1 mA to guaranty its parameters If not, its open-loop suffers – a 10-dB difference can be observed!

> 10-dB difference

I Easy bias Ibias = 1.3 mA solution

Rbias

Ibias = 300 µA

1 R = =Ω1 k bias 1m Agenda

Feedback generalities The TL431 in a compensator Small-signal analysis of the return chain A type 1 implementation with the TL431 A type 2 implementation with the TL431 A type 3 implementation with the TL431 Design examples Conclusion TL431 – Small-Signal Analysis The TL431 is an open-collector op amp with a reference voltage Neglecting the LED dynamic resistance, we have:

Vs VsVsout()− op ( ) out ( ) Is()= 1 R LED 1

RLED R1 sC1 1 Vsop()=− V out s () =− V out () s RuppersR upper C1 C1 I1 11⎡ ⎤ Is1 ()=+ Vout s ()⎢1 ⎥ ≈ 0 RLED⎣⎢ sR upper C1 ⎦⎥

We know that: VsFB()= −⋅ CTR R pullup ⋅ I1

Rlower Vsop () VsFB ( ) RpullupCTR⎡ 1+ sR upper C1 ⎤ ()=− ⎢ ⎥ Vsout R LED⎣⎢ sRC upper 1 ⎦⎥ TL431 – Small-Signal Analysis In the previous equation we have:

Rpullup 9 a static gain G0 =CTR RLED 1 9 a 0-dB origin pole frequency ωpo = CR1 upper 1 9 a zero ω = z1 RupperC1 We are missing a pole for the type 2!

Vdd Type 2 transfer function R pullup Add a cap. from Vs() collector to ground FB ⎡ ⎤ VsFB () RsRCpullupCTR 1+ upper 1 ()=− ⎢ ⎥ C2 Vs R sR C1+ sR C out LED ⎣⎢ upper12() pullup ⎦⎥ TL431 – Small-Signal Analysis The optocoupler also features a parasitic capacitor

¾ it comes in parallel with C2 and must be accounted for

Vout(s)

Vdd

Rpullup

V (s) FB FB c

C Copto

CCC2 = || opto e optocoupler TL431 – Small-Signal Analysis The optocoupler must be characterized to know where its pole is

Cdc Rled Ic 10uF 20k

2 5 Rpullup ∠Os( ) 20k Rbias

VFB 1 3 Vdd 5 X1 4 6 SFH615A-4 Os() Vbias Vac IF -3 dB

4 k

Adjust Vbias to have VFB at 2-3 V to be in linear region, then ac sweep The pole in this example is found at 4 kHz

11 Another design CnF== ≈2 opto constraint! 26.28204π Rfpullup pole ×× kk Agenda

Feedback generalities The TL431 in a compensator Small-signal analysis of the return chain A type 1 implementation with the TL431 A type 2 implementation with the TL431 A type 3 implementation with the TL431 Design examples Conclusion The TL431 in a Type 1 Compensator To make a type 1 (origin pole only) neutralize the zero and the pole

Vs() RsRCCTR⎡ 1+ ⎤ FB =− pullup⎢ upper 1 ⎥ Vs() R sR C1+ sR C out LED ⎣⎢ upper12() pullup ⎦⎥ R substitute 1 pullup ω = sRCsRCupper12= pullup CC12= po RRupper LED Rupper C1 CTR CTR RpullupCTR ω = C = po CR 2 2 LED 2π fRpo LED

Once neutralized, you are left with an integrator

1 f po CTR Gs()= ||Gf()= f = Gf C2 = s c pofcc 2πGfR fc fc cLED

ω po TL431 Type 1 Design Example We want a 5-dB gain at 5 kHz to stabilize the 5-V converter

VVout = 5

VVf = 1 Apply 15% VVTL431,min = 2.5 margin VVdd = 4.8 RLED,max ≤ 857 Ω RLED = 728 Ω VmVCE, sat = 300

ImAbias = 1

CTRmin = 0.3

Rkpullup =Ω20 5 20 G fc ==10 1.77 CTR 0.3 CnF2 == ≈7.4 fkHz10 2πGfR 6.28××× 1.77 5 k 728 c = fcLEDc

Copto = 2 nF Rpullup CnnnF= 7.4−= 2 5.4 CCnF12=≈14.7 Rupper TL431 Type 1 Design Example SPICE can simulate the design – automate elements calculations…

parameters Vout=5 Vf=1 Vref=2.5 VCEsat=300m Vdd=4.8 E1 Ibias=1m Vdd -1k L1 A=Vout-Vf-Vref {Vdd} 4.99V 1k 4.99V 4.99V B=Vdd-VCEsat+Ibias*CTR*Rpullup 4.80V err Rmax=(A/B)*Rpullup*CTR 6 5 7 Rupper=(Vout-2.5)/250u Rpullup RLED R2 R5 2.50V fc=5k {Rpullup} {RLED} {Rupper} 100m 9 Gfc=-5 2.50V 2.50V 4.99V 3.97V 2 10 G=10^(-Gfc/20) VFB 4 3 C3 B1 pi=3.14159 Voltage R6 1k V2 Fpo=G*fc 0V V(err)<0 ? 2.5 1k 0 : V(err) C1 Rpullup=20k {C1} V3 Cpole 2.96V AC = 1 RLED=Rmax*0.85 {Cpole} 1 C1=Cpole1*Rpullup/Rupper X2 Cpole1=CTR/(2*pi*Fpo*RLED)Optocoupler R3 Cpole=Cpole1-Copto Cpole = Copto X1 Automatic bias CTR = CTR 10k Fopto=4k TL431_G Copto=1/(2*pi*Fopto*Rpullup) point selection CTR = 0.3 TL431 Type 1 Design Example We have a type 1 but 1.3 dB of gain is missing? Hu? dB 20.0 Gs() 10.0 3.7 dB 0

-10.0

-20.0

° 270 argGs( ) 180

90.0

-90.0 100 200 500 1k 2k 5k 10k 20k 50k 100k TL431 Type 1 Design Example

The 1-kΩ resistor in parallel with the LED is an easy bias However, as it appears in the loop, does it affect the gain?

Vout(s) VIRIRFB= c pullup= L pullupCTR R RLED II= bias L 1 RR+ ac representation bias d I1 VRout bias IL = VFB(s) I I L b RLED++RRRR bias|| d bias d I R c d R bias R CTR VFB pullup Rbias s=0 = Rpullup VRRRRR++|| Vf out LED bias d bias d

CTR

Both bias and dynamic resistances have a role in the gain expression TL431 Type 1 Design Example

A low operating current increases the dynamic resistor

SFH615A-2 -FORWARD CHARACTERISTICS

0.002000 Rpullup = 20 kΩ, IF = 300 µA (CTR = 0.3) R = 158 Ω 0.001800 d

0.001600 Rpullup = 1 kΩ, IF = 1 mA (CTR = 1) 0.001400 Rd = 38 Ω 0.001200 I = 1 mA IF @ 110°C 0.001000 F IF @ 70°C 0.000800 IF @ 25°C

0.000600 IF @ -20°C IF Forward Current(A) Forward IF IF @ -40°C 0.000400 IF = 300 µA 0.000200

0.000000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VF Forward Voltage (Volts) Make sure you have enough LED current to reduce its resistance TL431 Type 1 Design Example The pullup resistor is 1 kΩ and the target now reaches 5 dB dB Yes! 20.0 Gs() 10.0 5 dB 0

-10.0

-20.0

° 270 argGs( ) 180

90.0

-90.0 100 200 500 1k 2k 5k 10k 20k 50k 100k Agenda

Vdd

Vout Rpullup G0 =CTR Rpullup RLED R 1 RLED V FB 1 ω = z1 RupperC1 Rbias

C C 1 2 1 ω = p1 RpullupC2 TL431 Rlower

Just make sure the optocoupler contribution is involved… TL431 Type 2 Design Example

You need to provide a 15-dB gain at 5 kHz with a 50° boost

f =+⎡⎤tan()boost tan2 boost () +=×= 1 f 2.74 5 k 13.7 kHz pc⎣⎦ R 2 G = CTRpullup == 1015 20 5.62 fzcp==ff25 k 13.7 k ≈ 1.8 kHz 0 RLED With a 250-µA bridge current, the divider resistor is made of:

Rlower ==Ω2.5 250uk 10 R1 = (12−=Ω 2.5) 250uk 38

The pole and zero respectively depend on Rpullup and R1:

CfRpF2 ==12π ppullup 581 CfRnF11=12π z = 2.3 The LED resistor depends on the needed mid-band gain:

RpullupCTR ok RLED ==Ω1.06 k RLED,max ≤ 4.85 kΩ G0 TL431 Type 2 Design Example

The optocoupler is still at a 4-kHz frequency:

CnFpole ≈ 2 Already above! Type 2 pole capacitor calculation requires a 581 pF cap.!

The bandwidth cannot be reached, reduce fc! For noise purposes, we want a minimum of 100 pF for C With a total capacitance of 2.1 nF, the highest pole can be: 11 f pole == =3.8 kHz 2π RCpullup 6.28×× 20 k 2.1 n For a 50° phase boost and a 3.8-kHz pole, the crossover must be:

f p fc =≈1.4 kHz tan()boost++ tan2 boost () 1 TL431 Type 2 Design Example

The zero is then simply obtained: 2 fc fz ==516 Hz f p We can re-derive the component values and check they are ok

CfRnF2 ==12π ppullup 2.1 CfRnF11=12π z = 8.1 Given the 2-nF optocoupler capacitor, we just add 100 pF

In this example, RLED,max is 4.85 kΩ

Rpullup 20 GordB0 >>>≈CTR 0.3 1.2 1.8 RLED 4.85

You cannot use this type 2 if an attenuation is required at fc! TL431 Type 2 Design Example

The 1-dB gain difference is linked to Rd and the bias current dB 30.0 Gs() 20.0

10.0

0 14 dB @ 1.4 kHz -10.0

° 140 argGs( ) 130

120 50° 110

100 10 100 1k 10k 100k TL431 – Suppressing the Fast Lane The gain limit problem comes from the fast lane presence

Its connection to Vout creates a parallel input ¾ The solution is to hook the LED resistor to a fixed bias

Vdd Vout Vdd Vout Vbias Vz

Rz Rpullup RLED R1 Rpullup RLED R1

Comp. network VFB changes! VFB R Rbias bias R2

C2 C2 C1 C1 TL431 TL431 Rlower Rlower TL431 – Suppressing the Fast Lane The equivalent schematic becomes an open-collector op amp

Vout Vdd Vz Vsout ( )

RLED R1 Rpullup

Gs1 ( ) VFB R C1 2 Gs( )

C2 Os( ) Transmission Rlower chain – O(s) Vref

Compensaton VsFB ( ) chain – G1(s) TL431 – Suppressing the Fast Lane The small-signal ac representation puts all sources to 0

Vout R 1 Os()= pullup CTR RsRC1+ LED pullup pole R1

Gs( )

R 1+R C Os() V C1 2 21 FB Gs1()= sRC11

−IC IL C2 R CTR RLED lower

Rpullup TL431 – Suppressing the Fast Lane The op amp can now be wired in any configuration! Just keep in mind the optocoupler transmission chain R 1 Os()= pullup CTR RsRCLED1+ pullup pole Wire the op amp in type 2A version (no high frequency pole)

1+R21 C Gs1()= sRC11 When cascaded, you obtain a type 2 with an extra gain term

R 1+RC Gs()= pullup CTR 21 RLED sR11 C()1+ sRpullup C pole

G2 TL431 Type 2 Design Example – No Fast Lane

We still have a constraint on RLED but only for dc bias purposes

VVVzfTL− − 431,min RRLED,max≤ pullupCTR min VVdd−+ CE,min sat I biasCTR R pullup

You need to attenuate by -10-dB at 1.4 kHz with a 50° boost The poles and zero position are that of the previous design

VVz = 6.2

VVf = 1 Apply 15% VVTL431,min = 2.5 margin VVdd = 4.8 RLED,max ≤1.5 kΩ RLED =1.27 kΩ VmVCE, sat = 300

ImAbias = 1

CTRmin = 0.3 Rk=Ω20 pullup fzp= 516Hz f= 3.8 kHz TL431 Type 2 Design Example – No Fast Lane We need to account for the extra gain term:

Rpullup 20k G2 ==CTR = 0.3 4.72 RLED 1.27k The required total mid-band attenuation at 1.4 kHz is -10 dB G ==10−10 20 0.316 fc The mid-band gain from the type 2A is therefore:

G0 0.316 GdB1 == =0.067 or − 23.5 2 G2 4.72 ⎛⎞f c +1 ⎜⎟ ⎝⎠f p Calculate R2 for this attenuation: RGR==Ω2.6 k 211 2 ⎛⎞f ⎜⎟z +1 ⎝⎠fc TL431 Type 2 Design Example – No Fast Lane An automated simulation helps to test the calculation results parameters

Vout=12 Rupper=(Vout-2.5)/250u fc=1.4k Gfc=10 Vf=1 Zener D1 Ibias=1m 1N827A C4 Vref=2.5 E1 value Vdd 0.1u -1k VCEsat=300m {Vdd} R5 5.00V 6.17V 1k 12.0V Vdd=5 Err Vz=6.2 6 5 12.0V CoL Rpullup=20k R4 R1 LoL 12 1kF 2.50V Fopto=4k {Rpullup} {RLED} 0V 1kH 9 14 Copto=1/(2*pi*Rpullup*Fopto) Rupper 12.0V 2.51V 4.32V {Rupper} CTR=0.3 13 Vref Vout 4 2 B1 2.50V 2.5 G1=Rpullup*CTR/RLED X2 Vac Voltage G2=10^(-Gfc/20) Optocoupler 11 V(err) Rbias G=G2/G1 Cpole = Copto CTR = CTR 1k pi=3.14159 C2 3.31V 2.50V fz=516 {C2} 1 10 fp=3.8k C1 R2 {R2} C1=1/(2*pi*fz*R2) {C1} Cpole2=1/(2*pi*fp*Rpullup) Rlower C2=Cpole2-Copto X1 10k a=(fz^2+fc^2)*(fp^2+fc^2) TL431_G c=(fz^2+fc^2) R2=(sqrt(a)/c)*G*fc*Rupper/fp Rmax1=(Vz-Vf-Vref) Rmax2=(Vdd-VCEsat+Ibias*(Rpullup*CTR)) RLED=(Rmax1/Rmax2)*Rpullup*CTR*0.85 TL431 Type 2 Design Example – No Fast Lane The simulation results confirm the calculations are ok dB 10.0 Gs() 0

-10.0

-20.0

-30.0 -10 dB @ 1.4 kHz

° 150 argGs( )

130

110 50°

90.0

70.0 10 100 1k 10k 100k TL431 Agenda

Vdd Vout 1 1 f = f = z 1 z2 2π RC11 2π ()RRC+ Rpullup RLED Rpz R1 LED pz pz 1 1 f = f p = p 1 2π R C 2 2||π RCC C pz pz pz pullup()2 opto

R G = pullup CTR RLED Rbias

C2 C1 RLED fixes the gain and a zero position Rlower

Suppress the fast lane for an easier implementation! TL431 The TL431 in a Type 3 Compensator Once the fast lane is removed, you have a classical configuration

Vdd Vout Vz 1 f = z 1 Rz 2π RC21 Rpullup RLED R1 R3 1 f = z2 2π RC13 C 1 3 f = R p 1 bias 2π RC33

1 C f = 2 p2 C1 R2 2||π RCCpullup()2 opto R G = pullup CTR Rlower RLED

TL431 TL431 Type 3 Design Example – No Fast Lane We want to provide a 10-dB attenuation at 1 kHz The phase boost needs to be of 120° ¾ place the double pole at 3.7 kHz and the double zero at 268 Hz Calculate the maximum LED resistor you can accept, apply margin

VVVzfTL−−431,min X 0.85 RLED,max≤≤ΩRk pullupCTR min 1.5 1.3 kΩ VVdd−+ CE,min sat I biasCTR R pullup

We need to account for the extra gain term:

Rpullup 20k G2 ==CTR = 0.3 4.6 RLED 1.3k The required total mid-band attenuation at 1 kHz is -10 dB G ==10−10 20 0.316 fc

TL431 TL431 Type 3 Design Example – No Fast Lane

The mid-band gain from the type 3 is therefore:

G0 0.316 GdB1 == =0.068 or − 23.3 G2 4.6

Calculate R2 for this attenuation:

22 ⎛⎞ff ⎛⎞ 11++cc ⎜⎟ ⎜⎟ GR f ffpp 11p1 ⎝⎠12 ⎝⎠ R2 ==Ω744 ff− 2 2 pz11 ⎛⎞fz ⎛⎞f 11++⎜⎟1 ⎜⎟c ff⎜⎟ ⎝⎠cz⎝⎠2

CnFCpFCnFCnF123===800 148 14.5opto = 2 The optocoupler pole limits the upper double pole position The maximum boost therefore depends on the crossover frequency TL431 Type 3 Design Example – No Fast Lane

The decoupling between Vout and Vbias affects the curves dB 10.0 Gs() -9.3 dB @ 1 kHz 0

-10.0

-20.0 Isolated 12-V dc source -30.0 -10 dB @ 1 kHz

° 240 argGs( )

200

160 135° 120

80.0

1 10 100 1k 10k 100k TL431 Agenda

Feedback generalities The TL431 in a compensator Small-signal analysis of the return chain A type 1 implementation with the TL431 A type 2 implementation with the TL431 A type 3 implementation with the TL431 Design examples Conclusion Design Example 1 – a Single-Stage PFC The single-stage PFC is often used in LED applications It combines isolation, current-regulation and power factor correction Here, a constant on-time BCM controller, the NCL30000, is used

141V 1 19 1 V = 1 µs 598mV a vc Dc 2 duty-cycle 68.4V X2 Vout Fsw XFMR 5 RATIO = -250m 52.5V I = 2.4 A 3.09V (kHz) Fsw -210V out PWM switch BCM switch PWM 8.74V Ip 7 8 Ip V1 6 p {Vrms*1.414} 154mV c 3 R2 R7 X1 R1 X5 50m 65k PWMBCMVM 100m GAIN K = Gpwm D4 50 V L = L GAIN 52.5V 1N965 26.9V 9 11 2 A string 0V 4 1.57V 22 B1 C1 C5 L1 Voltage 2.2mF 0.1uF {L} Rsense V(errac)-0.6 0.5 1.24V Vsense 23

parameters Vdd 15.1V {Vdd} 1.25 VILED1.24V 14 10 Vrms=100 R5 Ac out L=400u 5.00V {RLED} R4 18 {Rupper} Ct=1.5n VFB R6 Icharge=270u LoL {Rpullup} errac 1k 2.17V Gpwm=(Ct/Icharge)*1Meg 2.17V 12.2V 2.17V 29 17 16 X4 Optocoupler Cpole = Copto C4 R9 CoL On-time CTR = CTR {C1} {R2} 1k C2 11.1V 0V {C2} 13 28 selection 20 1.24V AC = 1 15 1.24V ac in V3 X3 TLV431 Average simulation Design Example 1 – a Single-Stage PFC Once the converter elements are known, ac-sweep the circuit Select a crossover low enough to reject the ripple, e.g. 20 Hz dB 0 8.00 Hs() -2.5 dB 4.00 20 Hz 0

-4.00

-8.00

° 80.0

40.0 arg H (s) -11° 0

-40.0

-80.0

1 2 5 10 20 50 100 200 500 1k Design Example 1 – a Single-Stage PFC Given the low phase lag, a type 1 can be chosen

¾ Use the type 2 with fast lane removal where fp and fz are coincident dB 2 20.0 1

10.0 f = 19 Hz 13 c 0

15 V 0.5 Ω -10.0

-20.0 Ts( ) 5 V 10 ° 11 6.1 kΩ 10 kΩ 180 ton generation 20 kΩ 90.0 7 6 ϕm = 90° 0 586 nF 13.6 kΩ 395 nF 4 12 -90.0

5 -180 argTs( )

Gs( ) 1 2 5 10 20 50 100 200 500 1k Design Example 1 – a Single-Stage PFC A transient simulation helps to test the system stability

6.00

4.00 2.2 A 2.00

-2.00 ILED (t)

5.00 Vt 4.60 FB ( )

4.20

3.80

3.40

4.00

2.00

-2.00

-4.00 Iin (t)

20.0m 60.0m 100m 140m 180m Vin = 100 V rms Design Example 2: a DCM Flyback Converter

We want to stabilize a 20 W DCM adapter

Vin = 85 to 265 V rms, Vout = 12 V/1.7 A

Fsw = 65 kHz, Rpullup = 20 kΩ Optocoupler is SFH-615A, pole is at 6 kHz Cross over target is 1 kHz Selected controller: NCP1216

1. Obtain a power stage open-loop Bode plot, H(s) 2. Look for gain and phase values at cross over 3. Compensate gain and build phase at cross over, G(s) 4. Run a loop gain analysis to check for margins, T(s) 5. Test transient responses in various conditions Design Example 2: a DCM Flyback Converter Capture a SPICE schematic with an averaged model

839mV

389mV a vc

DC 6 X2x duty-cycle XFMR D1A RATIO = -166m mbr20200ctp vout 90.0V 12.0V PWM switch CM vout 2 34

Vin p -76.1V 12.6V 90 c AC = 0 0V R10 13 20m X9 Rload PWMCM L1 12.0V V(errP)/3 > 1 ? 1 7.2 L = Lp {Lp} 1 : V(errP)/3 C5 Fs = 65k 8 Ri = 0.7 3mF Se = Se B1 Voltage

Coming from FB

Look for the bias points values: Vout = 12 V, ok Design Example 2: a DCM Flyback Converter

Observe the open-loop Bode plot and select fc: 1 kHz dB ° Hs() 40.0 180

20.0 90.0 Phase at 1 kHz -70 ° 0 0

-20.0 -90.0 arg H (s)

Magnitude at 1 kHz -40.0 -180 -23 dB

10 100 1k 10k 100k Design Example 2: a DCM Flyback Converter

Apply k factor or other method, get fz and fp

¾ fz = 3.5 kHz fp = 4.5 kHz Vout(s)

Vdd 2kΩ 38kΩ

20kΩ

VFB(s) 10nF k factor FB gave

2.5nF CnF= 3.8 10kΩ

install CnFopto =1.3

CnnnF2 =−≈3.8 1.3 2.5 Design Example 2: a DCM Flyback Converter

Check loop gain and watch phase margin at fc 4 ° dB 180 80.0 Ts( )

90.0 40.0 argTs( )

ϕm = 60° 0 0

-90.0 -40.0 Crossover 1 kHz

-180 -80.0

10 100 1k 10k 100k Design Example 2: a DCM Flyback Converter Sweep ESR values and check margins again

12.04 Vout(t) Hi 12.00 line Excellent!

11.96

11.92 100 Low mV line

11.88 200 mA to 2 A in 1 A/µs 3.00m 9.00m 15.0m 21.0m 27.0m Use an Automated Design Tool To speed-up your design studies, use the right tool! 1. 2. Enter Show power calculated stage gain values and phase

3. 4.

Compute See final pole/zero values on check open TL431 loop gain

www.onsemi.com NCP1200, design tools Conclusion Classical loop control theory describes op amps in compensators Engineers cannot apply their knowledge to the TL431 Examples show that the TL431 with an optocoupler have limits Once these limits are understood, the TL431 is simple to use All three compensator types have been covered Design examples showed the power of averaged models Use them to extensively reproduce parameter dispersions Applying these recipes is key to design success!

Merci ! Thank you! Xiè-xie! For More Information

• View the extensive portfolio of power management products from ON Semiconductor at www.onsemi.com

• View reference designs, design notes, and other material supporting the design of highly efficient power supplies at www.onsemi.com/powersupplies