Differential AC Boosting Compensation for Power-Efficient
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Copyright © 2019 American Scientific Publishers Journal of All rights reserved Low Power Electronics Printed in the United States of America Vol. 15, 379–387, 2019 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Tayebeh Asiyabi1 and Jafar Torfifard2 ∗ 1Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran 2Department of Electrical Engineering, Izeh Branch, Islamic Azad University, Izeh, Iran (Received: 26 February 2019; Accepted: 22 July 2019) In this paper, a new architecture of four-stage CMOS operational transconductance amplifier (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The pre- sented structure removes feedforward and boosts feedback paths of compensation network simul- taneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and large- signal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65 phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 Wfrom1.8V. Keywords: Differential AC Boosting, Frequency Compensation, CMOS Operational IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 TransconductanceCopyright: Amplifier American (OTA), Scientific Low Power, Publishers Low Voltage. Delivered by Ingenta 1. INTRODUCTION is compulsory for high-precision purposes. Most recently Operational transconductance amplifiers (OTAs) are reported buffer amplifiers2–5 use a three-stage nested Miller widely used in analog and mixed-signal circuits. The per- compensated topology to get better linearity for a given fect circuit design is to demonstrate how can implement power consumption and silicon area as compared with the OTA with low-voltage low-power operation. Regard- a simple two-stage Miller structure.6 The use of either ing advanced CMOS technology and decreasing effective the nested Miller compensation (NMC) structure or the channel length, the MOSFET’s intrinsic gain is degraded reversed nested Miller compensation (RNMC) technique is while industrial tendency is to achieve higher frequency the common solution for implementing a multi-stage oper- and resolution. Therefore, inevitably the need of high ational amplifier. An amplifier based on the RNMC usu- gain and high speed OTAs is handled. As the channel ally includes a higher bandwidth in comparison with the length and supply voltage are further scaling down, the amplifier using NMC technique because the inner com- single-stage amplifiers based on cascoding transistors are pensation capacitor of the amplifier using the RNMC no longer possible since devices are vertically stacked. method does not have loading effect.7 This technique is Several circuit structures are presented as folded cascode well considered due to its simplicity of design and no and recycling folded cascode structures,1–3 which enhance extra power consumption. However, this frequency com- the DC gain and gain-bandwidth frequency (GBW). At pensation method adds a right half plane (RHP) zero this time, such structures are progressively abandoned to the transfer function of amplifier leading to stabil- because of voltage swing reduction. Therefore, multi- ity difficulties.8–10 To address this problem, many RNMC stage structures are more compatible with technology techniques have been presented to cancel out the RHP advancement and low-voltage operation. Instead, multi- zero such as the RNMC amplifier using voltage buffer stage amplifiers have come in to use for low-voltage cir- and nulling resistor,1–6 reversed active feedback frequency cuits. They will prevail especially when high DC gain compensation (RAFFC),11 RNMC techniques with cur- rent follower (CF) and the voltage follower (VF).12–14 The ∗Author to whom correspondence should be addressed. pole-zero cancellation of differential block frequency com- Email: [email protected] pensation (DBFC) technique15 removes non-dominant pole J. Low Power Electron. 2019, Vol. 15, No. 4 1546-1998/2019/15/379/009 doi:10.1166/jolpe.2019.1623 379 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Asiyabi and Torfifard with zero, which leads to significant frequency response a differential input, but the signal applied to its input is the improvements while the multipath nested Miller compen- difference between the input and the output of the third sation (MNMC) method, which adds a stage between the stage, which implies that this difference is substantially input and second stages, increases the bandwidth at the equal to the output signal of the third stage, at least for expense of higher circuit complexity and power dissipa- the whole frequency range over which the third stage has tion. The reversed NMC (RNMC) technique demonstrates enough gain (this range is deemed to be much wider than better frequency response thanks to its insensitivity to load the UGF of the OTA since the pole associated to its output capacitor of inner compensation loop resulting the inner is assumed to be located at a frequency much higher than loop is intrinsically stable. All the mentioned techniques the UGF of the OTA). as well as other approaches such as nested Gm capac- Where gmk is the transconductance of the kth gain stage 16 itance compensation (NGCC), damping factor-control while Rk and Ck are the resistance and capacitance respec- frequency compensation (DFCFC),17 active feedback fre- tively, attached to the node-k in the op-amps (k = 1, 2, 7 quency compensation (AFFC) and AC boosting compen- 3, 4) and CL is the capacitive load. Note that the capac- 18 sation (ACBC) try to enhance the frequency response itance C1, C2, C3 and C4 represent the stray capacitance trough using feedback and feed forward paths. Since pas- to ground at those nodes which can be neglected. To sive elements are huge and have more concerns com- take their effect on the frequency response, the expression pared to active parts through the fabrication.19 Therefore, (1) should be guaranteed, which sets the lower bound to performing frequency compensation technique with less compensation capacitance (Cc). Here, the 1/Rk Ck is the complexity and silicon area is a critical requirement for angular frequency of the internal poles whereas the GBW implementing high performance and power-efficient multi- is gm1/Cc (where gm1 is the transconductance of the first stage op-amps. To achieve the higher power efficiency of stage). 1 frequency compensation scheme, the basic idea of the pro- > GBW (1) posed design is to use neither the nested Miller compen- RkCk sation architecture nor the reversed nested Miller method. As a result, the lower bond of the Cc is given by (2). Instead, the only one feedforward stage and one sepa- Cc rate Miller compensation are constructed. The main reason >gm1Rk (2) of the tendency to design circuit with small capacitors is Ck IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 the ability of easy integration with the absence of passive In practice, the Cc/Ck should be larger than gm1Rk by Copyright:14 American Scientific Publishers elements which reduces the die area. In thisDelivered paper, a bymore Ingenta than one order of magnitude as shown in (2), which new compensation technique is introduced named the dif- sets a lower bound to Cc that is normally high (this is a ferential AC boosting compensation (DACBC) where the similar problem to the encountered in three-stage ampli- feedforward path is eliminated to enhance the frequency fiers). Regarding to the proposed structure in Figure 1 and response. As will be shown, the design equations set the applying nodal analysis, (3) to (10) can be obtained. It is values of compensation network elements for the desired assumed Cc, CL Ck and gmkRk 1, the transfer func- phase margin and gain-bandwidth product. The paper is tion is given as follows. Note that the expression (3) is − organized as follows. The detailed analysis of proposed provided from the negative input (vi ) to the output (Vout). technique is presented in Section 2. The completed design a s2 + a s + a procedure of four-stage differential amplifier is described A = 2 1 0 (3) v 4 + 3 + 2 + + in Section 3. The simulation results of proposed topology b4s b3s b2s b1s 1 are shown in Section 4. At last, the conclusions are given Where in Section 5. = a2 C2CC gm1R1R2R4 (4) = 2. THE PROPOSED TECHNIQUE a1 CC gm1R1R4 (5) DESCRIPTION a = g g g g R R R R (6) Figure 1 shows the schematic of four-stage OTA based 0 m1 m2 m3 m4 1 2 3 4 on the DACBC frequency compensation technique. This And configuration uses a differential feedback stage for two = purposes. Initially, the differential feedback stage forms a b4 C1C2C3CLR1R2R3R4 (7) compensation network and then the output signal is driven b = C C C R R R (8) from this stage so that a higher DC gain can be achieved. 3 2 C L 1 2 4 = These two issues make the proposed method very effective b2 CC CLR1R4 (9) regarding frequency response. The signs of stages have to = b1 CC gm2gm3gm4R1R2R3R4 (10) be considered as shown in Figure 1 to get Miller effect essentially while the compensation capacitor is located in Since the parasitic poles (i.e., the poles associated to the negative loop configuration. Actually, the fourth stage has outputs of the second and the third stage) are located 380 J. Low Power Electron. 15, 379–387, 2019 Asiyabi and Torfifard Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Fig.