Differential AC Boosting Compensation for Power-Efficient

Differential AC Boosting Compensation for Power-Efﬁcient Multistage Ampliﬁers

Tayebeh Asiyabi1 and Jafar Torﬁfard2 ∗

1Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran 2Department of Electrical Engineering, Izeh Branch, Islamic Azad University, Izeh, Iran

(Received: 26 February 2019; Accepted: 22 July 2019)

In this paper, a new architecture of four-stage CMOS operational transconductance ampliﬁer (OTA) based on an alternative differential AC boosting compensation called DACBC is proposed. The presented structure removes feedforward and boosts feedback paths of compensation network simul- taneously. Moreover, the presented circuit uses a fairly small compensation capacitor in the order of 1 pF, which makes the circuit very compact regarding enhanced several small-signal and large- signal characteristics. The proposed circuit along with several state-of-the-art schemes from the literature have been extensively analysed and compared together. The simulation results show with the same capacitive load and power dissipation the unity-gain frequency (UGF) can be improved over 60 times than conventional nested Miller compensation. The results of the presented OTA with 15 pF capacitive load demonstrated 65 phase margin, 18.88 MHz as UGF and DC gain of 115 dB with power dissipation of 462 Wfrom1.8V. Keywords: Differential AC Boosting, Frequency Compensation, CMOS Operational IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 TransconductanceCopyright: Ampliﬁer American (OTA), Scientific Low Power, Publishers Low Voltage. Delivered by Ingenta

1. INTRODUCTION is compulsory for high-precision purposes. Most recently Operational transconductance amplifiers (OTAs) are reported buffer amplifiers2–5 use a three-stage nested Miller widely used in analog and mixed-signal circuits. The per- compensated topology to get better linearity for a given fect circuit design is to demonstrate how can implement power consumption and silicon area as compared with the OTA with low-voltage low-power operation. Regard- a simple two-stage Miller structure.6 The use of either ing advanced CMOS technology and decreasing effective the nested Miller compensation (NMC) structure or the channel length, the MOSFET’s intrinsic gain is degraded reversed nested Miller compensation (RNMC) technique is while industrial tendency is to achieve higher frequency the common solution for implementing a multi-stage oper- and resolution. Therefore, inevitably the need of high ational amplifier. An amplifier based on the RNMC usu- gain and high speed OTAs is handled. As the channel ally includes a higher bandwidth in comparison with the length and supply voltage are further scaling down, the amplifier using NMC technique because the inner com- single-stage amplifiers based on cascoding transistors are pensation capacitor of the amplifier using the RNMC no longer possible since devices are vertically stacked. method does not have loading effect.7 This technique is Several circuit structures are presented as folded cascode well considered due to its simplicity of design and no and recycling folded cascode structures,1–3 which enhance extra power consumption. However, this frequency com- the DC gain and gain-bandwidth frequency (GBW). At pensation method adds a right half plane (RHP) zero this time, such structures are progressively abandoned to the transfer function of amplifier leading to stabil- because of voltage swing reduction. Therefore, multi- ity difficulties.8–10 To address this problem, many RNMC stage structures are more compatible with technology techniques have been presented to cancel out the RHP advancement and low-voltage operation. Instead, multi- zero such as the RNMC amplifier using voltage buffer stage amplifiers have come in to use for low-voltage cir- and nulling resistor,1–6 reversed active feedback frequency cuits. They will prevail especially when high DC gain compensation (RAFFC),11 RNMC techniques with current follower (CF) and the voltage follower (VF).12–14 The ∗Author to whom correspondence should be addressed. pole-zero cancellation of differential block frequency com- Email: [email protected] pensation (DBFC) technique15 removes non-dominant pole

J. Low Power Electron. 2019, Vol. 15, No. 4 1546-1998/2019/15/379/009 doi:10.1166/jolpe.2019.1623 379 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Asiyabi and Torfifard with zero, which leads to significant frequency response a differential input, but the signal applied to its input is the improvements while the multipath nested Miller compen- difference between the input and the output of the third sation (MNMC) method, which adds a stage between the stage, which implies that this difference is substantially input and second stages, increases the bandwidth at the equal to the output signal of the third stage, at least for expense of higher circuit complexity and power dissipa- the whole frequency range over which the third stage has tion. The reversed NMC (RNMC) technique demonstrates enough gain (this range is deemed to be much wider than better frequency response thanks to its insensitivity to load the UGF of the OTA since the pole associated to its output capacitor of inner compensation loop resulting the inner is assumed to be located at a frequency much higher than loop is intrinsically stable. All the mentioned techniques the UGF of the OTA). as well as other approaches such as nested Gm capac- Where gmk is the transconductance of the kth gain stage 16 itance compensation (NGCC), damping factor-control while Rk and Ck are the resistance and capacitance respec- frequency compensation (DFCFC),17 active feedback fre- tively, attached to the node-k in the op-amps (k = 1, 2, 7 quency compensation (AFFC) and AC boosting compen- 3, 4) and CL is the capacitive load. Note that the capac- 18 sation (ACBC) try to enhance the frequency response itance C1, C2, C3 and C4 represent the stray capacitance trough using feedback and feed forward paths. Since pas- to ground at those nodes which can be neglected. To sive elements are huge and have more concerns com- take their effect on the frequency response, the expression pared to active parts through the fabrication.19 Therefore, (1) should be guaranteed, which sets the lower bound to performing frequency compensation technique with less compensation capacitance (Cc). Here, the 1/Rk Ck is the complexity and silicon area is a critical requirement for angular frequency of the internal poles whereas the GBW implementing high performance and power-efficient multi- is gm1/Cc (where gm1 is the transconductance of the first stage op-amps. To achieve the higher power efficiency of stage). 1 frequency compensation scheme, the basic idea of the pro- > GBW (1) posed design is to use neither the nested Miller compen- RkCk sation architecture nor the reversed nested Miller method. As a result, the lower bond of the Cc is given by (2). Instead, the only one feedforward stage and one sepa- Cc rate Miller compensation are constructed. The main reason >gm1Rk (2) of the tendency to design circuit with small capacitors is Ck IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 the ability of easy integration with the absence of passive In practice, the Cc/Ck should be larger than gm1Rk by Copyright:14 American Scientific Publishers elements which reduces the die area. In thisDelivered paper, a bymore Ingenta than one order of magnitude as shown in (2), which new compensation technique is introduced named the dif- sets a lower bound to Cc that is normally high (this is a ferential AC boosting compensation (DACBC) where the similar problem to the encountered in three-stage ampli- feedforward path is eliminated to enhance the frequency fiers). Regarding to the proposed structure in Figure 1 and response. As will be shown, the design equations set the applying nodal analysis, (3) to (10) can be obtained. It is values of compensation network elements for the desired assumed Cc, CL Ck and gmkRk 1, the transfer func- phase margin and gain-bandwidth product. The paper is tion is given as follows. Note that the expression (3) is − organized as follows. The detailed analysis of proposed provided from the negative input (vi ) to the output (Vout). technique is presented in Section 2. The completed design a s2 + a s + a procedure of four-stage differential amplifier is described A = 2 1 0 (3) v 4 + 3 + 2 + + in Section 3. The simulation results of proposed topology b4s b3s b2s b1s 1 are shown in Section 4. At last, the conclusions are given Where in Section 5. = a2 C2CC gm1R1R2R4 (4) = 2. THE PROPOSED TECHNIQUE a1 CC gm1R1R4 (5) DESCRIPTION a = g g g g R R R R (6) Figure 1 shows the schematic of four-stage OTA based 0 m1 m2 m3 m4 1 2 3 4 on the DACBC frequency compensation technique. This And configuration uses a differential feedback stage for two = purposes. Initially, the differential feedback stage forms a b4 C1C2C3CLR1R2R3R4 (7) compensation network and then the output signal is driven b = C C C R R R (8) from this stage so that a higher DC gain can be achieved. 3 2 C L 1 2 4 = These two issues make the proposed method very effective b2 CC CLR1R4 (9) regarding frequency response. The signs of stages have to = b1 CC gm2gm3gm4R1R2R3R4 (10) be considered as shown in Figure 1 to get Miller effect essentially while the compensation capacitor is located in Since the parasitic poles (i.e., the poles associated to the negative loop configuration. Actually, the fourth stage has outputs of the second and the third stage) are located

380 J. Low Power Electron. 15, 379–387, 2019 Asiyabi and Torfifard Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

Fig. 1. The schematic of OTA based on the DACBC technique. at a high frequency, the resulting small-signal transfer connected between the outputs of the first and the fourth function of the DACBC op-amp has a single dominant stages. pole response with 65 phase margin, and a close first The compensation capacitance (Cc)setsupthetwo order transient settling. Indeed, the second and third poles loops. The circuit uses positive feedback with capacitance get moved further away from dominant pole by factor of Cc around the second-stage and fourth-stage (gm2gm4+) roughly Cc/Ck. Hence, pole splitting can be achieved with introducing a left-half plane zero in order to cancel out a lower value of the compensation capacitor Cc and with one of the non-dominant poles. In this work, the pole- lower values of gm2 and gm3. This results in a significantly zero cancelation is done with this LHP zero and the pole larger unity gain frequency attainable by the op-amp, with of the fourth-stage. The circuit also uses negative feed- lower power dissipation and more compact layout, when back Cc and gm2gm3gm4− loop. The circuit dynamics can compared to the Miller compensated op-amps as evident be achieved as follows. from relation (2). g GBW = m1 (11) C IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 C 3. NEW OPERATIONAL g Copyright: American Scientific Publishers P = m2 (12) TRANSCONDUCTANCE AMPLIFIERDelivered by Ingenta 2 C CIRCUIT DESIGN 2 g Figure 2 shows the transistor level of the proposed cir- P = m3 (13) 3 C cuit. The input differential stage includes M –M tran- 3 1 5 g sistors with the active load of M /M while the second = m4 3 4 P4 (14) stage is an inverting gain stage involves a common source CL amplifier of M . The third stage of M is similar to the 6 8 = 1 previous one. The last stage is a fully differential amplifier, Z (15) r4CC which consists of devices M10 to M14 and the quiescent current level at the output stage controlled by the common- Here, GBW is the gain-bandwidth product frequency while mode feedback circuit (CMFB) of RC1 and RC2 shown P2 and P3 are high-frequency parasitic poles originate from in Figure 2. The CC is the compensation capacitance low-impedance nodes 2 and 3, respectively. Additionally,

Vdd M7 M3 M4 Vb2 M9 M13 M14

RC1 RC2

- + CC Vo Vo rf rf Vi+ Vi - M1 M2 CL CL M gm1 11 gm4 M12 M6 gm2 gm3 Vb1 M5 M8 Vb4 M10 C2 C3 Vss First Stage Second Stage Third Stage Differential Amp

Fig. 2. The completed proposed OTA.

J. Low Power Electron. 15, 379–387, 2019 381 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Asiyabi and Torfifard

P4 is the non-dominant pole, which is cancelled out with the first non-dominant pole is larger than the dominant LHP zero (Z). The resulting cancellation leaves the op- pole. Considering the frequency axis, the second pole must amp with a one-pole response. Thus the Miller capaci- be ten times larger than GBW to reach sufficient PM in the tance (Cc) can be conceded by (16). order of 90 . Under these conditions, the feedback stage transconductance (g ) is given by (24). C m4 = L Cc (16) 10C g gm4r4 ≥ L m1 gm4 (24) gm2gm3r2r3CC Additionally, the fourth pole P4 usually determines the phase margin. Here, the fourth pole is related to the load It should be noted that the PM of 90 guarantees a high capacitor and output impedance. This pole fortunately can stability margin of OTA at the expense of lower bandwidth. be cancelled by the first zero. This pole-zero cancellation Therefore, the gm4 must be taken so that the reasonable improves the frequency response considerably. The open speed and stability can be achieved. By choosing the PM loop gain (Adc)oftheOTAisgm1gm2gm3gm4r1r2r3r4 and of 63 , the new gm4 can be calculated in (25). thus the dominant pole (P1) is obtained in (17). 2C g g ≥ L m1 (25) m4 g g r r C = = 1 m2 m3 2 3 C P1 d (17) CC gm2gm3gm4r1r2r3r4 4. SIMULATION RESULTS From Figure 2, gmi and ri are the transconductance and The proposed approach is simulated in a 0.18-m n-well output resistance of the ith stage, respectively. The rdsm denotes to the drain-to-source resistance correspond to the CMOS technology using Hspice with a capacitive load of 15 pF at room temperature of 27 C. The circuit consumes mth transistor indicated in (16) while the C2 and C3 are the parasitic capacitances. only 462 W from a supply voltage of 1.8 V while the quiescent current of M5 is 10 A. The most important factors = r1 rds2 rds4 (18) to implement an amplifier is the feedback performance. The closed-loop pole-zero configuration in the S plane is = r2 rds6 rds7 (19) shown in Figure 3. According to this result, the stability = r3 rds8 rdsIP:9 192.168.39.210 (20)On: Sun,of 03 proposed Oct 2021 OTA 15:57:22 can be verified since the j axis is not crossed by poles. Moreover, the zero location is constant = Copyright: American Scientific Publishers r4 rds12 rds14 rf Delivered(21) byand Ingenta independent of feedback gain, which is predictable. The slew rate (SR) is the most important parameter The closed-loop transfer function for this amplifier is spec- showing the drive capability of OTA. When designing an ified by (22). According to the Routh–Hurwitz criterion, amplifier, it is important to enhance the SR as much as the first column coefficients are similar in sign verifying the GBW. Since the output stage operates in class AB, the stability of amplifier in any condition. then it doesn’t limit the slew rate. As a result, the slew A = g g g g r r r r + C g r r S rate will directly be determined the DC current of the first CL m1 m2 m3 m4 1 2 3 4 C m1 1 4 stage and compensating capacitance Cc asshownin(26) 2 + /CC CLr1r4S CC gm2gm3gm4r1r2r3r4S in which I is the maximum current entering or leaving Cc + g g g g r r r r (22) Cc in the case of only one of the differential input transis- m1 m2 m3 m4 1 2 3 4 tors is turned on through large differential signal applied Hence, the GBW can be calculated in (23). to the first stage with respect to the matching issue. g g g g r r r r g I = × = m1 m2 m3 m4 1 2 3 4 = m1 Cc max GBW Adc d (23) SR = (26) CC gm2gm3gm4r1r2r3r4 CC Cc Equation (23) demonstrates that the GBW is the ratio The OTA step response in the unity gain configuration in of the first stage transconductance to the compensation the case of PM = 65 is shown in Figure 4. The result capacitor, which is a general result whatever the com- associated with the phase margin (PM) in the transient pensation technique. There are two ways to reach higher response is connected with the settling time. Since the

GBW by means of increasing the transconductance of gm1, PM increases, the op-amp needs a shorter time to settle. which leads to consume more power and the second way As mentioned previously, the stability of the closed-loop is to choose smaller compensation capacitor. The latter configuration can be verified the Routh–Hurwitz criteria. is appropriate since it reduces the die area with no extra The settling time can be extracted from the step response power dissipation. Regarding to the PM, the range of com- which is mostly dependent on the dominant pole. The 99% pensation capacitor values is limited by compensation net- transient settling time (ts) for a 1000 mV step is met to work structure. The significant parameter of the proposed be approximately 0.02 sec improved using the DACBC technique is the Phase Margin, which is equal to 65 since technique.

382 J. Low Power Electron. 15, 379–387, 2019 Asiyabi and Torfifard Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

Fig. 3. Root-Locus plot of compensated ampliﬁer.

Figure 5 shows the phase margin and unity-gain fre- load capacitor decreases the non-dominant pole sacriﬁcing quency versus load capacitor in the range of 15 pF to the frequency response.

25 pF. The results illustrate when the capacitive load is The phase margin and unity-gain frequency versus gm4 15 pF, the PM becomes more than 60 indicating the are presented in Figure 6. The transconductance of the last design is fairly compatible with large capacitive loads. stage, gm4, deserves some additional comment. Figure 6 Indeed, the Eq. (12) clearly implies that the increase in results from the presence of any mismatch in the circuit,

IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 Copyright: American Scientific Publishers Delivered by Ingenta

= Fig. 4. The step response of the OTA with CL 15 pF.

Fig. 5. Phase margin and unity-gain frequency versus load capacitor.

J. Low Power Electron. 15, 379–387, 2019 383 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Asiyabi and Torfifard

Fig. 6. Phase margin and unity-gain frequency versus gm4.

IP: 192.168.39.210 On: Sun, 03 Oct 2021 15:57:22 Copyright: American Scientific Publishers = Fig. 7. PM and GBW versus compensation capacitor (Cc) withDeliveredCL 15 pF.by Ingenta

which causes to change several electrical characteristics versa, i.e., by considering absolute value of gm4 with of the OTA especially varying in gm4, which strongly respect to expression (24). Based on these results, the determines the frequency response. At this point, we are proposed circuit can reach appropriate phase margin and only concerned with the transconductance of the last stage unity-gain frequency regarding smaller values of the gm4. (gm4). For larger values of gm4, the response frequency Figure 7 demonstrate the phase margin and unity- enhances (increasing both the GBW and PM) and vice gain frequency variations versus compensation capacitor

100

50 0

-50 Gain (dB) -100 8 100 101 102 103 104 105 106 107 10 109 180 135 90

45 Phase (deg) Phase 0 100 101 102 103 104 105 106 107 108 109 Frequency (Hz)

Fig. 8. The corner analysis.

384 J. Low Power Electron. 15, 379–387, 2019 Asiyabi and Torfifard Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

Fig. 9. Mont Carlo simulation with capacitive load of 15 pF.

Table I. Dimensions of the transistors. important parameters such as DC gain, PM and GBW. Transistor W (m) L (m) Additionally, the results show that due to perfect pole- zero cancellation the presented design is much more robust M /M 21 1 2 against undesired compensation capacitor deviations such M /M 81 3 4 as thermal effects and fabrication mismatches. The results M5 41 M6 3.5 1 show that the presented circuit is capable to operate with M7 52 1 an open-loop gain of 115 dB, the PM of 65 and the GBW M8 3.7 1 M 52 1 of 18.8 MHz. Therefore, the GBW is enhanced by a factor 9 of 60 times using DACBC solution when compared to the M10 2.8 1 M11/M12 0.25 1 conventional NMC method in same power dissipation and M13/M14 81capacitive load. IP: 192.168.39.210 On: Sun, 03Additionally, Oct 2021 15:57:22 the Monte Carlo simulation is performed Copyright: American Scientific Publishers Table II. The performance of proposed design with C = 15 pf. L Delivered byon Ingenta the proposed circuit shown in Figure 9. All circuit parameters have a uniform distribution that put on Parameter Value the circuit in harder situation than Gaussian distribution. Power dissipation (W) 462 According to these results, the circuit is robust regarding Slew rate (V/S) 12.5 DC gain (dB) 115 undesired process variations and fabrication mismatches. GBW product (MHz) 18.8 To successfully compare the presented DACBC PM ()65approach with those obtained by different frequency com- CMRR (dB) 107.2 PSRR (dB) 73.6 pensation techniques, the following two deﬁnitions of Settling time (s)@(1 V) 0.2 ﬁgure of merit factors (FOMs) are used showing the performance of the design [20–23]. showing the robustness of the proposed circuit. The pre- × P · M MHz · deg FOM = GBW (27) sented circuit is able to operate with the fairly small com- BW Power mW pensation capacitor reducing the silicon area considerably. × C The corners simulation of the op-amp is performed in = SR L V · pF FOMSR (28) Figure 8, which involves the worst and best states of Power S mW

Table III. The performance OTAs.

Technology CMOS Voltage DC gain Load Power UGF CC Slew rate PM (m) (V) (dB) (pF) (W) (MHz) (pF) (V/S) ( )FOMs FOML

RNMC [8] 0.18 1.8 100 100 325 4.75 5 1.2 63.3 0.92 0.38 DFPFC [9] 0.18 1.8 >100 100 544 9.08 2 2.23 83 1.1 0.41 RNMC [10] 0.18 1.8 >100 100 360 6.66 4 1.12 90 1.66 0.31 NMC [13] 0.18 1.8 100 100 345 0.22 110 0.25 68.3 0.06 0.07 DBFC [15] 0.18 1.8 >100 100 380 6.66 6 0.9 86 1.51 0.23 AFFC [16] 0.8 1.2 >100 100 424 2.60 15 1.2 70.4 0.61 0.43 DCCII [20] 0.18 1.8 >100 100 310 9.63 3.9 – 85 1.11 0.33 NGCC [21] 0.18 1.2 >100 100 365 0.25 9.6 0.33 69.1 0.06 0.09 This work 0.18 1.8 115 15 462 18.8 0.78 12.5 65 2.66 0.6

J. Low Power Electron. 15, 379–387, 2019 385 Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers Asiyabi and Torfifard

The FOMBW and FOMSR indicate how enhanced are the 8. S. Biabanifard, S. M. Largani, M. Akbari, S. Asadi, and M. C. E. small-signal and large-signal characteristics, respectively. Yagoub, High performance reversed nested Miller frequency com- Because of the lack of compensation capacitors effect on pensation. Analog Integrated Circuits and Signal Processing 85, 223 (2015). FOMs mentioned previously, a new FOM can be defined 9. H. Largani, S. Mehdi, S. Shahsavari, S. Biabanifard, and A. Jalali, to consider the effect of compensation capacitor value. A new frequency compensation technique for three stages OTA Although the components’ circuit in this design have been by differential feedback path. International Journal of Numeri- biased in the moderate and strong inversion regions, the cal Modelling: Electronic Networks, Devices and Fields 28, 381 circuit can be biased in deep weak inversion region in (2014). order to reduce power dissipation making the circuit much 10. S. Biabanifard, S. M. Largani, A. Biamanifard, M. Biabanifard, M. Hemmati, and Z. Khanmohammadi, Three stages CMOS opera- suitable for very low power applications. Furthermore, the tional amplifier frequency compensation using single Miller capac- transistor dimensions are given in Table I. itor and differential feedback path. Analog Integrated Circuits and The circuit simulation results of OTA are summarized Signal Processing 97, 195 (2018). in Table II. 11. A. D. Grasso, G. Palumbo, and S. Pennisi, Improved reversed nested The results comparison are reported in Table III. The Miller frequency compensation technique with voltage buffer and resistor. IEEE Trans. Circuits and Systems II: Express Briefs 54, 382 results show several improvements regarding the dynamic (2007). range characteristics as well as power reduction by means 12. A. Walter, G. Palumbo, and S. Pennisi, Design methodology of of the DACBC technique. Miller frequency compensation with current buffer/amplifier. IET Circuits, Devices and Systems 2, 227 (2008). 13. S. Shahsavari, S. Biabanifard, S. M. Hosseini Largani, and 5. CONCLUSION O. Hashemipour, A new frequency compensation method based on A new differential AC boosting compensation (DACBC) differential current conveyor, 2014 22nd Iranian Conference on Elec- trical Engineering (ICEE), IEEE (2014). for low-power multistage amplifiers has been presented. 14. F. Zu, S. Yan, J. Hu, and E. Sanchez-Sinencio, Feedforward reversed The existing structure removes feedforward and boosts nested Miller compensation techniques for three-stage amplifiers, feedback paths of the compensation network accordantly. IEEE Int. Symp. on Circuits and Systems,Kobe,Japan(2005),Vol.1, The proposed circuit uses a fairly small compensation pp. 2575–2578. capacitor, which makes the OTA very compact. Addi- 15. T. Asiyabi and J. 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386 J. Low Power Electron. 15, 379–387, 2019 Asiyabi and Torfifard Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers

Tayebeh Asiyabi Tayebeh Asiyabi received the B.S. degree in in Electrical Engineering in 2007 from Shariaty University, Tehran, Iran and M.S. degree in Electrical Engineering in 2012 from IAU, Kermanshah Branch, Kermanshah, Iran. She is currently pursuing the Ph.D. degree in Electrical Engineering at IAU, Mahshahr Branch, Iran. Her research interests include design of various low voltage low power analog and RF blocks, data converter and analog and mixed-signal processing. Jafar Torﬁfard Jafar Torﬁfard received M.S. and Ph.D. degrees in Electrical Engineering from the IAU and University Technology of Malaysia in 2004 and 2013, respectively. Presently, he is an Associate Professor with the IAU, Izeh Branch. His research interests comprise low- voltage low-power analog and mixed-mode integrated circuits, integrated sensor interfaces, analog and digital signal processing and communication systems.

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