Switch-mode power converter compensation made easy

Robert Sheehan Systems Manager, Power Design Services Member Group Technical Staff Louis Diana Field Application, America Sales and Marketing Senior Member Technical Staff Texas Instruments Using this paper as a quick look-up reference can help designers compensate the most popular switch-mode power converter topologies.

Engineers have been designing switch-mode power converters for some time now. If you’re new to the design field or you don’t compensate converters all the time, compensation requires some research to do correctly. This paper will break the procedure down into a step-by-step process that you can follow to compensate a power converter.

We will explain the theory of compensation and why it is necessary, examine various power stages, and show how to determine where to place the poles and zeros of the compensation network to compensate a power converter. We will examine typical error amplifiers as well as transconductance amplifiers to see how each affects the control loop and work through a number of topologies/examples so that power engineers have a quick reference when they need to compensate a power converter.

Introduction Many SMPS designers would appreciate a how- A switch-mode power supply (SMPS) regulates to reference paper that they can use to look up the output voltage against any changes in compensation solutions to various topologies with output loading or input line voltage. An SMPS various feedback modes. We are striving to provide accomplishes this regulation with a feedback loop, this in a single paper. which requires compensation if it has an error Control-loop and compensation amplifier with linear feedback. This paper covers definitions the necessary definitions and theory required to As stated previously, a SMPS’s primary function understand how a linear feedback loop works. is to regulate its output against input/output We will define poles and zeros and power-stage variations and transients, which requires a feedback characteristics, along with various error amplifiers;Figure 1 loop. Figure 1 shows a typical SMPS with a discuss isolated feedback and optocouplers; and feedback loop. give examples of how to compensate various buck, boost and buck-boost topologies. We will cover voltage-mode control and current-mode control methods. Unless otherwise noted, equations and graphs depict fixed-frequency, continuous- conduction-mode (CCM) operation. We will define discontinuous-conduction-mode (DCM) versus CCM, and how each affects the feedback loop. This paper also includes a section on the practical limits of devices used in SMPSs. Figure 1. A test signal injected into the feedback of the control loop measures the frequency response.

Texas Instruments 2 September 2016 Figure 2

Figure 1 contains a power stage and an error amplifier. The power stage contains all of the magnetics and power switches, as well as a IOUT pulse-width modulated (PWM) controller. The error amplifier provides the feedback mechanism and compensation. A voltage divider connected to the VOUT output provides a sample Figureof the output voltage, 3 which is compared to a reference voltage by the error amplifier. The error voltage coming out of the error amplifier drives the PWM duty cycle higher if Figure 2:.Poor transient response characterized by underdamped the output voltage is low, or drives the PWM duty ringing of the output voltage when stepping the load current. cycle lower if the output voltage is high. Thus, the feedback scheme used here is negative feedback. Loop gain is the gain around the feedback loop, comprising the product of error-amplifier gain, IOUT modulator gain and power-stage gain. The feedback loop’s gain and phase response versus frequency will determine how well the SMPS will function. VOUT The bandwidth of the control loop determines its speed in responding to a transient condition. Compensation adjusts the loop bandwidth and tailors the frequency response. Increasing the loop Figure 3. Good transient response exhibits no ringing with a critically bandwidth increases the speed at which the SMPS damped characteristic. reacts to a transient. Therefore, maximizing the crossover frequency will produce a quicker transient Phase and gain-margin definitions response. Phase and gain margin are parameters used to Phase margin, which we discuss in the next section, identify the health of a feedback loop. A control loop also plays an important role in compensation. is unstable if the loop has unity gain when the phase Figure 2 shows the results of low phase margin. In passes through zero. Gain margin is the gain value this case there is ringing after the load transient and when the phase passes through 0 degrees. This is measured in decibels and should be a negative the loop is underdamped. This is not a desirable number. Phase margin is the value of the phase response. measured in degrees when the gain passes through In Figure 3, the phase margin has increased; zero. This is measured in degrees and should be a therefore, the waveform does not show any ringing positive number (Figure 4). after the load transient. This response is well damped.

Texas Instruments 3 September 2016 Figure 4 Figure 5

Control Loop – Frequency Response 20 45 60 135

40 90 0 0

20 Phase 45 -20 -45 margin

0 0 (°) Phase Phase (°) Phase

Gain margin (dB) Magnitude -40 -90

Magnitude (dB) Magnitude -20 -45

-40 -90 -60 -135 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 Frequency (kHz) Frequency (kHz)

Figure 4. Phase margin is the difference in degrees when the gain Figure 5. The Bode plot of a pole shows the gain decreasing by –20 crosses zero. Gain margin is the difference in decibels when the phase dB/decade, with a phase shift at higher frequencies of –90 degrees. crosses zero. Equation 2 defines a zero where s is in the numerator. At the frequency of the zero the gain is Sufficient phase margin is required to prevent 3 dB up and increasing at a +20 dB/decade slope. oscillations. A phase margin of 45 degrees or The phase starts to increase one decade before greater is the design goal. A gain margin of –6 dB is the zero frequency, is 45 degrees up at the zero the minimum, while –10 dB is considered good. frequency, and continues to increase another 45 Although higher crossovers areFigure generally preferable, 6 degrees for one more decade. The total change is there are practical limitations. The rule of thumb 90 degrees over two decades (Figure 6). is one-fifth to one-tenth the switching frequency. s Attenuation at the switching frequency is also 1+ ωZ (2) important for noise immunity to minimize jitter. The H(s) = 1 gain should ideally pass through zero with a slope

of –20 dB/decade. This will maximize gain margin and will also negate the chance of the gain turning 60 135 positive at a higher frequency where the phase may be going through zero. If that happens, you could 40 90 have an unstable control loop. 20 45

Poles and zeros definitions (°) Phase

Magnitude (dB) Magnitude 0 0 Equation 1 defines a pole where s is in the denominator. At the frequency of the pole the gain -20 -45 0.01 0.1 1 10 100 1000 is –3 dB down and rolling off at a –20 dB/decade Frequency (kHz) slope. The phase starts to decrease one decade Figure 6. The Bode plot of a zero shows the gain increasing by +20 before the pole frequency, is 45 degrees down at the dB/decade, with a phase shift at higher frequencies of +90 degrees. pole frequency, and continues to decrease another 45 degrees for one more decade. The total change Figure 7 shows an inverted zero often used with a is –90 degrees over two decades (Figure 5). low-frequency pole when using the mid-band gain as the reference gain, defined by Equation 3. The 1 H (s) = s (1) inverted zero still has s in the numerator, but s and 1+ ωP are swapped.

ω

Texas Instruments 4 September 2016 Figure 7

ω As mentioned in the introduction, we will discuss 1+ Z H(s) = s (3) two types of loop control methods: voltage-mode 1 control and current-mode control. The control

method determines the characteristics of the of the 60 45 power stage. For example, in a voltage-mode buck converter the inductor-capacitor (LC) filter exhibits 40 0 a complex conjugate pole at the LC resonant

20 -45 frequency. This means that there are two poles at

Phase (°) Phase the same frequency, and the gain changes –40 dB/

Magnitude (dB) Magnitude 0 -90 decade with an associated phase change of –180 degrees. A current-mode buck converter does not -20 -135 0.01 0.1 1 10 100 1000 have a complex pole at the LC resonant frequency. Frequency (kHz) Equation 5 shows the transfer function of a complex conjugate pole with a quality factor, Q, associated Figure 7. The Bode plot of an inverted zero shows the gain going up and to the left of the reference gain, shown here as 0 dB. This cancels with the LC filter. Q is a measure of the sensitivity a pole at some lower frequency so that the phase changes from –90 or quality of the tuned circuit. A higher Q value degrees to 0 degrees. corresponds to a narrower bandwidth of the tuned circuit. A high Q value is not so good for a power- A right-half-plane zero is characteristic of boost and supply output filter, however, because as Q increases buck-boost power stages. The magnitude increases the phase slope increases. This means that the at 20 dB/decade with an associated phase lag phase changes much more quickly over a small band of –90 degrees. As you can see in Equation 4, s of frequencies, whereas two regular poles would is in the numerator, but it is negative. This makes Figure 8 change with a more gradual slope over two decades. compensating the converter more difficult Figure( 8). 1 s H(s) = 2 1− s s (5) 1+ + 2 ωZ (4) H(s) = QO ⋅ωO ωO 1 Figure 9 Figure 9 illustrates how phase slope increases as

Q increases. Since a high Q LC filter can cause a 60 45 –180 degree phase shift in the loop Bode plot, it

40 0 is important to understand the Q of the LC filter in order to compensate for this phase change. 20 -45

Phase (°) Phase 20 45

Magnitude (dB) Magnitude 0 -90 Gain 0 0 -20 -135 Q = 2 0.01 0.1 1 10 100 1000 -20 Q = 1 -45 Q = 0.5 Frequency (kHz) -40 -90

Q = 0.25 (°) Phase

Figure 8. The Bode plot of a right-half-plane zero shows the gain (dB) Magnitude -60 -135 increasing by +20 dB/decade, with a phase shift at higher frequencies Phase of –90 degrees. -80 -180 0.01 0.1 1 10 100 1000

Frequency (kHz)

Figure 9. The Bode plot of a complex conjugate pole shows the gain decreasing by –40 dB/decade, with a phase shift at higher frequencies of –180 degrees.

Texas Instruments 5 September 2016 Equivalent series resistance zero converter with its associated input/output voltage The equivalent series resistance (ESR) zero is transfer function. As you can see in Equation 7, the output voltage is related to the input voltage associated with output capacitance. FigureAlthough 11all capacitors exhibit ESR, ceramic capacitors have multiplied by the on-time duty cycle, D. very low ESR – in the order of 3-5 mΩ. Electrolytic- (7) type capacitors have higher ESR – in the order VOUT =VIN ⋅ D of 10-20 mΩ for an aluminum polymer and up to hundreds of mΩ for regular electrolytic capacitors. The ESR in an output capacitor determines the frequency at which the ESR zero occurs; see the numerator in Equation 6. Figure 10 shows the frequency response of an LC filter with an ESR zero, which comes in at about 10 kHz. The gain

transitions from a slope of –40 dB to a slope of –20 Figure 11. A buck converter steps down the input to produce a lower dB, and the phase turns positive for 90 degrees output voltage. Figure 10 over two decades. Forward, two-switch forward, active-clamp forward s and half-bridge converters are also buck-derived 1+ ω topologies, but their input/output voltage transfer H (s) = Z (6) s s2 1+ + functions are multiplied by the transformer turns Q ⋅ω ω 2 O O O ratio. See Equation 8. Push-pull, full bridge and phase-shifted full bridge also have the same input/ 20 45 output voltage transfer function, but with a factor

0 0 of 2 multiplier as well as the transformer turns ratio.

-20 -45 See Equation 9.

-40 -90 N Phase (°) Phase S (8) VOUT = VIN ⋅ D⋅

Magnitude (dB) Magnitude N -60 -135 P

-80 -180 N 0.01 0.1 1 10 100 1000 V = V ⋅2⋅ D ⋅ S (9) OUT IN N Frequency (kHz) P

Boost topologies Figure 10. An ESR zero after the complex conjugate pole causes the slope of the gain to reduce to –20 dB/decade, while the phase shift Boost topologies deliver energy to the output 180 moves toward –90 degrees. degrees out of phase with the energy delivered to Buck-derived topologies the input. This causes a right-half-plane zero to appear in the transfer function. Figure 12 shows a Buck-derived topologies deliver power to the output boost power stage, along with its associated input/ after reception at the input. Buck-derived topologies output voltage transfer function. In Equation 10, D running in CCM with voltage-mode feedback have is the off-time duty cycle given by D = 1 – D. an LC filter response with one complex conjugate ˊ pole and one ESR zero. Figure 11 shows a buck ˊ

Texas Instruments 6 September 2016 Figure 13

Figure 12

1 V OUT =VIN ⋅ (10) D′

IN OUT

Figure 13. A single switch buck-boost converter inverts the polarity of the input voltage. The magnitude of the output voltage can be lower or higher than the input.

Figure 12. A boost converter steps up the input to produce a higher output voltage. Voltage-mode buck Operation of a voltage-mode buck modulator is Buck-boost-derived topologiesFigure 14 very straightforward. Along with the schematic for a Inverting buck-boost, flyback, single-ended primary voltage-mode buck power stage, Figure 14 shows

inductor converter (SEPIC), Zeta and Cuk converters how comparing the feedback error voltage, VC, with a

are examples of buck-boost-derived topologies. linear ramp, VRAMP, accomplishes PWM. These topologies have the potential to buck down the input voltage or boost up the input voltage, much like the more advanced buck-derived topologies that use a transformer. The exception is the inverting buck-boost, which inverts the polarity of the voltage at the output. Buck-boost topologies store energy in the inductor on the first part of the switching period, delivering that energy to the output during the second part of the switching period. Much like a boost converter, this creates a right-half-plane zero, which as we mentioned before can complicate the compensation of the feedback loop. Figure 14. This voltage-mode-controlled buck converter detail shows Figure 13 shows a schematic of an inverting the control voltage intersecting the ramp modulating the PWM duty buck-boost, while Equation 11 shows the input- cycle. to-output voltage relationship. Equation 11 holds true for inverting buck-boost, Zeta, Cuk and SEPIC Equations 13 and 14 calculate the duty cycle relationship for a buck converter in CCM: topologies. The flyback equation, Equation 12, has the multiplier of the coupled inductor (transformer) VOUT D = (13) turns ratio. VIN

D VIN −VOUT V OUT =VIN ⋅ (11) D ′ = (14) D′ VIN

D NS V OUT = VIN ⋅ ⋅ (12) D′ NP

Texas Instruments 7 September 2016 Equation 15 shows the transfer function for a more gradual slope over two decades. A high-Q voltage-mode buck converter: LC filter can cause a –180 degree phase shift in s the loop Bode plot. You may be able to minimize 1+ v ˆ ω OUT = A ⋅ Z this phase shift by moving the error-amplifier zeros VC 2 (15) vˆC s s 1+ + 2 to coincide with the LC resonant frequency. (We QO ⋅ωO ω O will use this method in the voltage-mode buck The transfer function comprises several parts. The example.) Equation 19 for Q ignores the output first part is the PWM modulator gain. The PWM capacitor’s ESR and the inductor’s DC resistance. output is a pulse waveform averaged by the output Both of these effects will slightly lower the Q. filter and applied to the load as a direct current ROUT QO = (DC) voltage. The modulator gain is the average of L (19) C this pulse train divided by the control voltage. The OUT control voltage is bounded by theFigure ramp, while 15 the We typically see voltage mode used only for buck- output is bounded by zero and the input voltage. derived topologies, because these topologies don’t Equation 16 defines the modulator gain for a CCM exhibit a right-half-plane zero in the power-stage voltage-mode buck, where the input voltage is transfer function. Figure 15 shows the associated

divided by the peak-to-peak ramp voltage, VRAMP. Bode response. The second part is a complex conjugate pole characteristic of the LC output filter. It rolls off at 40 45 O AVC –40 dB/decade, with a phase change of –180 20 2 0 degrees. See Equation 17. This pole is followed by  0 Z -45 the ESR zero of the output capacitor in Equation 18, 2 -20 -90 reducing the slope to –20 dB/decade. (°) Phase

Magnitude (dB) Magnitude -40 -135 dv d ⎛ v ⎞ V OUT ⎜ C ⎟ IN (16) -60 -180 AVC = = ⋅⎜vIN ⋅ ⎟ = dvC dvC ⎝ vRAMP ⎠ VRAMP 0.01 0.1 1 10 100 1000 EQua16 Frequency (kHz) 1 (17) ωO = Figure 15. The voltage-mode buck frequency response has the L⋅COUT characteristic complex conjugate pole with ESR zero.

1 (18) ωZ = Current-mode buck RESR ⋅COUT The difference between voltage- and current-mode The Q associated with the complex conjugate control is that for current-mode control, the PWM pole determines the slope of the phase. See modulator uses the inductor ripple current as the Equation 19. As we discussed in the section on ramp. Voltage-mode control uses a fixed ramp, complex conjugate poles, Q complicates converter which contains no information about the inductor compensation because as Q increases, the phase current. Current-mode control exhibits some slope increases. This means that the phase changes desirable attributes because it samples the inductor much quicker over a small band of frequencies, current. The inner current loop splits the complex whereas two regular poles would change with a conjugate pole of the filter into two real poles, turning

Texas Instruments 8 September 2016 the modulator into a voltage-controlled current V source. Current-mode control also provides a cycle- D = OUT (20) VIN by-cycle current limit, which is advantageous for V −V protecting the power stage. D ′ = IN OUT (21) VIN Along with these advantages comes a not-so- advantageous attribute: subharmonic oscillation. Equation 22 shows the transfer function for the Subharmonic oscillation occurs when the inductor current-mode buck power stage: ripple current does not return to its initial value by the s start of next switching cycle. For peak current-mode 1+ vˆOUT ωZ ≈ AVC ⋅ control, this occurs at a duty cycle greater than 50 vˆ ⎛ s ⎞ ⎛ s ⎞ (22) C ⎜1+ ⎟⋅⎜1+ ⎟ ⎜ ω ⎟ ⎜ ω ⎟ percent. With larger inductances, as the slope of ⎝ P ⎠ ⎝ L ⎠ the inductor current decreases and tends toward As you can see, in Equation 22 the transfer function becoming flat, the PWM modulator can trigger on is made up of gain, A , calculated by Equation 23: noise, making the problem worse. Subharmonic VC

oscillation is normally characterized by alternating ROUT AVC ≈ wide and narrow pulses at the switch node. An Ri (23) external ramp added to the inductor current ramp where = ⋅ . i AR R S cancels the subharmonic oscillation and is known as Equations 24 and 25 express two separate poles. slope compensation. This external ramp stabilizes The first pole (Equation 24) is related to the output the modulator gain. capacitor and the output load: Figure 16 shows the schematic of the current-mode 1 ω ≈ (24) buck power stage. P C ⋅ R Figure 16 OUT OUT Equations 20 and 21 give the duty-cycle relationship The second pole (Equation 25) is related to the for the current-mode buck in CCM, which is the inductance and V . The modulator voltage same as voltage mode: SLOPE

gain, Km, is equal to VIN/VSLOPE at D = 0.5 and will have little variation with operating conditions when

properly scaling VSLOPE.

Km ⋅Ri ωL = L (25)

 VIN where Km ≈ at D = 0.5. VSLOPE

Figure 16. The current-mode buck power stage incorporates the The transfer function also contains an ESR zero inductor current sense as an inner control loop. The current loop acts as a lossless damping resistor, splitting the complex conjugate associated with the output capacitor, expressed as pole of the output filter into two real poles. It turns the modulator into Equation 26: a voltage-controlled current source, where the inductor current is

proportional to the control voltage at VC. 1 ω Z = (26) RESR ⋅COUT

Texas Instruments 9 September 2016 For the peak current-mode buck, Equation 27 Current-mode boost calculates the optimal value of slope compensation: The current-mode boost is similar to the current-

mode buck, but the current-mode boost exhibits VOUT ⋅Ri ⋅T V SLOPE = (27) L a right-half-plane zero in the transfer function. This is because energy is stored in the inductor during

where Ri is the current-sense gain times the the switch on-time and delivered to the output sense resistor, and T is equal to the switching during the off-time. This energy storage and delivery period, 1/f . SW Figure 18 tends to limit the overall loop bandwidth due to the Dozens of papers tackle the subject of modeling associated phase lag of the right-half-plane zero. current-mode control. Simple average modeling is Figure 18 shows the schematic of the current- usually good enough for most applications. More mode boost power stage. accurate models that look at the control behavior up to and beyond half the switching frequency are becoming more common. While these are simplified, Equation 22 and the Bode plot in Figure 17 are common for the current-mode buck power stage.  Not all data sheets have enough information to accurately calculate the control-to-output gain.

Both the equivalent current-sense gain, Ri, and Figure 18. In this example of a current-mode boost power stage, slope compensation, VSLOPE, are required, but for the inductor current is sampled in the metal-oxide semiconductor Figure 17 internally compensated regulators, data sheets may field-effect transistor (MOSFET) source resistor. not include the value of R, or may not list the value i Equations 28 and 29 give the duty-cycle relationship of V for switching regulators with internal power SLOPE for the current-mode boost in CCM: switches. Only the power stage L and COUT are available to adjust the response. V −V D = OUT IN (28) VOUT

40 45 P VIN AVC D ′ = (29) 20 2 0 VOUT

0 -45 Equation 30 shows the transfer function for the -20 -90 current-mode boost power stage. As you can see,

Phase (°) Phase Z L Magnitude (dB) Magnitude it contains two poles, one zero, one right-half-plane -40 2 2 -135 zero and an associated gain. -60 -180 0.01 0.1 1 10 100 1000 ⎛ s ⎞ ⎛ s ⎞ Frequency (kHz) ⎜1− ⎟⋅⎜1+ ⎟ (30) vˆOUT ⎝ ωR ⎠ ⎝ ωZ ⎠ ≈ AVC ⋅ Figure 17. The current-mode buck power stage exhibits a single pole vˆ ⎛ s ⎞ ⎛ s ⎞ C ⎜ ⎟ ⎜ ⎟ at as the dominant characteristic ⎜1+ ⎟⋅⎜1+ ⎟ P ⎝ ωP ⎠ ⎝ ωL ⎠ ω

Texas Instruments 10 September 2016 Figure 19

Equation 31 expresses the gain as: Figure 19 shows the Bode plot of the current-mode boost power stage. OUT ⋅ DR ′ A VC ≈ (31) 2⋅ Ri 40 45 P where and ′ AVC  i = AR ⋅ R S = 1− DD . 20 2 L 0 2 Equation 32 calculates the first pole, which is related 0 -45   to the output capacitance and the load resistance. -20 R Z -90 Phase (°) Phase The effect of boosting moves the pole out by a 2 2 Magnitude (dB) Magnitude -40 -135 factor of two [9]. -60 -180 2 0.01 0.1 1 10 100 1000 ω P ≈ (32) Frequency (kHz) COUT ⋅ ROUT Figure 19. The current-mode boost power stage has a right-half- Equation 33 calculates the second pole, which is plane zero at R in the transfer function. related to the inductance. The modulator voltage Current-modeω buck-boost gain, Km, is equal to VOUT/VSLOPE at D = 0.5 and will have little variation with operating conditions when Like the current-mode boost, the current-mode buck-boost also exhibits a right-half-plane zero properly scaling VSLOPE. in the transfer function. It has the same energy Km ⋅Ri ωL = storage characteristic during the switch on-time, L with energy delivered to the output during the (33) V where K ≈ OUT at D = 0.5. off-time. Again, this tends to limit the overall loop m V SLOPE bandwidth due to the associated phase lag of the right-half-plane zero. Equation 34 gives the right-half-plane zero, which is related to the inductance and output Figure 20 shows the schematic of the current- mode buck-boost power stage. For the buck-boost, resistance, while Equation 35 is related to the output the convention used here is to define either V or capacitance ESR: Figure 20 IN V with its sign on the schematic. This is shown in 2 OUT ROUT ⋅ D′ ω R = (34) Figure 20 as –V . All equations use the absolute L OUT value of VIN and VOUT, regardless of sign. 1 ω = (35) Z ⋅ RESR COUT

For the peak current-mode boost, Equation 36 calculates the optimal value of slope compensation:

(VOUT −VIN )⋅Ri ⋅T (36) VSLOPE = L 

where Ri is the current-sense gain times the sense resistor, and T is equal to the switching period, Figure 20. This positive-to-negative current-mode buck-boost power stage is a level-shifted version of the standard buck converter. 1/fSW.

Texas Instruments 11 September 2016 Equations 37 and 38 give the duty-cycle relationship 2 ROUT ⋅ D′ for the current-mode buck-boost in CCM: ω R = (43) L⋅ D

V D = OUT (37) 1 ω = (44) VIN +VOUT Z RESR ⋅COUT

V D ′ = IN (38) For the peak current-mode buck-boost,

VIN +VOUT Equation 45 calculates the optimal value of slope

Equation 39 shows the transfer function for the compensation: current-mode buck-boost power stage. As you can V ⋅R ⋅T see, it contains two poles, one zero, one right-half- V = OUT i (45) SLOPE L plane zero and an associated gain. Figure 21 where R is the current-sense gain times the sense i ⎛ s ⎞ ⎛ s ⎞ ⎜1− ⎟⋅⎜1+ ⎟ ⎜ ⎟ ⎜ ⎟ resistor, and T is equal to the switching period, vˆOUT ⎝ ωR ⎠ ⎝ ωZ ⎠ ≈ AVC ⋅ (39) 1/fSW. vˆC ⎛ s ⎞ ⎛ s ⎞ ⎜1+ ⎟⋅⎜1+ ⎟ ⎝ ωP ⎠ ⎝ ωL ⎠ Figure 21 shows the Bode plot of the current-mode

buck-boost power stage. Equation 40 expresses the gain as:

⋅ DR ′ A ≈ OUT 40  45 VC 1+ ⋅ RD (40) P ()i AVC  20 2 L 0 2 where i = AR ⋅ R S and ′ = 1− DD . 0 -45 Equation 41 calculates the first pole, which is related   -20 R Z -90 to the output capacitance and the load resistance: 2 2 (°) Phase Magnitude (dB) Magnitude -40 -135 1+ D ω P ≈ (41) -60 -180 COUT ⋅ ROUT 0.01 0.1 1 10 100 1000 Frequency (kHz) Equation 42 calculates the second pole, which is

related to the inductance. The modulator voltage Figure 21. Like the current-mode boost, the current-mode buck-boost power stage also has a right-half-plane zero at in the transfer gain, K , is equal to (V +V )/V at D = 0.5 and R m IN OUT SLOPE function. will have little variation with operating conditions ω

when properly scaling VSLOPE. Current-mode forward and other buck-derived topologies ⋅RK ω = im L L The current-mode forward is similar to the current- (42) mode buck, since energy transfers to the output + where IN VV OUT at D = 0.5. Km ≈ during the primary switch on-time. Adjusting the VSLOPE transformer turns ratio provides the nominal output Equation 43 gives the right-half-plane zero, voltage within a practical duty-cycle range. which is related to the inductance and output Figure 22 shows the schematic of the current- resistance, while Equation 44 is related to the output mode forward power stage. capacitance ESR:

Texas Instruments 12 September 2016 Figure 22

T1 Equation 51 calculates the second pole, which is NP : NS D1 L related to the inductance. The modulator voltage VIN VOUT COUT CIN gain, K , is equal to V /V at D = 0.5 and will D2 ROUT m IN SLOPE RESR PWM have little variation with operating conditions when Logic Q1 properly scaling VSLOPE. VSLOPE A + 2 RS -  m ⋅RK ⎛ NSi ⎞ ωL = ⋅⎜ ⎟ + VC ⎜ ⎟ L ⎝ NP ⎠ (51) Figure 22. A single-switch current-mode forward power stage has a buck-type output at the secondary. The inductor current is reflected VIN where Km ≈ at D = 0.5. into the primary and sampled in series with the switch. VSLOPE

Equation 52 gives the zero, which is related to the Equations 46 and 47 give the duty-cycle relationship output capacitance ESR: for the current-mode forward in CCM: 1 ω = VOUT N P Z (52) D = ⋅ (46) RESR ⋅ COUT VIN NS

For the peak current-mode forward, Equation 53 NP VIN −VOUT ⋅ NS (47) calculates the optimal value of slope compensation: D′ =

VIN

VOUT ⋅Ri ⋅T NS V SLOPE = ⋅ (53) Equation 48 shows the transfer function for the L N P current-mode forward power stage. As you can where R is the current-sense gain times the see, it contains two poles, one zero and an i Figure 23 sense resistor, and T is equal to the switching associated gain. period, 1/f . s SW 1+ vˆOUT ωZ Figure 23 shows the Bode plot of the current-mode ≈ AVC ⋅ vˆC ⎛ s ⎞ ⎛ s ⎞ (48) forward power stage. ⎜1+ ⎟⋅⎜1+ ⎟ ⎝ ωP ⎠ ⎝ ωL ⎠

Equation 49 expresses the gain as: 40 45 P AVC R N 20 2 0 A ≈ OUT ⋅ P VC Ri NS (49) 0 -45

-20 -90 where Ri = A⋅ RS . (°) Phase Z L Magnitude (dB) Magnitude -40 2 2 -135 Equation 50 calculates the first pole, which is related -60 -180 to the output capacitance and the load resistance: 0.01 0.1 1 10 100 1000

Frequency (kHz) 1 ω P ≈ (50) COUT ⋅ ROUT Figure 23. The current-mode forward power-stage frequency response is similar to that of the buck.

Texas Instruments 13 September 2016 Current-mode flyback Equation 57 expresses the gain as: The current-mode flyback has a right-half-plane zero ⋅ DR ′ N ≈ OUT ⋅ P in the transfer function. The magnetizing inductance AVC ()1+ ⋅ RD i NS (57) stores energy during the switch on-time, with where and ′ energy delivered to the output during the off-time. i = AR ⋅ R S = 1− DD .

This tends to limit the overall loop bandwidth due Equation 58 calculates the first pole, which is related Figure 24 to the associated phase lag of the right-half-plane to the output capacitance and the load resistance: zero. 1+ D Figure 24 shows the schematic of the current- ω ≈ (58) P C ⋅ R mode flyback power stage. OUT OUT

T1 Equation 59 calculates the second pole, which is NP : NS D1 VIN VOUT related to the inductance. The modulator voltage COUT CIN L P ROUT gain, K , is equal to (V +V ·N /N )/V at D RESR m IN OUT P S SLOPE PWM = 0.5 and will have little variation with operating Logic Q1

VSLOPE conditions when properly scaling VSLOPE. A + R -  S ⋅RK + V ω = im C L L P (59) Figure 24. For the current-mode flyback power stage, the isolation N transformer also serves as the energy-storage inductor. +VV ⋅ P IN OUT N where K ≈ S at D = 0.5. m V Equations 54 and 55 give the duty-cycle relationship SLOPE for the current-mode flyback in CCM: Equation 60 gives the right-half-plane zero, which is related to the inductance and output V D = OUT N resistance, while Equation 61 is related to the output V ⋅ S +V (54) IN OUT N P capacitance ESR:

2 2 VIN ′ ⎛ ⎞ D ′ = (55) ROUT ⋅ D NP (60) ωR = ⋅⎜ ⎟ NP ⎜ ⎟ VIN +VOUT ⋅ LP ⋅ D ⎝ NS ⎠

NS 1 Equation 56 shows the transfer function for the ω Z = (61) RESR ⋅COUT current-mode flyback power stage. As you can see, it contains two poles, one zero, one right-half-plane For the peak current-mode flyback, Equation 62 zero and an associated gain. calculates the optimal value of slope compensation:

⎛ s ⎞ ⎛ s ⎞ ⎜1− ⎟⋅⎜1+ ⎟ ⎜ ⎟ ⎜ ⎟ VOUT ⋅Ri ⋅T NP vˆOUT ⎝ ωR ⎠ ⎝ ωZ ⎠ V SLOPE = ⋅ (62) ≈ AVC ⋅ (56) L N vˆ ⎛ s ⎞ ⎛ s ⎞ P S C ⎜1+ ⎟⋅⎜1+ ⎟ ⎜ ⎟ ⎜ ⎟ ⎝ ωP ⎠ ⎝ ωL ⎠

Texas Instruments 14 September 2016 where Ri is the current-sense gain times the Equation 63 is written by summing the currents at Figure 25 sense resistor, and T is equal to the switching the error-amplifier inputs:

period, 1/fSW. vˆ′ vˆ ⎛ 1 1 ⎞ OUT C ˆ ⎜ ⎟ (63) Figure 25 shows the Bode plot of the current-mode + = vFB ⋅⎜ + ⎟ RFBT ZCOMP ⎝ RFBT ZCOMP ⎠ flyback power stage. Equation 64 relates the feedback voltage to the control voltage by the open loop gain of the 40  45 P amplifier: AVC  20 2 L 0 2 − vˆ 0 -45 v ˆ = C (64) FB A   OL -20 R Z -90 2 2 (°) Phase

Magnitude (dB) Magnitude -40 -135 Equation 65 combines Equations 63 and 64:

-60 -180 ⎛ ⎞ 0.01 0.1 1 10 100 1000 ⎜ ⎟ Frequency (kHz) vˆC ZCOMP ⎜ 1 ⎟ = − ⋅⎜ ⎟ (65) vˆ′ R 1 ⎛ Z ⎞ OUT FBT ⎜1+ ⋅⎜1+ COMP ⎟ ⎟ Figure 25. The current-mode flyback power-stage frequency ⎜ ⎜ ⎟ ⎟ ⎝ AOL ⎝ RFBT ⎠ ⎠ response is similar to that of the buck-boost. Equation 66 shows that if the gain of the error Type I error amplifier amplifier is large enough Figure 26 shows a Type I error amplifier ⎛ R ⎞ configuration, which is the simplest form of A ⋅⎜ FBT ⎟ >> 1 (66) OL ⎜ R + Z ⎟ compensation; it is characterized by a single pole. ⎝ FBT COMP ⎠

You can analyze this circuit by recognizing that the Then the closed-loop gain can be expressed by error amplifier is inverting and has a virtual short Equation 67 as: between VFB and VREF. The feedback impedance divided by the input impedance gives you the small vˆ Z 1 ω Figure 26 C ≈ − COM P = − = − EA (67) ˆ′ ⋅ ⋅ signal gain. Since VREF can be viewed as an AC vOUT RFBT s CCOM P RFBT s

ground, you can ignore the value of RFBB, as it does not affect the AC transfer function. Equation 68 defines the error amplifier pole frequency:

1 ω EA = (68) RFBT ⋅CCOM P

Examining the result reveals a single pole at the origin. In practice, this is limited at DC by the open-loop gain of the amplifier and is called dominant-pole compensation. Figure 26. Type I error amplifier compensation has a single capacitor in the feedback. Figure 27 shows the straight-line approximation of the frequency response for an error amplifier with Type I compensation. Type I compensation is often

Texas Instruments 15 September 2016 Power Supply Design Seminar 2016/17

used for a constant-current type of current-mode where AVM is defined as the mid-band voltage gain. buck, driving a light-emitting diode (LED) load with Examining the result reveals that in Equation 70 the Figure 27 no output capacitor. While you can use this type of mid-band voltage gain is: dominant-pole compensation for any power RCOM P supply, for many systems this type of A VM ≈ (70) RFBT compensation does not offer the flexibility necessary to achieve optimal performance. Equation 71 reveals a zero at:

1 60 135 ω ZEA = (71) COM P ⋅CR COM P 40 90

20 45 While Equation 72 reveals a high-frequency pole at:

0 0  (°) Phase 1 EA ωHF ≈ Magnitude (dB) Magnitude -20 -45 COM P ⋅CR HF 2 (72) -40 -90 assuming 0.01 0.1 1 10 100 1000 COMP >> CC HF . Frequency (kHz) In practice, the open-loop gain of the amplifier Figure 27. A Type I error-amplifier frequency response is will limit the error-amplifier gain at DC. Type II characterized by a single pole. Figure 28 compensation is generally well suited for use with Type II error amplifier current-mode control. In selective cases, you can Figure 28 shows the schematic of a Type II error use it for voltage-mode control with a high value of amplifier. Figure 29 ESR in the output capacitor. Figure 29 shows the straight-line approximation of the frequency response for an error amplifier with Type II compensation.

80 180

60 135

40 90 Figure 28. Type II error-amplifier compensation adds a resistor and high-frequency capacitor to the feedback. 20 AVM 45 Phase (°) Phase ZEA HF Magnitude (dB) Magnitude 0 2 2 0 Using the same derivation process as for Type I -20 -45 compensation, Equation 69 expresses the 0.01 0.1 1 10 100 1000 Frequency (kHz) voltage-gain transfer function as: Figure 29. A Type II compensator frequency response has a mid-band ω s 1+ ZEA 1+ gain between the zero and pole. vˆC s AVM ⋅ωZEA ωZEA AVM ⋅−≈ −≈ ⋅ (69) vˆ′ s s s OUT 1+ 1+ ωHF ωHF

Texas Instruments 16 September 2016 Type II transconductance amplifier The difference is in the mid-band voltage gain, given by Equation 74: The difference between a conventional error = ⋅⋅ amplifier and a transconductance amplifier is VM FB m RgKA COMP (74) that with a transconductance amplifier, the input RFBB where K FB = . resistor divider network and the transconductance FBB + RR FBT

(gm) parameter are now a part of the gain transfer function. Recalling the section on Type I error As you can see from Equation 73, a Type II error amplifiers, the bottom resistor of the input divider amplifier has a pole at the origin, a zero and a dropped out of the transfer function due to the second high-frequency pole. Equations 75 and 76 virtual ground effect. Both pins were at the same are identical to Equations 71 and 72:

potential and the AC contribution of the lower 1 ω ZEA = (75) resistor was nonexistent. In a transconductance COM P ⋅CR COM P amplifier, there is no local feedback; therefore there

is no virtual ground. You can no longer ignore the 1 ωHF ≈ bottom resistor of the input divider, and gm can COM P ⋅CR HF vary depending on the integrated circuit design. A (76) assuming C >> C and >> RR . transconductance amplifier is also well suited for COMP HF EA COMP Figure 30 Type II compensation. The transconductance and output resistance of the Figure 30 shows the schematic of a Type II amplifier set the open-loop gain, which will limit the transconductance error amplifier. error-amplifier gain at DC. Equation 77 expresses the open-loop gain as:

OL = m ⋅ RgA EA (77)

You can use the transconductance amplifier for current-mode control. We do not recommend its use for Type III operation with voltage-mode control

Figure 30. Type II transconductance amplifier compensation because of the feedback divider limitation on phase components are referenced to ground at the output. boost for low-voltage outputs. Figure 31 shows the straight-line approximation The voltage-gain transfer function for a Type II of the frequency response for a transconductance transconductance amplifier is the same as for error amplifier with Type II compensation. a regular error amplifier, as you would expect. Equation 73 is identical to Equation 69:

ω s 1+ ZEA 1+ vˆ A ⋅ω ω C A ⋅−≈ s −≈ VM ZEA ⋅ ZEA (73) vˆ′ VM s s s OUT 1+ 1+ ωHF ωHF

Texas Instruments 17 September 2016 Figure 31

The mid-band gain is the same as it is for a Type II 80 180 error amplifier. Equation 79 is identical to Equation 70: 60 135 R A ≈ COM P 40 90 VM (79) RFBT 20 AVM 45   (°) Phase ZEA HF Examining the Type III transfer function reveals Magnitude (dB) Magnitude 0 2 2 0 two zeros: one zero set by RCOMP and CCOMP (Equation -20 -45 80) and another zero set by R and C (see 0.01 0.1 1 10 100 1000 FBT FF Frequency (kHz) Equation 81) to help offset the complex conjugate poles: Figure 31. A transconductance error amplifier with Type II compensation has a frequency response equivalent to a standard 1 operational amplifier. ω ZEA = (80) COM P ⋅CR COM P Type III error amplifier 1 ω ≈ (81) Type III compensation is generally the most useful FZ FBT ⋅CR FF Figure 32 technique for compensating voltage-mode-control

converters, but it requires two additional components RFF and CFF along with RCOMP and CHF determine the not present in Type II compensation, shown in poles in the system, usually occurring after the output Figure 32. filter’s complex conjugate pole. The examples will reveal more on the exact placement of these poles and zeros. See Equations 82 and 83:

1 ω FP = (82) ⋅CR FFFF

1 ω ≈ Figure 32. Type III error-amplifier compensation adds a lead network HF (83) COMP ⋅CR HF across the top divider resistor. assuming and This compensation network provides a pole at CCOMP >> C HF FBT >> RR FF .

the origin, two zeros and two higher-frequency Type III compensation is useful in power supplies poles in the feedback path. The two zeros offset where the output capacitor ESR is very low, such as the complex conjugate pole of the voltage-mode in converters with ceramic output capacitors. buck. Type III compensation can increase both The reason for this is that low-ESR capacitors push the bandwidth and phase margin of a closed-loop the ESR zero higher in frequency than high-ESR system. capacitors. Thus, your converter will not benefit Equation 78 expresses the voltage-gain transfer from the phase boost at lower frequencies, but Type function for Type III compensation as: III compensation can make up for that.

⎛ ωZEA ⎞ ⎛ s ⎞ ⎛ ⎞ ⎛ ss ⎞ ⎜1+ ⎟⋅⎜1+ ⎟ ⎜1+ ⎟⋅⎜1+ ⎟ vˆC ⎝ s ⎠ ⎝ ωFZ ⎠ AVM ⋅ωZEA ⎝ ωZEA ⎠ ⎝ ωFZ ⎠ = AVM ⋅− = − ⋅ vˆOUT′ ⎛ ⎞ ⎛ ss ⎞ s ⎛ ⎞ ⎛ ss ⎞ ⎜ + ⎟⋅⎜11 + ⎟ ⎜ + ⎟⋅⎜11 + ⎟ ⎝ ωFP ⎠ ⎝ ωHF ⎠ ⎝ ωFP ⎠ ⎝ ωHF ⎠ (78)

Texas Instruments 18 September 2016 Figure 33

Figure 33 shows the straight-line approximation of Adding RBIAS maintains a minimum current through the frequency response for an error amplifier with the TL431 for regulation. It is not part of the Type III compensation. frequency compensation network. Equation 84 expresses the voltage-gain transfer function as:

80 270 ω s 1+ ZEA 1+ vˆ A ⋅ω ω 60 225 C ≈ −A ⋅ s ≈ − VM ZEA ⋅ ZEA v ˆ ′ VM s s s (84) OUT 1+ 1+ 40 180 ωHF ωHF 20 135

AVM FP HF 0 90 (°) Phase In Equation 85 the mid-band voltage gain is:   Magnitude (dB) Magnitude ZEA FZ 2 2 -20 45 2 2 RP (85) -40 0 AVM = CTR ⋅ 0.01 0.1 1 10 100 1000 RD

Frequency (kHz) Equation 86 defines the current transfer ratio: Figure 33. A Type III compensator frequency response boosts the gain and phase in the mid band. I CTR = C (86) I F Isolated feedback with optocoupler Figure 34 shows Type II compensation using an As you can see from Equation 84, this isolated optocoupler and the TL431 shunt regulator. The feedback with an optocoupler is configured as a current-transfer ratio and resistors set the mid-band Type II error amplifier, which has a pole at the origin, gain through the optocoupler. Bias currents and the a zero and a second high-frequency pole. See diode forward voltage can limit the dynamic range. Equations 87 and 88: The reference voltage for a standard TL431 is 2.5 1 V, which can work for 5-V outputs and higher. For ω ZEA = (87) RFBT ⋅CCOM P lower output voltages, the TLV431Figure has a 1.24-V 35 reference. 1 ω HF = (88) In Figure 34, CP includes the parasitic capacitance RP ⋅CP

of the optocoupler’s output transistor. Parasitic capacitance is often the limiting factor of the Figure 35 shows the frequency-response plot. Figure 34 bandwidth in this configuration. The associated phase shift can go to –180 degrees, making 80 180 compensation at higher frequencies challenging. 60 135

40 90

20 AVM 45 Phase (°) Phase ZEA HF Magnitude (dB) Magnitude 0 2 2 0 -20 -45 0.01 0.1 1 10 100 1000 Frequency (kHz)

Figure 35. The frequency response of this optocoupler feedback has Figure 34. This isolated feedback with an optocoupler uses a shunt a Type II characteristic. regulator for secondary-side voltage control.

Texas Instruments 19 September 2016 Voltage-mode buck example Once you have selected AVM and calculated Figure 36 is the complete voltage-mode buck the pole/zero location, you can solve for the Figure 36 regulator model, showing the modulator, output filter compensation component values using the and error amplifier. For Type III compensation, use a equations below. We recommend that you verify the standard voltage-type operational amplifier. system crossover frequency and phase margin on the bench to confirm your desired performance.

Use the following simplified design method for the voltage-mode buck:

• Choose a value for RFBT based on the bias current and power dissipation.

• Pick a target bandwidth; typically, fSW/10: C = 2∙π∙fC. • Find A to achieve the target bandwidth. VM ω

• Set ZEA and FZ equal to the output-filter complex conjugate pole : = = . ω ω O ZEA FZ O Figure 36. The complete voltage-mode buck converter with power • Set equal to the output-filter zero, : = . stage and error amplifier. The fixed ramp shown could be proportional, FP ω ω ω ω Z FP Z depending upon the controller. • Set equal to half the switching frequency: = ωHF ω ω HFω 2∙π∙f /2. Voltage-mode buck compensation ωSW ω strategy Solve Equations 89 through 93 to find the We will now outline the compensation guidelines for component values:

a voltage-mode buck with Type III compensation. ωC This is an approximate method. Choose a large A VM = (89) AVC ⋅ωO

value for RFBT; typical values for RFBT are between

2 kΩ and 200 kΩ. AVM, the mid-band voltage gain, R COMP = AVM ⋅ RFBT (90) is one of the design parameters; by changing this

parameter, you can change the performance of the 1 C = system. The value of A that gives you the desired FF (91) VM ωFZ ⋅ RFBT performance will vary with modulator gain. 1 For voltage-mode control, set the system bandwidth C COM P = (92) ωZEA ⋅ RCOM P typically at 10 percent of the switching frequency.

The two zeros, ZEA and FZ, should cancel the 1 C HF = (93) output filter’s complex conjugate pole. Set the ωHF ⋅ RCOM P ω ω pole frequency, FP, to cancel the output-filter zero caused by the output capacitor ESR. Set the high- ω

frequency pole, HF, equal to half the switching frequency. For higher bandwidth, set equal to ω HF the switching frequency. ω

Texas Instruments 20 September 2016 Figure 37 (a)

s 1 Voltage-mode buck compensation vˆ  OUT A  Z VC 2 results vˆC s s 1  2 Q OO O Figure 37 shows the voltage-mode buck idealized straight-line plots of the power stage, error amplifier 40 45 O AVC and control loop. The overall control loop is the 20 2 0 product of the power-stage and error-amplifier 0 -45 transfer functions. On the Bode plots, the overall Z -20 -90 Magnitude (dB) Magnitude 2 (°) Phase loop gain is the sum in decibels of the power-stage -40 -135 gain and error-amplifier gain. Adjust the mid-band -60 -180 gain of the error amplifier to meet the target 0.01 0.1 1 10 100 1000 Frequency (kHz) loop bandwidth. Power stage (a)

Figure 37 (b) Current-mode buck example     s  Figure 38 is the complete current-mode buck 1 ZEA  1    Figure 38 regulator model, showing the modulator, output filter vˆC  s   FZ   AVM  vˆ    ss  and error amplifier. For Type II compensation, this OUT    11         FP   HF  example uses a transconductance amplifier.

60 270  40 HF 225 2 20 180 FP 0 135 2 (°) Phase AVM

Magnitude (dB) Magnitude   -20 ZEA & FZ 90  2  2  -40 45 0.01 0.1 1 10 100 1000 Figure 37 (c) Frequency (kHz) Error amplifier (b) Figure 38. This current-mode buck shows idealized current sensing in series with the inductor. vˆ vˆ vˆ OUT OUT  C   vˆOUT vˆC vˆOUT Current-mode buck compensation

60 135 strategy

40 90 We will now outline the compensation guidelines for

20 45 a current-mode buck with Type II compensation.

0 0 At frequencies after the output-filter pole, the Phase (°) Phase C

Magnitude (dB) Magnitude modulator transconductance and output-filter -20 2 -45 capacitor set the power-stage gain. -40 -90 0.01 0.1 1 10 100 1000 Frequency (kHz) You can adjust the mid-band voltage gain, AVM, to achieve the target loop bandwidth, typically Control loop (c) one-tenth the switching frequency. Figure 37. The power-stage (a) and error-amplifier (b) plots sum to produce the control-loop plot (c) for the voltage-mode buck frequency To give the maximum amount of phase boost, place response. the error-amplifier zero, ZEA, a decade below the target crossover frequency. An alternate strategy ω Texas Instruments 21 September 2016 is to place the error-amplifier zero at the load pole Current-mode buck compensation

of O, which will give you an equivalent result. The results high-frequency pole, , should cancel the ESR ω HF Figure 39 shows the current-mode buck idealized zero of the output capacitor. For capacitors with ω straight-line plots of the power stage, error amplifier very low ESR, set the pole to 10 times the crossover and control loop. frequency. If the error amplifier has a relatively low s 1 vˆ  unity-gain bandwidth, CHF may not be required. OUT Z AVC  vˆC    ss     11   For an ideal current-mode buck, the upper limit for  P    L 

the loop bandwidth is fSW/5. For nonideal parameters 40 90 P – such as a relatively high amount of slope A VC 2 compensation – you may need to lower the loop 20 45  bandwidth to less than f /20. A Type III feedback 0 Z 0 SW 2 network could compensate for this, but is not (°) Phase Magnitude (dB) Magnitude -20 -45 L effective with a transconductance amplifier. 2 -40 -90 0.01 0.1 1 10 100 1000 Use the following simplified design method for the Frequency (kHz) current-mode buck:Figure 39 (b) Power stage (a) • Choose a value for R based on the bias current and FBT  1 ZEA vˆ power dissipation. C  A  s vˆ VM s OUT 1 • Find the modulator transconductance in A/V. HF

• Pick a target bandwidth; typically, fSW/10: C = 2∙π∙fC. 40 225 • Find A to achieve the target bandwidth. VM ω 20 180

• Set ZEA equal to one-tenth the target crossover frequency: 0 AVM 135 ZEA HF = /10. (°) Phase ZEAω C 2 2 Magnitude (dB) Magnitude -20 90 • Set equal to the ESR zero frequency: = . ω HFω HF Z -40 45 Solve Equations 94 through 99 to find the 0.01 0.1 1 10 100 1000 ω ω ω Frequency (kHz) component values:Figure 39 (c) Error amplifier (b) 1 Gm (mod) = (94) R vˆ vˆ vˆ i OUT OUT  C

vˆOUT vˆC vˆOUT

ωC ⋅COUT AVM = (95) Gm (mod) 60 135

40 90 (op amp) (96) RCOMP = AVM ⋅ RFBT 20 45

0 0  (°) Phase AVM C RCOM P = (gm amp) (97) (dB) Magnitude -20 2 -45 gm ⋅ K FB -40 -90 1 0.01 0.1 1 10 100 1000 Frequency (kHz) CCOM P = (98) ωZEA ⋅ RCOM P Control loop (c) 1 C HF = (99) Figure 39. The power-stage (a) and error-amplifier (b) plots sum to ωHF ⋅ RCOM P produce the control-loop plot (c) for the current-mode buck frequency

response.

Texas Instruments 22 September 2016 Current-mode boost example Use the following simplified design method for the Figure 40 is the complete current-mode boost current-mode boost: Figure 40 regulator model, showing the modulator, output filter • Choose a value for RFBT based on the bias current and and error amplifier. For Type II compensation, this power dissipation. example uses a transconductance amplifier. • Find the modulator transconductance in A/V. • Find the right-half-plane zero frequency at the minimum input voltage and maximum load current. • Set the target bandwidth to one-fourth the right-half-plane zero frequency: = 2∙π∙f = /4.  C C R • Find A to achieve the target bandwidth. VM ω ω

• Set ZEA equal to one-tenth the target crossover frequency: = /10. ω ZEA C • Set equal to the lower of the right-half-plane or ESR Figure 40. This current-mode boost senses the current in series with HF ω ω zero frequency: = or . the switch. ω HF R Z Solve Equations 100 through 106 to find the Current-mode boost compensation ω ω ω component values: strategy D′ We will now outline the compensation guidelines for G m (mod) = (100) Ri a current-mode boost with Type II compensation. 2 At frequencies after the output-filter pole, the ROUT ⋅ D′ (101) ωR = modulator transconductance and output-filter L

capacitor set the power-stage gain. The overall ωC ⋅COUT (102) AVM = loop bandwidth is typically limited to one-fourth Gm (mod)

the right-half-plane zero frequency. You can adjust R COMP = AVM ⋅ RFBT (op amp) (103) AVM to achieve the target loop bandwidth. To give

the maximum amount of phase boost, place the A R = VM (104) error-amplifier zero, , a decade below the target COM P (gm amp) ZEA gm ⋅ K FB crossover frequency. The high-frequency pole, , ω HF 1 should cancel the lower of the right-half-plane or C = (105) ω COM P ω ⋅ R ESR zero frequency. ZEA COM P

1 Some sets of operating conditions and parameter C = (106) HF ω ⋅ R values may require additional phase margin. In such HF COM P

cases, the crossover frequency may be limited Current-mode boost compensation to one-fifth or one-sixth the right-half-plane zero results frequency. Figure 41 shows the current-mode boost idealized straight-line plots of the power stage, error amplifier and control loop.

Texas Instruments 23 September 2016 Figure 41 (a)

   ss  Current-mode buck-boost example    11   vˆOUT  R    Z  AVC  Figure 42 is the complete current-mode vˆC    ss     11   buck-boost regulator model, showing the  P    L  Figure 42 modulator, output filter and error amplifier. For 40 45 P Type II compensation, this example uses a AVC  20 2 L 0 transconductance amplifier. 2 0 -45   -20 R Z -90 2 2 (°) Phase

Magnitude (dB) Magnitude -40 -135

-60 -180 0.01 0.1 1 10 100 1000 Frequency (kHz) Figure 41 (b) Power stage (a)   1 ZEA vˆ C  A  s vˆ VM s OUT 1 HF Figure 42. The error amplifier is referenced to -VOUT for this current-mode buck-boost. 40 270 Current-mode buck-boost 20 HF 225 AVM 2 0 180 compensation strategy ZEA -20 2 135 We will now outline the compensation guidelines Phase (°) Phase for the current-mode buck-boost with Type II

Magnitude (dB) Magnitude -40 90

-60 45 compensation. At frequencies after the output-filter 0.01 0.1 1 10 100 1000 pole, the modulator transconductance and output- Frequency (kHz) filter capacitor set the power-stage gain. Figure 41 (c) Error amplifier (b) The overall loop bandwidth is typically limited to one-fourth the right-half-plane zero frequency.

vˆ vˆ vˆ Adjust AVM to achieve the target loop bandwidth. OUT OUT  C vˆOUT vˆC vˆOUT To give the maximum amount of phase boost, place

the error-amplifier zero, ZEA, a decade below the 60 135 target crossover frequency. The high-frequency ω 40 90 pole, HF, should cancel the lower of the right-half- 20 45 plane or ESR zero frequency. ω 0 0 C (°) Phase Some sets of operating conditions and parameter 

Magnitude (dB) Magnitude 2 -20 -45 values may require additional phase margin. -40 -90 0.01 0.1 1 10 100 1000 In such cases, the crossover frequency may be Frequency (kHz) limited to one-fifth or one-sixth the right-half-plane Control loop (c) zero frequency.

Figure 41. The power-stage (a) and error-amplifier (b) plots sum to produce the control-loop plot (c) for the current-mode boost frequency response.

Texas Instruments 24 September 2016 Figure 43 (a)

Use the following simplified design method for the    ss     11   current-mode buck-boost: vˆOUT  R    Z  AVC  vˆ    ss  C    11   • Choose a value for RFBT based on the bias current and      P    L  power dissipation. 40 45 • Find the modulator transconductance in A/V. P AVC  20 2 L 0 • Find the right-half-plane zero frequency at the minimum 2 0 -45 input voltage and maximum load current.   -20 R Z -90 • Set the target bandwidth to one-fourth the right-half-plane 2 2 (°) Phase Magnitude (dB) Magnitude -40 -135 zero frequency: C = 2∙π∙fC = R/4. -60 -180 • Find A to achieve the target bandwidth. 0.01 0.1 1 10 100 1000 VM ω ω Frequency (kHz) • Set equal to one-tenth the target crossover ZEAFigure 43 (b) Power stage (a) frequency: = /10. ω ZEA C  • Set equal to the lower of the right-half-plane or ESR 1 ZEA HF ω ω vˆ C  A  s zero frequency: = or . vˆ VM s ω HF R Z OUT 1 HF Solve Equations 107ω throughω ω 113 to find the component values: 40 270 20  225 D′ (107) HF AVM 2 G m (mod) = 0 180 Ri ZEA -20 2 135 2 Phase (°) Phase ROUT ⋅ Dʹ′ (108)

ω = (dB) Magnitude -40 90 R L ⋅ D -60 45 0.01 0.1 1 10 100 1000 ωC ⋅COUT (109) AVM = Figure 43 (c) Frequency (kHz) Gm (mod) Error amplifier (b) (110) RCOMP = AVM ⋅ RFBT (op amp) vˆ vˆ vˆ OUT OUT  C vˆOUT vˆC vˆOUT AVM (111) RCOM P = (gm amp) gm ⋅ K FB 60 135

1 (112) 40 90 C = COM P 20 45 ωZEA ⋅ RCOM P 0 0  (°) Phase 1 (113) C C =  HF (dB) Magnitude -20 2 -45 ωHF ⋅ RCOM P -40 -90 0.01 0.1 1 10 100 1000 Current-mode buck-boost Frequency (kHz) compensation results Control loop (c) Figure 43 shows the current-mode buck-boost idealized straight-line plots of the power stage, error Figure 43. The power-stage (a) and error-amplifier (b) plots sum to produce the control-loop plot (c) for the current-mode buck-boost amplifier and control loop. frequency response.

Texas Instruments 25 September 2016 Isolated current-mode forward the optocoupler feedback, which incorporates the example primary-side amplifier. In this configuration, the optocoupler emitter is at a virtual ground of V Figure 44 is the complete isolated current-mode REF. This minimizes the pole due to the optocoupler’s Figure 44 forward converter model, showing the modulator, parasitic capacitance, since the collector-to-emitter output filter and error amplifier. For Type II voltage does not change. compensation, this example uses a TL431 shunt regulator and optocoupler. For an ideal current-mode forward, the upper T1 limit for the loop bandwidth is f /5. For nonideal NP : NS D1 L SW VIN VOUT COUT CIN parameters such as a relatively high amount of D2 ROUT RESR PWM slope compensation, you may need to lower the Logic Q1

VSLOPE loop bandwidth to less than fSW/20. + + VCC C RS RD S -  Ri + RFBT RP Use the following simplified design method for the

VC CCOMP - current-mode forward: + RE Peak current-mode forward VREF • Choose a value for R based on the bias current and TL431 RFBB FBT Optimal VSLOPE = VOUT·Ri·T/L·NS/NP power dissipation. Figure 44. This isolated current-mode forward converter uses the • Find the modulator transconductance in A/V. primary-side error amplifier as part of the feedback.

• Pick the target bandwidth; typically, fSW/10: C = 2∙π∙fC. Current-mode forward compensation • Find A to achieve the target bandwidth. VM ω strategy • Adjust RD, RP and COUT as required. We will now outline the compensation guidelines for • Set ZEA equal to one-tenth the target crossover a current-mode forward with Type II compensation. frequency: = /10. ω ZEA C At frequencies after the output-filter pole, the • Set equal to the ESR zero frequency: = . HF ω ω HF Z modulator transconductance and output-filter Solve Equationsω 114 through 118 to findω theω capacitor set the power-stage gain. Adjust A to VM component values: achieve the target loop bandwidth, typically one-

tenth the switching frequency. The selection of R 1 N P D G m (mod) = ⋅ (114) Ri NS and RP for DC bias considerations may limit AVM. In such cases, you may need to increase C OUT ω ⋅C C OUT (115) to meet the desired crossover frequency. To give AVM = Gm (mod) the maximum amount of phase boost, place the R error-amplifier zero, ZEA, a decade below the target P RD = CTR ⋅ (116) crossover frequency. The high-frequency pole, , AVM ω HF should cancel the ESR zero of the output capacitor. ω 1 C COM P = (117) For capacitors with very low ESR, you can set the RFBT ⋅ωZEA pole to 10 times the crossover frequency. This example uses a high-bandwidth configuration for 1 C S = (118) RS ⋅ωHF

Texas Instruments 26 September 2016 Figure 45 (a)

s Current-mode forward compensation 1 vˆOUT Z AVC  results vˆC    ss     11   Figure 45 shows the current-mode forward  P    L  idealized straight-line plots of the power stage, error 40 90 amplifier and control loop. P A VC 2 20 45 Isolated current-mode flyback  0 Z 0 2 example Phase (°) Phase

Magnitude (dB) Magnitude -20 -45 Figure 46 Figure 46 is the complete current-mode flyback L 2 regulator model showing the modulator, output -40 -90 0.01 0.1 1 10 100 1000 filter and error amplifier. For Type II compensation, Frequency (kHz) this example uses a TL431 shunt regulator and Figure 45 (b) Power stage (a) optocoupler. T1  NP : NS D1 1 ZEA VIN VOUT ˆ COUT vC s CIN LP  AVM  ROUT ˆ s RESR vOUT  1 PWM HF Logic Q1

VSLOPE A VCC

+ + 40 225 RS -  Ri = A·RS + RP RD 20 180 VC

CP RBIAS A 0 VM  135 ZEA HF RFBT

Phase (°) Phase CCOMP 2 2 Peak current-mode flyback TL431

Magnitude (dB) Magnitude -20 90 Optimal VSLOPE = VOUT·Ri·T/LP·NP/NS RFBB -40 45 0.01 0.1 1 10 100 1000 Figure 46. The optocoupler feedback for this isolated current-mode Figure 45 (c) Frequency (kHz) flyback is implemented with a minimum of components. Error amplifier (b) Current-mode flyback compensation vˆ vˆ vˆ strategy OUT OUT  C   vˆOUT vˆC vˆOUT We will now outline the compensation guidelines for the current-mode flyback with Type II compensation. 60 135 At frequencies after the output-filter pole, the 40 90 modulator transconductance and output-filter 20 45 capacitor set the power-stage gain. The overall loop 0 0

Phase (°) Phase bandwidth is typically limited to one-fourth the right- C

Magnitude (dB) Magnitude -20  -45 2 half-plane zero frequency. Adjust AVM to achieve the

-40 -90 target loop bandwidth. The selection of RD and RP 0.01 0.1 1 10 100 1000 for DC bias considerations may limit A . In such Frequency (kHz) VM

cases, you may need to increase COUT to meet the Control loop (c) desired crossover frequency. To give the maximum amount of phase boost, place the error-amplifier Figure 45. The power-stage (a) and error-amplifier (b) plots sum zero, , a decade below the target crossover to produce the control-loop plot (c) for the current-mode forward ZEA frequency. The high-frequency pole, , should frequency response. ω HF cancel the lower of the right-half-plane or ESR ω zero frequency.

Texas Instruments 27 September 2016 Figure 47 (a)

Some sets of operating conditions and parameter    ss     11   values may require additional phase margin. vˆOUT  R    Z  AVC  vˆ    ss  In such cases, the crossover frequency may be C    11        limited to one-fifth or one-sixth the right-half-plane  P   L 

zero frequency. 40 45 P AVC  Use the following simplified design method for the 20 2 L 0 current-mode flyback: 2 0 -45 • Choose a value for R based on the bias current and   FBT -20 R Z -90 power dissipation. 2 2 (°) Phase Magnitude (dB) Magnitude -40 -135 • Find the modulator transconductance in A/V. -60 -180 • Find the right-half-plane zero frequency at the minimum 0.01 0.1 1 10 100 1000 Frequency (kHz) input voltage and maximum load current. • Set the targetFigure bandwidth 47 to (b)one-fourth the right-half-plane Power stage (a) zero frequency: = 2∙π∙f = /4. C C R  1 ZEA • Find A to achieve the target bandwidth. vˆC s VM ω ω  A  vˆ VM s OUT 1 • Adjust RD, RP and COUT as required. HF

• Set ZEA equal to one-tenth the target crossover frequency: = /10. 40 270 ω ZEA C 20 HF 225 • Set HF equal to the lower of the right-half-plane or ESR ω ω AVM 2 zero frequency: = or . 0  180 ω HF R Z ZEA -20 2 135

Solve Equations 119ω throughω ω 124 to find the (°) Phase Magnitude (dB) Magnitude -40 90 component values: -60 45 0.01 0.1 1 10 100 1000 D′ N P (119) G (mod) = ⋅ m Frequency (kHz) RFigurei NS 47 (c) 2 Error amplifier (b) R ⋅ D′2 ⎛ N ⎞ OUT ⎜ P ⎟ (120) ωR = ⋅⎜ ⎟ LP ⋅ D ⎝ NS ⎠ vˆ vˆ vˆ OUT OUT  C ˆ ˆ ˆ ωC ⋅COUT (121) vOUT vC vOUT AVM = Gm (mod) 60 135

RP (122) 40 90 RD = CTR ⋅ AVM 20 45

1 0 0 (°) Phase C = (123) COM P  R ⋅ω (dB) Magnitude C FBT ZEA -20 -45 2 1 -40 -90 C P = (124) 0.01 0.1 1 10 100 1000 RP ⋅ωHF Frequency (kHz) Current-mode flyback compensation Control loop (c) results Figure 47 shows the current-mode flyback Figure 47. The power-stage (a) and error-amplifier (b) plots sum to produce the control-loop plot (c) for the current-mode flyback idealized straight-line plots of the power stage, error frequency response. amplifier and control loop.

Texas Instruments 28 September 2016 Bandwidth versus transient response With no ESR, slew rate or duty-cycle limiting, Equation 125 calculates t as: Transient response is directly related to the P 1 bandwidth of the control loop. With no ESR, slew t = P 4⋅ f rate or duty-cycle limiting, the initial response time is C (125) one-fourth the effective control-loop period. This is 1 t = = 25µs the equivalent first quarter of a sinusoidal response P 4⋅10kHz

at the unity-gain frequency. The peak voltage will vary Current-mode single-pole approximation with Equation based on the topology and damping, but is easily 126 calculates VP as: predictable with a surprising degree of accuracy. ΔI VP = It is important to verify the performance over all 2⋅π ⋅ fC ⋅C OUT operating conditions. Duty-cycle limiting can cause (126) 5A V = =180mV a significant droop when operating the control loop P 2⋅π ⋅10kHz ⋅440µF outside its linear range. Reference [11] is an Applied Current-mode critically damped (as shown in Power Electronics Conference and Exhibition (APEC) Figure 49) with Equation 127 calculates V as: Figure 48 paper on the topic, which includes design methods P ΔI to meet transient response. Figure 48 shows a VP = e⋅π ⋅ fC ⋅C OUT typical frequency-response plot, while Figure 49 (127) 5A shows the transient response. V = =130mV P e⋅π ⋅10kHz ⋅440µF

60 135 Voltage-mode control with Equation 128 calculates VP

40 90 as: Δ 20 45 I VP = 8⋅ fC ⋅C OUT

0 0 (°) Phase

Figure 49 (dB) Magnitude f 5A (128) -20 C -45 V = =140mV P 8⋅10kHz ⋅440µF -40 -90 0.01 0.1 1 10 100 1000

Frequency (kHz) Practical limitations of error Figure 48. The current-mode bandwidth is set at 10 kHz for this amplifiers example. The error-amplifier bandwidth can limit the maximum

loop-crossover frequency. As you can see from Figure 50, where the closed-loop gain intersects the ∆I open-loop gain plot, the phase drops quickly. You will need a wider-bandwidth op amp for voltage mode due to Type III compensation.

vP tP

Figure 49.The corresponding current-mode transient response shows

tP = 25 μs and VP = 130 mV for a load step of ∆I = 5 A.

Texas Instruments 29 September 2016 Figure 50

bandwidth, a voltage-mode converter can approach Error amplifier BW limit 80 270 one-third the switching frequency and have adequate

60 225 phase and gain margin. An ideal current-mode buck can

40 180 achieve one-fifth the switching frequency with critical damping. Higher crossover frequency results in higher 20 135 Phase (°) Phase

Magnitude (dB) Magnitude Figure 52 noise sensitivity and possible switching jitter. A general 0 90 rule of thumb is one-fifth to one-tenth the switching -20 45 0.01 0.1 1 10 100 1000 frequency. The right-half-plane zero usually limits boost Frequency (kHz) and buck-boost converters operating in CCM. Figure 50: The error amplifier’s open-loop gain and bandwidth set a hard limit for the closed-loop response. Voltage-mode control loop 80 180 Practical limitations of optocouplers 60 135 Resistance in series with the output transistor forms a 40 90 pole in the kilohertz range. The pole is dependent on 20 45 bias current and output resistance. As you can see in Magnitude (dB) Magnitude

0 0 (°) Margin Phase

Figure 51, higher output resistance causes the pole fSW = 200 kHz -20 -45 to occur at a lower frequency. In a simplified analysis, 0.01 0.1 1 10 100 1000 we used a single pole with an external capacitor. With Frequency (kHz) no external capacitor the roll-off approaches –40 dB/ Figure 52. The voltage-mode control loop shows the phase going Figure 51 to zero near the switching frequency. The available gain and phase decade, with phase shift at higher frequencies of margin set an upper limit on the control-loop bandwidth. –180 degrees. This is more of an issue for forward- or other buck-derived topologies with higher crossover Discontinuous versus continuous frequencies. conduction-mode DCM occurs when the inductor current dwells at zero Opto frequency response 20 45 before the end of the switching cycle. DCM is a normal condition for diode-rectified circuits when the load drops 0 Gain 0 Figure 53 to a light level. DCM causes a reduction in bandwidth, -20 -45 which you can clearly see in Figure 53 for the current- -40 R = 1 kΩ -90

P (°) Phase RP = 5 kΩ mode response. In general, if the control loop is stable in Magnitude (dB) Magnitude -60 -135 RP = 20 kΩ Phase CCM, it will also be stable in DCM. -80 -180 1 10 100 1000 Frequency (kHz) Current-mode buck power stage 40 90 Figure 51. The optocoupler pole moves toward lower frequencies at 20 45 lower bias currents using higher resistor values. Gain 0 0 Practical limitations due to the -20 -45

-40 -90 (°) Phase

switching frequency (dB) Magnitude CCM Phase -60 -135 The maximum crossover frequency is some fraction DCM -80 -180 of the switching frequency. Figure 52 shows the 0.01 0.1 1 10 100 1000 Frequency (kHz) control-loop phase margin going quickly negative at the switching frequency. With a sufficient error-amplifier Figure 53. The current-mode power-stage bandwidth is reduced in DCM.

Texas Instruments 30 September 2016 Figure 55 Figure 54

For the voltage-mode response shown in Figure 54, the order of the filter is reduced in DCM, since the inductor now acts as a current source.

Voltage-mode buck power stage

40 90 20 45 Gain 0 0 Figure 55. The converter acts as a load on the input filter. For stability, -20 -45 filter OUTZ << converter ZIN. -40 -90 (°) Phase Magnitude (dB) Magnitude -60 CCM Phase -135 DCM Equations 132 and 133 calculate the characteristic -80 -180 source impedance and resonant frequency, 0.01 0.1 1 10 100 1000 respectively: Frequency (kHz)

Figure 54. The voltage-mode power-stage bandwidth is also reduced LIN Z S = (132) in DCM. CIN

1 DCM duty cycle fS = (133) 2 ⋅π ⋅ LIN ⋅CIN Equations 129 through 131 show the duty-cycle

equations for DCM. To determine the mode The converter exhibits a negative input impedance, boundary, you can set the CCM and DCM duty- which is lowest at the minimum input voltage cycle equations equal to each other. (Equation 134):

V V 2 2⋅ L⋅ fSW ⋅ IOUT ⋅VOUT IN IN Buck: D = (129) Z IN = − = − (134) I P VIN ⋅(VIN −VOUT ) IN OUT

Equation 135 gives the damping factor for the input 2⋅ L⋅ f ⋅ I ⋅(V −V ) Boos t: D = SW OUT OUT IN (130) filter as: VIN 1 ⎛ R + R Z ⎞ ζ = ⋅⎜ L C + S ⎟ (135) 2⋅ L⋅ f ⋅ I ⋅V 2 ⎜ Z Z ⎟ Buck -boost: D = SW OUT OUT (131) ⎝ S IN ⎠ VIN where RL is the input wiring resistance and RC is the Input-filter stability and second- series resistance of the input capacitors. The term

stage filters ZS/ZIN will always be negative due to ZIN.

Input-filter stability When = 1, the input filter is critically damped, but this value may be difficult to achieve with practical The line impedance and input capacitors form a ζ component values. When < 0.2, the input filter resonant circuit when connecting the converter will exhibit significant ringing. If is zero or negative, to a remote input power source through a wiring ζ there is not enough resistance in the circuit and the harness, as shown in Figure 55. Typical wiring ζ inductance is on the order of 0.5 μH/m. An input input filter will sustain an oscillation. inductor reduces reflected ripple current back to the source. In order to minimize overshoot,

make CIN > 10·LIN.

Texas Instruments 31 September 2016 Figure 56

The general guidelines are:

• Converter input impedance – switching regulators exhibit a negative input impedance, which is lowest at the minimum input voltage. • Filter output impedance – an underdamped LC filter Figure 56. A buck regulator with second-stage filter. exhibits a high output impedance at resonance. The general guidelines are: • Relative impedance – for stability, the filter’s output • Filter capacitors – make C smaller than C . C is impedance must be much less than the converter’s input OUT1 OUT2 OUT1 typically ceramic. impedance.

• Filter inductors – make L2 smaller than L1. Make sure that I is greater than I max. When operating near the minimum input voltage, SAT OUT you may need an aluminum electrolytic capacitor • Filter resonance – make the second-stage filter resonance three times larger than the crossover frequency. across CIN to damp the input. You should evaluate any parallel capacitor for its root-mean-square • Damping – damp the second-stage filter to a Q of 1. (RMS) current rating. The current will split between the ceramic and aluminum capacitors based on the Primary-side compensation relative impedance at the switching frequency. considerations Primary-side compensation Second-stage filter Figure 57 illustrates a method that uses the Figure 56 shows the power stage of a buck primary-side inverting amplifier to implement regulator followed by a second-stage filter. The first- Figure 57 frequency compensation. Though not often stage capacitor is sized to handle the output RMS used alone, it can complement secondary-side current, while the second-stage capacitor reduces compensation. If the output-voltage accuracy is not the ripple voltage and provides energy storage critical, a series Zener and resistor can directly drive for the load transient. This method is particularly the optocoupler from the output voltage. useful for boost- or buck-boost-type outputs, which have high ripple voltage due to the pulsing rectifier VC current. VCC You must include the effect of the second-stage RF filter in the control-loop analysis. Account for the RI total output capacitance and use the capacitance - to determine the loop bandwidth. A second-stage + VREF RE resonance at too low a frequency can cause the control loop to go unstable, even when taking Figure 57. Primary-side compensation can provide additional control of the frequency response. feedback at the first-stage output.

Texas Instruments 32 September 2016 High-bandwidth configurationFigure 60 Phase boost Figure 58 shows a configuration where the Figure 60 shows how a feed-forward network

optocoupler emitter is at a virtual ground of VREF. across RD adds phase boost for increased Figure 58 This configuration minimizes the pole due to the bandwidth. This method cancels the inherent pole optocoupler’s parasitic capacitance, since the of the optocoupler. collector-to-emitter voltage does not change. This V′ configuration is also particularly useful in forward OUT RD CFF converters to achieve high bandwidth; we used it R in the section covering the isolated current-mode FF forward example.

RFBT CCOMP VCC TL431 V C RFBB RP Figure 60. Placing a lead network across the optocoupler’s - gain-setting resistor adds phase boost.

+ VREF RE Zener bias Figure 58. The optocoupler emitter is biased at V of the primary- REF Figure 61 shows how Zener bias for R eliminates side amplifier in the high-bandwidth configuration. D Figure 61 the high-frequency feedback path for secondary- side compensation. This method is common for Secondary-side compensation higher output voltages to prevent exceeding the considerations TL431’s voltage rating. RS and ZS can also bias the ESR zero compensation optocoupler from the rectified secondary voltage. Figure 59 shows how a resistor-capacitor (RC) V′OUT pole to the optocoupler can cancel the ESR zero Z RS Figure 59 RD S of the output capacitor, which is helpful when RFBT using aluminum electrolytic output capacitors CHF with high ESR. We used this configuration in the

section covering the isolated current-mode forward CCOMP RCOMP

example. TL431 RFBB

V′OUT C RS RD S Figure 61. A Zener biases the optocoupler with a fixed voltage. Real-world compensation example

Switching regulator with poor compensation RFBT CCOMP Figure 62 shows a basic current-mode buck TL431 regulator, which uses a transconductance amplifier. RFBB After building the circuit, it showed a fairly high

Figure 59. A simple RC to the optocoupler allows for ESR zero crossover frequency with low phase margin. compensation.

Texas Instruments 33 September 2016 Figure 64 (a)

DC bias of the output ceramic capacitors reduced the effective capacitance substantially. A switched Power stage 40 45 resistive load exercised the loop at its maximum 20 0 Figure 62 bandwidth. Bench measurements of the control loop agreed with the transient response shown 0 -45

in Figure 63, where low phase margin results in -20 -90 Phase (°) Phase

output-voltage ringing. (dB) Magnitude Figure 64 (b) -40 -135 0.1 μF -60 -180 3.3 μH 0.1 1 10 100 1000 VIN BOOT VOUT VIN PH Frequency (kHz) 15 μF 31.6 kΩ GND U1 47 μF (a) VSENSE EN COMP 10 kΩ SS/TR Figure 63 RT/CLK 5 kΩ Error amplifier 22 μF 60 270 10 nF 100 kΩ 1 nF effective capacitance 40 225

Figure 62. A synchronous buck regulator exhibits poor transient 20 180 performance. 0 135 Phase (°) Phase Figure 64 (c) (dB) Magnitude -20 90 -40 45 0.1 1 10 100 1000 Frequency (kHz) IOUT (b)

VOUT Control loop 60 135

40 90

Figure 63. An underdamped transient response indicates low phase 20 45 margin. 0 0 Phase (°) Phase

By observing the frequency response in Figure (dB) Magnitude -20 -45 64, you can analyze the performance. In -40 -90 Figure 64a, the phase is headed toward –180 0.1 1 10 100 1000 degrees, indicating relatively high internal slope Frequency (kHz)

compensation. In Figure 64b, the error-amplifier (c) zero appears to be a bit high and the mid-band gain is around 3 dB. In Figure 64c, the crossover Figure 64. The power-stage (a) and error-amplifier (b) plots sum to produce the control-loop plot (c), showing high bandwidth and low frequency is 95 kHz, with only 20 degrees of phase margin. phase margin.

Texas Instruments 34 September 2016 Figure 67 (a)

Switching regulator with revised compensation Power stage Figure 65 Adjusting the compensation network of the error 40 45 amplifier achieves well-damped performance. 20 0 Figure 65 shows the revised circuit, while 0 -45 Figure 66 shows the improved transient response. -20 -90

0.1 μF (°) Phase

Magnitude (dB) Magnitude -40 -135 3.3 μH VIN BOOT VOUT VIN PH -60 -180 15 μF Figure 67 (b) 31.6 kΩ 0.1 1 10 100 1000 GND U1 47 μF VSENSE Frequency (kHz) EN COMP 10 kΩ SS/TR (a) Figure 66 RT/CLK 1 kΩ 22 μF 10 nF 100 kΩ 10 nF effective capacitance Error amplifier Figure 65. Adjusting only two compensation components improved 60 270 the performance. 40 225

20 180

0 135 Phase (°) Phase

I (dB) Magnitude OUT -20 90

Figure 67 (c) -40 45 0.1 1 10 100 1000 V OUT Frequency (kHz) (b)

Figure 66. A critically damped transient response indicates good Control loop phase margin. 60 135

40 90

By observing the frequency response in 20 45 Figure 67, you can analyze the performance. 0 0 In Figure 67a, there is no external adjustment for (°) Phase Magnitude (dB) Magnitude -20 -45 slope compensation. All power-stage components are the same. In Figure 67b, decreasing R -40 -90 COMP 0.1 1 10 100 1000 lowers the mid-band gain, which will lower the Frequency (kHz)

crossover frequency. Increasing CCOMP to move the error-amplifier zero to a lower frequency increases (c) the phase margin at crossover. In Figure 67c, the Figure 67. By leaving the power stage (a) as is and adjusting the crossover frequency is now 30 kHz, with 67 degrees error-amplifier (b) response, the control loop (c) exhibits acceptable of phase margin. gain and phase margin.

Texas Instruments 35 September 2016 Summary 5. Dixon, L.H. “Control Loop Design.” Texas Instruments This paper covered CCM operation of voltage- and Power Supply Design Seminar SEM800, 1991. current-mode converters. Standard linear feedback 6. Dixon, L.H. “Control Loop Cookbook.” Texas Instruments amplifiers for nonisolated and isolated converters Power Supply Design Seminar SEM1100, 1996. enable a wide range of compensation techniques. 7. Ridley, R. “A More Accurate Current-Mode Control We hope that you can use the design examples of Model.” Texas Instruments Power Supply Design popular topologies we have given here. Seminar SEM1300, 1999. To summarize the compensation design method 8. Mitchell, D., and Mammano, B. “Designing Stable simply: Control Loops.” Texas Instruments Power Supply Design • Identify the poles and zeros of the power stage. Seminar SEM1400, 2001. • Cancel the power stage poles and zeros with zeros and 9. Sheehan, R. “Current Mode Modeling – Reference poles in the error amplifier. Guide.” (SNVA542), Texas Instruments, 2007. • Adjust the gain for best performance. 10. Sheehan, R. “Understanding and Applying Current-Mode Control Theory.” (SNVA555). Texas Instruments, 2007. Additional information 11. Bag, S., Mukhopadhyay, S., Samanta, S., Sheehan, 1. Dixon, L.H. “Closing the Feedback Loop.” Texas R., and Roy, T. “Frequency Compensation and Power Instruments Power Supply Design Seminar SEM300, Stage Design for Buck Converters to Meet Load 1984. Transient Specifications.” 2014 IEEE Applied Power 2. Dixon, L.H. “Current-Mode Control of Switching Power Electronics Conference and Exhibition – APEC 2014, Supplies.” Texas Instruments Power Supply Design 1024-1031. Seminar SEM400, 1985. 12. Meeks, D. “Loop Stability Analysis of Voltage Mode 3. Dixon, L.H. “The Right-Half-Plane Zero – A Simplified Buck Regulator with Different Output Capacitor Types Explanation.” Texas Instruments Power Supply Design – Continuous and Discontinuous Modes.” Texas Seminar SEM500, 1986. Instruments Application Report (SLVA301), April 2008. 4. Mammano, R. “Isolating the Control Loop.” Texas Instruments Power Supply Design Seminar SEM700, 1990.

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